From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 27756 invoked by alias); 20 Feb 2013 02:49:10 -0000 Received: (qmail 27729 invoked by uid 22791); 20 Feb 2013 02:49:08 -0000 X-SWARE-Spam-Status: No, hits=-2.9 required=5.0 tests=AWL,BAYES_00,KHOP_SPAMHAUS_DROP,KHOP_THREADED,RP_MATCHES_RCVD,TW_EG X-Spam-Check-By: sourceware.org Received: from usmamail.tilera.com (HELO USMAMAIL.TILERA.COM) (12.216.194.151) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 20 Feb 2013 02:49:01 +0000 Received: from [10.200.0.56] (124.207.145.166) by USMAExch2.tad.internal.tilera.com (10.3.0.33) with Microsoft SMTP Server (TLS) id 14.0.722.0; Tue, 19 Feb 2013 21:48:58 -0500 Message-ID: <51243991.4040304@tilera.com> Date: Wed, 20 Feb 2013 02:49:00 -0000 From: Jiong Wang User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:17.0) Gecko/20130107 Thunderbird/17.0.2 MIME-Version: 1.0 To: Yao Qi CC: Joel Brobecker , , Walter Lee Subject: Re: [RFC/TileGX 2/6] simplify the handling of skip prologue for plt stub References: <50F91516.6010204@tilera.com> <20130118131511.GF3564@adacore.com> <50F9664D.2090008@tilera.com> <511F0FE9.8030300@codesourcery.com> In-Reply-To: <511F0FE9.8030300@codesourcery.com> Content-Type: multipart/mixed; boundary="------------060103040408060907050703" Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2013-02/txt/msg00525.txt.bz2 --------------060103040408060907050703 Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit Content-length: 2368 > On 01/18/2013 11:12 PM, Jiong Wang wrote: >> this is because tilegx skip_prologue will invoke >> tilegx_analyze_prologue, which >> will prefetch 32*8 bytes. >> >> while for when the address is in plt stub, you can see it near the >> eh_frame_hdr section >> >> [14] .plt 0000000000010a00 000a00 0000a0 28 >> AX 0 0 64 >> ... >> [16] .eh_frame_hdr 0000000000010ac0 000ac0 000024 00 A 0 0 4 >> [17] .eh_frame 0000000000010ae8 000ae8 0000b4 00 A >> 0 0 8 >> >> the .eh_frame_hdr aligns to 4, there is a hole between .eh_frame_hdr and >> .eh_frame, and this >> will cause trouble for section_table_xfer_memory_partial. >> >> after fetch memory starting from 0x10ac0 to 0x10ae4, then the memaddr >> will be 0x10ae4 in section_table_xfer_memory_partial, >> while this function did not consider this hole situation, so goes to >> line 666, error occured. > > Wang Jiong, > > AFAICT, the root cause of this problem is GDB prefetches too much > contents in one time that exceeds the boundary of a section. > > At the beginning of tilegx_analyze_prologue, I notice this comment > > /* To cut down on round-trip overhead, we fetch multiple bundles > at once. These variables describe the range of memory we have > prefetched. */ > > Can't we fetch one bundle in one time? Fetching multiple bundles > causes this problem, so we have to disable it. I think we should keep prefetching multiple instruction bundles to cut down on round-trip overhead, just as the comment explained. > > Even we still decide to use fetching multiple bundle in one time, we > should take care of the boundary and existing code does this, see this > comment, > > /* Figure out how many bytes to fetch. Don't span a page > boundary since that might cause an unnecessary memory > error. */ > > Looks existing code takes care of not crossing the page boundary, > similarly, we should also take care of not crossing the section > boundary. What do you think? thanks, check section boundary looks better, and I think we can remove the old page boundary check, please CR the new patch gdb/ChangeLog: * tilegx-tdep.c (tilegx_skip_prologue): when prefetching multiple instruction bundles, check section boundary instead of page boundary. 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