From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8330 invoked by alias); 14 Nov 2012 02:23:14 -0000 Received: (qmail 8321 invoked by uid 22791); 14 Nov 2012 02:23:13 -0000 X-SWARE-Spam-Status: No, hits=-4.5 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,KHOP_THREADED,RCVD_IN_HOSTKARMA_W,RCVD_IN_HOSTKARMA_WL,TW_XF X-Spam-Check-By: sourceware.org Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 14 Nov 2012 02:23:06 +0000 Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1TYSd7-0001DS-5e from Yao_Qi@mentor.com ; Tue, 13 Nov 2012 18:23:05 -0800 Received: from SVR-ORW-FEM-04.mgc.mentorg.com ([147.34.97.41]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 13 Nov 2012 18:23:04 -0800 Received: from qiyao.dyndns.org (147.34.91.1) by svr-orw-fem-04.mgc.mentorg.com (147.34.97.41) with Microsoft SMTP Server id 14.1.289.1; Tue, 13 Nov 2012 18:23:03 -0800 Message-ID: <50A30070.2030700@codesourcery.com> Date: Wed, 14 Nov 2012 02:23:00 -0000 From: Yao Qi User-Agent: Mozilla/5.0 (X11; Linux i686; rv:15.0) Gecko/20120911 Thunderbird/15.0.1 MIME-Version: 1.0 To: Joel Brobecker CC: Subject: Re: [PATCH/arm] Backtrace through exception frames on arm/cortex-m target References: <1352816140-3221-1-git-send-email-yao@codesourcery.com> <20121113154926.GB5103@adacore.com> In-Reply-To: <20121113154926.GB5103@adacore.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2012-11/txt/msg00354.txt.bz2 On 11/13/2012 11:49 PM, Joel Brobecker wrote: >> 2012-11-13 Daniel Jacobowitz >> > Yao Qi >> > >> > * arm-tdep.c (arm_addr_bits_remove): Do not adjust the low >> > bit of EXC_RETURN. >> > (arm_m_exception_cache, arm_m_exception_this_id) >> > (arm_m_exception_prev_register, arm_m_exception_unwind_sniffer) >> > (arm_m_exception_unwind): New. >> > (arm_gdbarch_init): Register arm_m_exception_unwind. > Yao, can you add a comment/description for each new function that > you introduce? Sure. We didn't add comments to these functions because they are installed to 'struct frame_unwind' to compose a unwinder for a specific type of frames. The situation is similar to gdbarch hook functions, so I add comment in the similar way, for example, +/* Implementation of function hook 'this_id' in + 'struct frame_uwnind'. */ + +static void +arm_m_exception_this_id (struct frame_info *this_frame, besides them, I also add some comments on the code, point readers to the right section of the right manual, which is more useful, IMO. Below is the updated patch. -- Yao gdb: 2012-11-14 Daniel Jacobowitz Yao Qi * arm-tdep.c (arm_addr_bits_remove): Do not adjust the low bit of EXC_RETURN. (arm_m_exception_cache, arm_m_exception_this_id) (arm_m_exception_prev_register, arm_m_exception_unwind_sniffer) (arm_m_exception_unwind): New. (arm_gdbarch_init): Register arm_m_exception_unwind. --- gdb/arm-tdep.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 122 insertions(+), 0 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 1a67366..01af187 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -448,6 +448,11 @@ arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr) static CORE_ADDR arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) { + /* On M-profile devices, do not strip the low bit from EXC_RETURN + (the magic exception return address). */ + if (gdbarch_tdep (gdbarch)->is_m && (val & 0xfffffff0) == 0xfffffff0) + return val; + if (arm_apcs_32) return UNMAKE_THUMB_ADDR (val); else @@ -2926,6 +2931,121 @@ struct frame_unwind arm_stub_unwind = { arm_stub_unwind_sniffer }; +/* Put here the code to store, into CACHE->saved_regs, the addresses of + the saved registers of frame described by THIS_FRAME. CACHE is + returned. */ + +static struct arm_prologue_cache * +arm_m_exception_cache (struct frame_info *this_frame) +{ + struct gdbarch *gdbarch = get_frame_arch (this_frame); + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + struct arm_prologue_cache *cache; + CORE_ADDR unwound_sp; + LONGEST xpsr; + + cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); + cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); + + unwound_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); + + /* The hardware saves eight 32-bit words, comprising xPSR, ReturnAddress, + LR (R14), R12, R3, R2, R1, R0. See details in "B1.5.6 Exception entry + behavior" in "ARMv7-M Architecture Reference Manual". */ + cache->saved_regs[0].addr = unwound_sp; + cache->saved_regs[1].addr = unwound_sp + 4; + cache->saved_regs[2].addr = unwound_sp + 8; + cache->saved_regs[3].addr = unwound_sp + 12; + cache->saved_regs[12].addr = unwound_sp + 16; + cache->saved_regs[14].addr = unwound_sp + 20; + cache->saved_regs[15].addr = unwound_sp + 24; + cache->saved_regs[ARM_PS_REGNUM].addr = unwound_sp + 28; + + /* If bit 9 of the saved xPSR is set, then there is a four-byte + aligner between the top of the 32-byte stack frame and the + previous context's stack pointer. */ + cache->prev_sp = unwound_sp + 32; + if (safe_read_memory_integer (unwound_sp + 28, 4, byte_order, &xpsr) + && (xpsr & (1 << 9)) != 0) + cache->prev_sp += 4; + + return cache; +} + +/* Implementation of function hook 'this_id' in + 'struct frame_uwnind'. */ + +static void +arm_m_exception_this_id (struct frame_info *this_frame, + void **this_cache, + struct frame_id *this_id) +{ + struct arm_prologue_cache *cache; + + if (*this_cache == NULL) + *this_cache = arm_m_exception_cache (this_frame); + cache = *this_cache; + + /* Our frame ID for a stub frame is the current SP and LR. */ + *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame)); +} + +/* Implementation of function hook 'prev_register' in + 'struct frame_uwnind'. */ + +static struct value * +arm_m_exception_prev_register (struct frame_info *this_frame, + void **this_cache, + int prev_regnum) +{ + struct gdbarch *gdbarch = get_frame_arch (this_frame); + struct arm_prologue_cache *cache; + + if (*this_cache == NULL) + *this_cache = arm_m_exception_cache (this_frame); + cache = *this_cache; + + /* The value was already reconstructed into PREV_SP. */ + if (prev_regnum == ARM_SP_REGNUM) + return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp); + + return trad_frame_get_prev_register (this_frame, cache->saved_regs, + prev_regnum); +} + +/* Implementation of function hook 'sniffer' in + 'struct frame_uwnind'. */ + +static int +arm_m_exception_unwind_sniffer (const struct frame_unwind *self, + struct frame_info *this_frame, + void **this_prologue_cache) +{ + CORE_ADDR this_pc = get_frame_pc (this_frame); + + /* No need to check is_m; this sniffer is only registered for + M-profile architectures. */ + + /* Exception frames return to one of these magic PCs. Other values + are not defined as of v7-M. See details in "B1.5.8 Exception return + behavior" in "ARMv7-M Architecture Reference Manual". */ + if (this_pc == 0xfffffff1 || this_pc == 0xfffffff9 || this_pc == 0xfffffffd) + return 1; + + return 0; +} + +/* Frame unwinder for M-profile exceptions. */ + +struct frame_unwind arm_m_exception_unwind = { + SIGTRAMP_FRAME, + default_frame_unwind_stop_reason, + arm_m_exception_this_id, + arm_m_exception_prev_register, + NULL, + arm_m_exception_unwind_sniffer +}; + static CORE_ADDR arm_normal_frame_base (struct frame_info *this_frame, void **this_cache) { @@ -10218,6 +10338,8 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg); /* Add some default predicates. */ + if (is_m) + frame_unwind_append_unwinder (gdbarch, &arm_m_exception_unwind); frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind); dwarf2_append_unwinders (gdbarch); frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind); -- 1.7.7.6