From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id z1RkI5v5D2CTJQAAWB0awg (envelope-from ) for ; Tue, 26 Jan 2021 06:14:35 -0500 Received: by simark.ca (Postfix, from userid 112) id 7CFEB1EF80; Tue, 26 Jan 2021 06:14:35 -0500 (EST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER, UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id A50BB1E940 for ; Tue, 26 Jan 2021 06:14:32 -0500 (EST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E94283857C62; Tue, 26 Jan 2021 11:14:31 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E94283857C62 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1611659672; bh=NoHYd/dSp9Rtpi/ATfTfKR84PtIyeslvyAxl72QL39k=; h=Subject:To:References:Date:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=fZ2TAnsGHXlMMgqM4Oj4xsaOHo17MLTFcCMzjaS7t2uUQr1Uk/2uR5OssBo0pqpwC niz188UnB+2vRlh0mdeq4Srz1QEPn1tt3ei6ohM47fI1q6bb78HZh0J1LyMw8YqGSp AuI6QMj5/KyQU+g2GMalmpEejfv4FTiu5PX+5h1U= Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2067.outbound.protection.outlook.com [40.107.22.67]) by sourceware.org (Postfix) with ESMTPS id DD2853857C62 for ; Tue, 26 Jan 2021 11:14:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org DD2853857C62 Received: from MR2P264CA0130.FRAP264.PROD.OUTLOOK.COM (2603:10a6:500:30::22) by DBBPR08MB4345.eurprd08.prod.outlook.com (2603:10a6:10:c7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3784.11; Tue, 26 Jan 2021 11:14:23 +0000 Received: from VE1EUR03FT034.eop-EUR03.prod.protection.outlook.com (2603:10a6:500:30:cafe::68) by MR2P264CA0130.outlook.office365.com (2603:10a6:500:30::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3784.16 via Frontend Transport; Tue, 26 Jan 2021 11:14:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; sourceware.org; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;sourceware.org; dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by VE1EUR03FT034.mail.protection.outlook.com (10.152.18.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3784.11 via Frontend Transport; Tue, 26 Jan 2021 11:14:23 +0000 Received: ("Tessian outbound 587c3d093005:v71"); Tue, 26 Jan 2021 11:14:22 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: c3a5fe7e0634465c X-CR-MTA-TID: 64aa7808 Received: from f91fdb956ffb.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id E19AAAE8-AC44-42B6-A992-931904821F06.1; Tue, 26 Jan 2021 11:14:03 +0000 Received: from EUR04-DB3-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id f91fdb956ffb.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Tue, 26 Jan 2021 11:14:03 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=AKrTcYMoxh0scX8uRWKbLUnRnrDGNFskwEMiHzsqz1RsQ/G9VQlT41PrRb/BtCGrSEEoUGqa34Zd5rGjYLo3NiFKSwb78uuHp5xRJm8j7xcecN4UVGpDtfLlJeZAdNSD2FBNpsWKKYBIMdO2D7F5JMe4GPjmNl7F0xM4TVewwhW1nM8ut7GumyjeVCOrmWjfsalOc3X3CVLW8cMcyjSbqikddQZSmBYDq0kHrxtiwcfYq8xCRwspTH7VAvVA4lB80/tbQVp+XdReb3tzZMB7oancvIg5e406AFCKgfqDLubux7d5JV+xTcjcWTU7hbZ/iJ58tPzVCrec/Zl039yEWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=NoHYd/dSp9Rtpi/ATfTfKR84PtIyeslvyAxl72QL39k=; b=dUGdmMFfPg3Z8RhYwChEzoyFuLBBL3ZQ3dnACQcdh9keJ+Z11rRQCjTO7sKkhkZconWqoOn6Urmj9EGKr3nC0sR8NwYeB2bJ1c8WqMFoZcPfXD3CoAbWYm5sDCFz1VXxu576okbEiPEoV17lj1Ngyb+PZZlMsrgdlnH/qRH1zGbhiRM3mKENguwQzcw+WlKkVho7D4utRBUT4owGSz5E1pWw6iAWHadxEMsj8Mx/FURHwoLdAdi9AHJlPyXNZjC2ri47W3VA0PGMxxWPS8EDD/OoB+Ea0YvJYFIH2WXshBxt6PaY1f08kE4AdXbO0r2582h/Hcj0lHzbKpGNZqV5uQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none Authentication-Results-Original: arm.com; dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=arm.com; Received: from AM6PR08MB3157.eurprd08.prod.outlook.com (2603:10a6:209:48::24) by AM6PR08MB4213.eurprd08.prod.outlook.com (2603:10a6:20b:8e::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3784.11; Tue, 26 Jan 2021 11:14:02 +0000 Received: from AM6PR08MB3157.eurprd08.prod.outlook.com ([fe80::4847:9e54:1f0a:b6cb]) by AM6PR08MB3157.eurprd08.prod.outlook.com ([fe80::4847:9e54:1f0a:b6cb%7]) with mapi id 15.20.3784.017; Tue, 26 Jan 2021 11:14:02 +0000 Subject: Re: [Patch] GDB: aarch64: Add ability to step over a BR/BLR instruction To: Luis Machado References: <9226b8ae-aaea-65c3-3e86-f607b11fd375@linaro.org> <9EACDC38-BB8D-4804-AD19-057E3309819A@arm.com> <3d86bcb9-dedd-6eb2-7cff-e8349d4b20da@palves.net> <9efc84c3-d4fb-03d6-8612-600cc2f74e65@linaro.org> Message-ID: <4e5f7899-6a44-c18b-45ae-31228a6f5c20@arm.com> Date: Tue, 26 Jan 2021 11:13:59 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 In-Reply-To: <9efc84c3-d4fb-03d6-8612-600cc2f74e65@linaro.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-Originating-IP: [217.140.106.55] X-ClientProxiedBy: LNXP265CA0071.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:5d::35) To AM6PR08MB3157.eurprd08.prod.outlook.com (2603:10a6:209:48::24) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [10.2.78.69] (217.140.106.55) by LNXP265CA0071.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:5d::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3805.16 via Frontend Transport; Tue, 26 Jan 2021 11:14:01 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: d54e3b12-8003-4a8e-9911-08d8c1eb88fb X-MS-TrafficTypeDiagnostic: AM6PR08MB4213:|DBBPR08MB4345: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:9508;OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: WPWCtpnlPRsRY8n3JQfnZBSzgnbx8piB0eCxMKVVzp+D+oL420Yd7TiFLe44mbGPCdGsQN2vEIfAhwa3I68QTZK1WoOjZ17mr96LjI8bGDHOHHGTmyTD0MmZBJx2Ga51r5z+OkIg8bnfvL/svkx0+B8KCria7QTXnfByvNPF//Wg+rxXESyNElGK8utBk5z6IVmVujQkvwNiJIIqoN3z9lYpmrbykERh/Ql9KMtypVsgpbWN2o7rIBkyXxJNwc2dD0VOrMG13xfdOPuytGJ7C2/x0RrU4L6hptbwfaO11a8creW5Cosd4OzwmFA3dspuber6/PVEGVJNzXAZcI0n9nbjHymTSXcI7YbCnRNsDs/s6lyMJK7lPm8Rfnpdxsan/2jN8xKxIkCqJe/+WnF4sJXWJhCPXNOlL5hf7WbG5B2ISXQrXFGzvc9klAsstxq6h4f5WCxIU5Ap260c7JIeFXtAMBcRLLdlO8w+HjMfwzE= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM6PR08MB3157.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(396003)(366004)(136003)(376002)(346002)(39850400004)(956004)(2616005)(31696002)(8676002)(52116002)(44832011)(36756003)(86362001)(6916009)(2906002)(66556008)(83380400001)(66476007)(66946007)(4326008)(26005)(31686004)(5660300002)(6486002)(8936002)(478600001)(30864003)(316002)(16526019)(16576012)(186003)(53546011)(54906003)(45980500001)(43740500002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: =?Windows-1252?Q?TF0fkzEyIcEFeNzqIPK81NwFPz7+Lv31nLxJuG9N264ps3dgO4kmfxPy?= =?Windows-1252?Q?azybBExTl9+ZB1m9ozgmDPLI8c9+aCqdRyaErrN3hU1gj9kfxC+LoP1D?= =?Windows-1252?Q?lNvlJt9FUCvRYA8T2VAC+k4YzXSRXQLnOu3XcYSt5Q9xPZrKXheHNh0h?= =?Windows-1252?Q?8+fI7PCPwrNTD3Ah5cNExNjndAyAJ3Dn8KtCoR7sCMUEO5EIiFXJYF5z?= =?Windows-1252?Q?Tt7WG4SFwLDbYqadIcC1OW21SPdwEfL7yRTRBgthIjez2Me41Kz92v3P?= =?Windows-1252?Q?WYtzC82lzYre7Hktj9cf+ILv2+VAyeWH//PVsnAoCPJ6Js8NIUy5Hgsi?= =?Windows-1252?Q?NvG+4DnEqfWHraKZvc/kpsHa8MAxek4pG2YjJknNvRA5Ruiy2EgaOxvk?= =?Windows-1252?Q?1NcYTJ22hDcGNzK5BII+RJh2QlScKhEpfDxzNbHFCe/MwmtSCzv4egio?= =?Windows-1252?Q?RMTedIRgRFvAN4sOa66m6UQ3wdazjanA8MkOVbJJ0iZExOp0Wmfy/PGQ?= =?Windows-1252?Q?4sWXEts0YoX60D80xMLixtGP+st9yDK4ueGwdNonRdpwWUVocKHqwGNs?= =?Windows-1252?Q?kWrrYnF/n03+1cJ8WgSN+48zTI7d/61HFsYPHCz9J+U4AiH6QaTV1voK?= =?Windows-1252?Q?8qgXb690ykHEYtdasGfVEWF+OM7PXZI9Zf9fkXgeXQFZEFyu8HCISDb9?= =?Windows-1252?Q?GZcybRpnnJAqaOAd2X5H+xTPedIK3gqbD9Pcr6JM/4mlHXgVN5yeGYig?= =?Windows-1252?Q?vuZS6+mh+OJM+MnNt/Mxt09eeWdzldB8HBeYVGCk6n7aLEThVDl6Pi2u?= =?Windows-1252?Q?eMBBJecpCBQuvYWSWtF2ptG1xwO6MiaKEtTrzPpu2A41e9e0FITr6y4/?= =?Windows-1252?Q?Y7ycY1SpY/+MHCQA6p2Bg+O7W8pPR2BRtMvnf0SjC+BB8+dNUIXEMJsg?= =?Windows-1252?Q?63WyEhM1qT0gA3BBMTxGqbj8/ne+oK/ZtulK+8yKOdSVWa2PXdcV9j1u?= =?Windows-1252?Q?mf51yS2oKE9/+Zf3OfABOEs5JELPvHHF1jxAjznj5vwGPxjqzcK1jrAy?= =?Windows-1252?Q?LSnXYyiyb8qobEAITavDBbsh9KMSyAqMZ9XHNrxW6gX78tFDcA1eHdhc?= =?Windows-1252?Q?E2xl8u/3slOxdcCPCZQS+xAx?= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB4213 Original-Authentication-Results: arm.com; dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: VE1EUR03FT034.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 1f36c057-cf8d-4e3e-fc7a-08d8c1eb7c79 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gmRnxUvQjPxl/W6a8ZM0OqYAZbRhTy7UEEKrcK8CMDzYhbJW+FCfZZjJsx6i9Akd5soX1qwdEhmX2gkaRj3HUY5C+oMQ6t2MqR8NpJaXuZiuaXgOjjuxJlqHS1RwsSWKOfoXQXwzateF+qgwITG2hBCIdzDBbC9/2EAGbjlfj3O291P73sroqxpPdtcIEhON0TsSFUd8Ce1U6dxRD+9SmhbLe9Zxm13z9zNQj8W15MTCXEwWgICJlm/BviqnO2z4RZuW4jx662TF+0xwC0P7hg02+foHTrxp3aZMFJfPPOTGVCQ2cyusoSG6Z7Xheo+KhSw+Vhib9zmcQVg70gUwRRfV7fzg9rBB6rcxzE7ZIUaP93mqIImnDAnIENVDNelyR8eBzjq9wJ9YCRGqBAbDJf+cGgzyUQfo7pY77cvkVCiWjnOQGZfCc8nCPvqdP2mzxbsbYwMl7yglxBR/0gG5UaHoE5Ynddh/gYLnZnGNUNvQ6iOcQkfneYaXAzXrM0WuOjBNjCR4u/QwoxfheYBaG9hXBGfC8sTv1ustkqpT5632hpNULpCbVOYLkhAt6H96Muy//Pzj0WO3erjnlH05VBejCNUmLTPww458DkOoAHegXDwmgoGogrEz/qxBJugc X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(136003)(346002)(396003)(39850400004)(376002)(46966006)(83380400001)(82740400003)(336012)(2906002)(186003)(2616005)(956004)(44832011)(6862004)(478600001)(6486002)(70586007)(30864003)(316002)(16526019)(5660300002)(567974003)(26005)(81166007)(47076005)(86362001)(356005)(31686004)(31696002)(54906003)(16576012)(8676002)(82310400003)(4326008)(70206006)(36756003)(8936002)(53546011)(43740500002); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2021 11:14:23.0921 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d54e3b12-8003-4a8e-9911-08d8c1eb88fb X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT034.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB4345 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Matthew Malcomson via Gdb-patches Reply-To: Matthew Malcomson Cc: nd , gdb-patches Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" On 25/01/2021 18:44, Luis Machado wrote: > Hi Matthew, > > On 1/25/21 3:31 PM, Matthew Malcomson wrote: >> I'd like to ping the below patch. >> >> N.b. When I last sent it up running with >> `--target_board=native-gdbserver` was not working, but I ran the tests >> after a rebase just now and everything now passes. >> >> Given the problem I noticed before was not in this patch (explanation >> in the previous email), and this patch applies cleanly now, is this >> good to go in? > > Sorry. That must have flown under the radar. > > The attached patch does not contain the new test that was submitted > before. Was that an oversight? > > I think the patch looks good. I just want to make sure I know what > pieces to apply. > > Luis Hi Luis, Thanks for looking at it. The lack of the original test is on purpose -- when I was following requests from reviews I noticed that there was already a testcase for displaced stepping that I had missed originally. The attached patch should contain a change to `gdb.arch/insn-reloc.c` which is where I've added tests for the new functionality (rather than as a separate test as before). Thanks, Matthew > >> >> Regards, >> Matthew >> >> On 20/08/2020 13:41, Matthew Malcomson wrote: >>>> On 7/23/20 5:48 PM, Matthew Malcomson wrote: >>>>> + >>>>> +# Test for displaced stepping over the BLR instruction. >>>>> +gdb_test "run" \ >>>>> +� "Starting program.*Breakpoint $decimal.*" \ >>>>> +� "Run until BLR test start" >>>>> + >>>> >>>> Please don't use "run" directly.� Use one of runto, runto_main, >>>> gdb_run_cmd instead.� See amd64-disp-step.exp for example. >>>> >>>> If you use "run" directly, then the testcase won't run against >>>> gdbserver.� Please make sure this passes cleanly: >>>> >>>> �� $ make check \ >>>> ����� RUNTESTFLAGS="--target_board=native-gdbserver" \ >>>> ����� TESTS="gdb.arch/aarch64-disp-stepping.exp" >>>> >>> >>> >>> Thanks for the suggestion, as it turns out trying to use this meant I >>> noticed a >>> bunch of other things, and I couldn't get this to pass cleanly ... >>> >>> I have now found some existing cases for displaced stepping on >>> AArch64 in >>> insn-reloc.c driven by disp-step-insn-reloc.exp. >>> Hence I've added the BR and BLR testcases there rather than making my >>> own test >>> driver. >>> >>> However, it seems the existing tests already show there are some >>> problems >>> with AArch64 displaced stepping on gdbserver -- it seems there's some >>> problem >>> with ensuring the context is the same when running using >>> `--target_board=native-gdbserver`. >>> I see errors on the existing cbz, tbnz, bcond_true, and bcond_false >>> tests. >>> The bl test fails because of an illegal instruction in the >>> bcond_false test >>> that only gets run when the test is failing (swithing `b.eq 0b` in that >>> function to `b.eq 0f` works for me and I'll make that switch in a >>> different >>> patch). >>> The new BR and BLR tests also fail from what seems to be using the >>> values of >>> the registers as seen by `info registers` which don't appear to be >>> getting >>> updated correctly as the program proceeds. >>> I can see the same problem on the instruction `mov x1, x2` (that the >>> value of >>> x2 used is what GDB prints out with `info registers` rather than the >>> value it >>> should be based on the code. >>> >>> So, the testcase does not pass cleanly with the command you >>> suggested, but I >>> think it's not a problem with the changes I've made. >>> >>> -------- MOV Testcase that fails under gdbserver >>> Putting this function in the insn-reloc.c (and placing it in the test >>> array so >>> it gets called before the program exits from a broken test) >>> demonstrates that >>> displaced stepping doesn't seem to use the correct values from the >>> gdbserver >>> context. >>> >>> >>> static void >>> can_relocate_mov (void) >>> { >>> ��� int ok = 0; >>> ��� asm ("� mov x1, #1\n" >>> �������� "set_point15:\n" >>> �������� "� mov %[ok], x1\n" >>> �������� : [ok] "=r" (ok) >>> �������� : : "x1"); >>> ��� if (ok == 1) >>> ����� pass(); >>> ��� else >>> ����� fail(); >>> �� } >>> ------- >>> >>> >>> >>> If Ok could someone apply this for me (I don't have commit rights)? >>> >>> >>> ###### Proposed commit message and patch below >>> >>> Enable displaced stepping over a BR/BLR instruction >>> >>> Displaced stepping over an instruction executes a instruction in a >>> scratch area and then manually fixes up the PC address to leave >>> execution where it would have been if the instruction were in its >>> original location. >>> >>> The BR instruction does not need modification in order to run correctly >>> at a different address, but the displaced step fixup method should not >>> manually adjust the PC since the BR instruction sets that value already. >>> >>> The BLR instruction should also avoid such a fixup, but must also have >>> the link register modified to point to just after the original code >>> location rather than back to the scratch location. >>> >>> This patch adds the above functionality. >>> We add this functionality by modifying aarch64_displaced_step_others >>> rather than by adding a new visitor method to aarch64_insn_visitor. >>> We choose this since it seems that visitor approach is designed >>> specifically for PC relative instructions (which must always be modified >>> when executed in a different location). >>> >>> It seems that the BR and BLR instructions are more like the RET >>> instruction which is already handled specially in >>> aarch64_displaced_step_others. >>> >>> This also means the gdbserver code to relocate an instruction when >>> creating a fast tracepoint does not need to be modified, since nothing >>> special is needed for the BR and BLR instructions there. >>> >>> Regression tests showed nothing untoward on native aarch64. >>> I noticed that the disp-step-insn-reloc.exp test produces quite a few >>> errors when running with RUNTESTFLAGS="--target_board=native-gdbserver" >>> (bcond_true, cbz, tbnz, bcond_false, blr, br). >>> There are existing errors, and the BLR and BR tests also fail. >>> It seems the context is not preserved properly for displaced >>> stepping(for the Conditional instructions the condition flags are not >>> preserved, and for BLR/BR the general registers are not preserved). >>> The same� problem can be observed when using displaced stepping on a >>> `mov %[ok], x1` instruction, so I'm confident this is not a problem with >>> my patch. >>> >>> ------##### >>> Original observed (mis)behaviour before was that displaced stepping over >>> a BR or BLR instruction would not execute the function they called. >>> Most easily seen by putting a breakpoint with a condition on such an >>> instruction and a print statement in the functions they called. >>> When run with the breakpoint enabled the function is not called and >>> "numargs called" is not printed. >>> When run with the breakpoint disabled the function is called and the >>> message is printed. >>> >>> --- GDB Session >>> hw-a20-10:gcc-source [15:57:14] % gdb ../using-blr >>> Reading symbols from ../using-blr...done. >>> (gdb) disassemble blr_call_value >>> Dump of assembler code for function blr_call_value: >>> ... >>> ���� 0x0000000000400560 <+28>:��� blr���� x2 >>> ... >>> ���� 0x00000000004005b8 <+116>:�� ret >>> End of assembler dump. >>> (gdb) break *0x0000000000400560 >>> Breakpoint 1 at 0x400560: file ../using-blr.c, line 22. >>> (gdb) condition 1 10 == 0 >>> (gdb) run >>> Starting program: /home/matmal01/using-blr >>> [Inferior 1 (process 33279) exited with code 012] >>> (gdb) disable 1 >>> (gdb) run >>> Starting program: /home/matmal01/using-blr >>> numargs called >>> [Inferior 1 (process 33289) exited with code 012] >>> (gdb) >>> >>> Test program: >>> ---- using-blr ---- >>> \#include >>> typedef int (foo) (int, int); >>> typedef void (bar) (int, int); >>> struct sls_testclass { >>> ����� foo *x; >>> ����� bar *y; >>> ����� int left; >>> ����� int right; >>> }; >>> >>> __attribute__ ((noinline)) >>> int blr_call_value (struct sls_testclass x) >>> { >>> ��� int retval = x.x(x.left, x.right); >>> ��� if (retval % 10) >>> ����� return 100; >>> ��� return 9; >>> } >>> >>> __attribute__ ((noinline)) >>> int blr_call (struct sls_testclass x) >>> { >>> ��� x.y(x.left, x.right); >>> ��� if (x.left % 10) >>> ����� return 100; >>> ��� return 9; >>> } >>> >>> int >>> numargs (__attribute__ ((unused)) int left, __attribute__ ((unused)) >>> int right) >>> { >>> ��������� printf("numargs called\n"); >>> ��������� return 10; >>> } >>> >>> void >>> altfunc (__attribute__ ((unused)) int left, __attribute__ ((unused)) >>> int right) >>> { >>> ��������� printf("altfunc called\n"); >>> } >>> >>> int main(int argc, char **argv) >>> { >>> ��� struct sls_testclass x = { .x = numargs, .y = altfunc, .left = 1, >>> .right = 2 }; >>> ��� if (argc > 2) >>> ��� { >>> ��������� blr_call (x); >>> ��� } >>> ��� else >>> ��������� blr_call_value (x); >>> ��� return 10; >>> } >>> >>> ------ >>> >>> gdb/ChangeLog: >>> 2020-08-19� Matthew Malcomson� >>> >>> ����* aarch64-tdep.c (aarch64_displaced_step_others): Account for >>> ����BLR and BR instructions. >>> ����* arch/aarch64-insn.h (enum aarch64_opcodes): Add BR opcode. >>> ����(enum aarch64_masks): New. >>> >>> gdb/testsuite/ChangeLog: >>> 2020-08-19� Matthew Malcomson� >>> >>> ����* gdb.arch/insn-reloc.c: Add tests for BR and BLR. >>> >>> >>> >>> ###############���� Attachment also inlined for ease of reply >>> ############### >>> >>> >>> diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c >>> index >>> 5e7d0d0b8682af04ce4f01fd999d26c9eb459932..d247108f53bf045a018b2bf85284088563868ae0 >>> 100644 >>> --- a/gdb/aarch64-tdep.c >>> +++ b/gdb/aarch64-tdep.c >>> @@ -2974,15 +2974,22 @@ aarch64_displaced_step_others (const uint32_t >>> insn, >>> ���� struct aarch64_displaced_step_data *dsd >>> ������ = (struct aarch64_displaced_step_data *) data; >>> -� aarch64_emit_insn (dsd->insn_buf, insn); >>> -� dsd->insn_count = 1; >>> - >>> -� if ((insn & 0xfffffc1f) == 0xd65f0000) >>> +� uint32_t masked_insn = (insn & CLEAR_Rn_MASK); >>> +� if (masked_insn == BLR) >>> ������ { >>> -����� /* RET */ >>> -����� dsd->dsc->pc_adjust = 0; >>> +����� /* Emit a BR to the same register and then update LR to the >>> original >>> +���� address (similar to aarch64_displaced_step_b).� */ >>> +����� aarch64_emit_insn (dsd->insn_buf, insn & 0xffdfffff); >>> +����� regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM, >>> +��������������������� data->insn_addr + 4); >>> ������ } >>> ���� else >>> +��� aarch64_emit_insn (dsd->insn_buf, insn); >>> +� dsd->insn_count = 1; >>> + >>> +� if (masked_insn == RET || masked_insn == BR || masked_insn == BLR) >>> +��� dsd->dsc->pc_adjust = 0; >>> +� else >>> ������ dsd->dsc->pc_adjust = 4; >>> �� } >>> diff --git a/gdb/arch/aarch64-insn.h b/gdb/arch/aarch64-insn.h >>> index >>> 6a63ce9c2005acd6fe018a12c640f1be01751d6b..f261363feefe4e93e155434ba6d3df8e4b994c9f >>> 100644 >>> --- a/gdb/arch/aarch64-insn.h >>> +++ b/gdb/arch/aarch64-insn.h >>> @@ -40,7 +40,9 @@ enum aarch64_opcodes >>> ���� CBNZ����������� = 0x21000000 | B, >>> ���� TBZ������������ = 0x36000000 | B, >>> ���� TBNZ����������� = 0x37000000 | B, >>> +� /* BR������������ 1101 0110 0001 1111 0000 00rr rrr0 0000 */ >>> ���� /* BLR����������� 1101 0110 0011 1111 0000 00rr rrr0 0000 */ >>> +� BR������������� = 0xd61f0000, >>> ���� BLR������������ = 0xd63f0000, >>> ���� /* RET����������� 1101 0110 0101 1111 0000 00rr rrr0 0000 */ >>> ���� RET������������ = 0xd65f0000, >>> @@ -107,6 +109,14 @@ enum aarch64_opcodes >>> ���� NOP������������ = (0 << 5) | HINT, >>> �� }; >>> +/* List of useful masks.� */ >>> +enum aarch64_masks >>> +{ >>> +� /* Used for masking out an Rn argument from an opcode.� */ >>> +� CLEAR_Rn_MASK = 0xfffffc1f, >>> +}; >>> + >>> + >>> �� /* Representation of a general purpose register of the form xN or wN. >>> ����� This type is used by emitting functions that take registers as >>> operands.� */ >>> diff --git a/gdb/testsuite/gdb.arch/insn-reloc.c >>> b/gdb/testsuite/gdb.arch/insn-reloc.c >>> index >>> 106fd6ed1e8cb146863ff767130a82814ee89f86..9e7cf7a12df387e85881e19bdef7372046ba2861 >>> 100644 >>> --- a/gdb/testsuite/gdb.arch/insn-reloc.c >>> +++ b/gdb/testsuite/gdb.arch/insn-reloc.c >>> @@ -512,6 +512,99 @@ can_relocate_bl (void) >>> ��������� : : : "x30"); /* Test that LR is updated correctly.� */ >>> �� } >>> +/* Make sure we can relocate a BR instruction. >>> + >>> +���� ... Set x0 to target >>> +�� set_point12: >>> +���� BR x0 ; jump to target (tracepoint here). >>> +���� MOV %[ok], #0 >>> +���� B end >>> +�� target: >>> +���� MOV %[ok], #1 >>> +�� end >>> + >>> +�� */ >>> + >>> +static void >>> +can_relocate_br (void) >>> +{ >>> +� int ok = 0; >>> + >>> +� asm ("� movz x0, :abs_g3:0f\n" >>> +������ "� movk x0, :abs_g2_nc:0f\n" >>> +������ "� movk x0, :abs_g1_nc:0f\n" >>> +������ "� movk x0, :abs_g0_nc:0f\n" >>> +������ "set_point12:\n" >>> +������ "� br x0\n" >>> +������ "� mov %[ok], #0\n" >>> +������ "� b 1f\n" >>> +������ "0:\n" >>> +������ "� mov %[ok], #1\n" >>> +������ "1:\n" >>> +������ : [ok] "=r" (ok) >>> +������ : >>> +������ : "0"); >>> + >>> +� if (ok == 1) >>> +��� pass (); >>> +� else >>> +��� fail (); >>> +} >>> + >>> +/* Make sure we can relocate a BLR instruction. >>> + >>> +�� We use two different functions since the test runner expects one >>> breakpoint >>> +�� per function and we want to test two different things. >>> +�� For BLR we want to test that the BLR actually jumps to the relevant >>> +�� function, *and* that it sets the LR register correctly. >>> + >>> +�� Hence we create one testcase that jumps to `pass` using BLR, and one >>> +�� testcase that jumps to `pass` if BLR has set the LR correctly. >>> + >>> +� -- can_relocate_blr_jumps >>> +���� ... Set x0 to pass >>> +�� set_point13: >>> +���� BLR x0������� ; jump to pass (tracepoint here). >>> + >>> +� -- can_relocate_blr_sets_lr >>> +���� ... Set x0 to foo >>> +�� set_point14: >>> +���� BLR x0������� ; jumps somewhere else (tracepoint here). >>> +���� BL pass������ ; ensures the LR was set correctly by the BLR. >>> + >>> +�� */ >>> + >>> +static void >>> +can_relocate_blr_jumps (void) >>> +{ >>> +� int ok = 0; >>> + >>> +� /* Test BLR indeed jumps to the target.� */ >>> +� asm ("� movz x0, :abs_g3:pass\n" >>> +������ "� movk x0, :abs_g2_nc:pass\n" >>> +������ "� movk x0, :abs_g1_nc:pass\n" >>> +������ "� movk x0, :abs_g0_nc:pass\n" >>> +������ "set_point13:\n" >>> +������ "� blr x0\n" >>> +������ : : : "x0","x30"); >>> +} >>> + >>> +static void >>> +can_relocate_blr_sets_lr (void) >>> +{ >>> +� int ok = 0; >>> + >>> +� /* Test BLR sets the LR correctly.� */ >>> +� asm ("� movz x0, :abs_g3:foo\n" >>> +������ "� movk x0, :abs_g2_nc:foo\n" >>> +������ "� movk x0, :abs_g1_nc:foo\n" >>> +������ "� movk x0, :abs_g0_nc:foo\n" >>> +������ "set_point14:\n" >>> +������ "� blr x0\n" >>> +������ "� bl pass\n" >>> +������ : : : "x0","x30"); >>> +} >>> + >>> �� #endif >>> �� /* Functions testing relocations need to be placed here.� GDB will >>> read >>> @@ -536,6 +629,9 @@ static testcase_ftype testcases[] = { >>> ���� can_relocate_ldr, >>> ���� can_relocate_bcond_false, >>> ���� can_relocate_bl, >>> +� can_relocate_br, >>> +� can_relocate_blr_jumps, >>> +� can_relocate_blr_sets_lr, >>> �� #endif >>> �� }; >>> >>