From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id IH8YDDwXUWNYsA4AWB0awg (envelope-from ) for ; Thu, 20 Oct 2022 05:39:08 -0400 Received: by simark.ca (Postfix, from userid 112) id 2F6E31E112; Thu, 20 Oct 2022 05:39:08 -0400 (EDT) Authentication-Results: simark.ca; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=gSqMnHr5; dkim-atps=neutral X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RDNS_DYNAMIC,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id D295F1E0D5 for ; Thu, 20 Oct 2022 05:39:07 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9CA283856149 for ; Thu, 20 Oct 2022 09:37:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9CA283856149 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1666258671; bh=/3W2c22l9gOsYeluXtUmFCFw/3nCU20j0c60Xi0SR3A=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=gSqMnHr5j8QkioGrCcHxb96wJxIrsGxTgo4aCanFXb90YI5A3ANBY81yWCek8Ix8b HoKoCCR9k37mNO8gtNpenszBDAUYBBEN9IeiRquCGylVs6dS/XqJjanSDY4ozrHCWP 6MNa7Skrhba+u/K8k3hzZd8hKNO968nw2LN2M5zI= Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 7E292395A03A for ; Thu, 20 Oct 2022 09:36:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7E292395A03A Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id CF68D300089; Thu, 20 Oct 2022 09:36:34 +0000 (UTC) To: Tsukasa OI , Andrew Burgess , Mike Frysinger , Nick Clifton Subject: [PATCH 21/40] sim/m32r: Declare all required functions Date: Thu, 20 Oct 2022 09:32:26 +0000 Message-Id: <4a4ba144b84972f5b244be4d6e0900fbaae8c62f.1666258361.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Tsukasa OI via Gdb-patches Reply-To: Tsukasa OI Cc: gdb-patches@sourceware.org Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" This commit declares all required functions in m32r-sim.h. They should be defined in "cpu.h", "cpux.h" and "cpu2.h" but we currently cannot do that. It also moves declarations of four functions out of two #ifndef blocks to make those function available on all cases. --- sim/m32r/m32r-sim.h | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/sim/m32r/m32r-sim.h b/sim/m32r/m32r-sim.h index 0c5103b0784..189be8868e1 100644 --- a/sim/m32r/m32r-sim.h +++ b/sim/m32r/m32r-sim.h @@ -42,9 +42,6 @@ extern int m32r_decode_gdb_ctrl_regnum (int); #define GET_H_SM() ((CPU (h_psw) & 0x80) != 0) #ifndef GET_H_CR -extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT); -extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI); - #define GET_H_CR(regno) \ XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno)) #define SET_H_CR(regno, val) \ @@ -52,9 +49,6 @@ extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI); #endif #ifndef GET_H_PSW -extern UQI m32rbf_h_psw_get_handler (SIM_CPU *); -extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI); - #define GET_H_PSW() \ XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu) #define SET_H_PSW(val) \ @@ -68,8 +62,26 @@ extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI); The correct solution is to fix the code in cgen/sim.scm to generate prototypes for each of the functions it generates. */ +extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT); +extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI); +extern USI m32rxf_h_cr_get_handler (SIM_CPU *, UINT); +extern void m32rxf_h_cr_set_handler (SIM_CPU *, UINT, USI); +extern USI m32r2f_h_cr_get_handler (SIM_CPU *, UINT); +extern void m32r2f_h_cr_set_handler (SIM_CPU *, UINT, USI); +extern UQI m32rbf_h_psw_get_handler (SIM_CPU *); +extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI); +extern UQI m32rxf_h_psw_get_handler (SIM_CPU *); +extern void m32rxf_h_psw_set_handler (SIM_CPU *, UQI); +extern UQI m32r2f_h_psw_get_handler (SIM_CPU *); +extern void m32r2f_h_psw_set_handler (SIM_CPU *, UQI); extern DI m32rbf_h_accum_get_handler (SIM_CPU *); extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI); +extern DI m32rxf_h_accum_get_handler (SIM_CPU *); +extern void m32rxf_h_accum_set_handler (SIM_CPU *, DI); +extern DI m32r2f_h_accum_get_handler (SIM_CPU *); +extern void m32r2f_h_accum_set_handler (SIM_CPU *, DI); +extern DI m32rxf_h_accums_get_handler (SIM_CPU *, UINT); +extern void m32rxf_h_accums_set_handler (SIM_CPU *, UINT, DI); extern DI m32r2f_h_accums_get_handler (SIM_CPU *, UINT); extern void m32r2f_h_accums_set_handler (SIM_CPU *, UINT, DI); -- 2.34.1