From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 11571 invoked by alias); 19 Apr 2012 15:13:05 -0000 Received: (qmail 11502 invoked by uid 22791); 19 Apr 2012 15:13:01 -0000 X-SWARE-Spam-Status: No, hits=-1.7 required=5.0 tests=AWL,BAYES_00,TW_AV,TW_FP,TW_IW,TW_MX,TW_VF,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from hagrid.ecoscentric.com (HELO mail.ecoscentric.com) (212.13.207.197) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 19 Apr 2012 15:12:23 +0000 Received: from localhost (hagrid.ecoscentric.com [127.0.0.1]) by mail.ecoscentric.com (Postfix) with ESMTP id 66D262F78003; Thu, 19 Apr 2012 16:12:21 +0100 (BST) Received: from mail.ecoscentric.com ([127.0.0.1]) by localhost (hagrid.ecoscentric.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cayUBT4yTXy1; Thu, 19 Apr 2012 16:12:15 +0100 (BST) Message-ID: <4F902B4E.9070704@eCosCentric.com> Date: Thu, 19 Apr 2012 15:13:00 -0000 From: Jonathan Larmour User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111108 Fedora/3.1.16-1.fc14 Lightning/1.0b3pre Thunderbird/3.1.16 MIME-Version: 1.0 To: gdb-patches@sourceware.org CC: Ilija Kocho , Terry Guo , Pedro Alves Subject: [patch] Add support for VFP d16 layout for Cortex-M4 Content-Type: multipart/mixed; boundary="------------090401080301080007060209" Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2012-04/txt/msg00629.txt.bz2 This is a multi-part message in MIME format. --------------090401080301080007060209 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-length: 2001 As mentioned in my response to the GDB list mail , I have a patch to allow easy automatic use of Cortex-M targets with a register layout with 16 double precision / 32 single precision regs. This is as used in the increasingly popular Cortex-M4 core. I have chosen to use the remote packet guessing approach again, rather than inferring from the executable's ELF header, because not everyone will actually want to use hardware FP just because they're using that core, so what the stub actually supports is a better indicator of what is wanted. There's a couple of trivial little fixes from earlier changes too (a comment and missing entries in features/Makefile). FAOD I have write-after-approval commit perms. Jifl 2012-04-19 Jonathan Larmour * arm-dep.h (VFP_REGISTER_SIZE): Define. * features/Makefile: Add arm-with-m* entries currently missing. * features/arm-with-m-vfp-d16.xml: New file. Describes Cortex-M with VFPv4-sp-d16 FPU register layout. * features/arm-with-m-vfp-d16.c: Generate from above. * arm-tdep.c: Include arm-with-m-vfp-d16.c. (arm-register_g_packet_guesses): Fix comment. Add vfp-d16 guess. (_initialise_arm_tdep): Initialize arm-with-m-vfp-d16 tdesc. arm-tdep.c | 12 ++++++++ arm-tdep.h | 4 ++ features/Makefile | 3 +- features/arm-with-m-vfp-d16.c | 54 ++++++++++++++++++++++++++++++++++++++++ features/arm-with-m-vfp-d16.xml | 13 +++++++++ 5 files changed, 84 insertions(+), 2 deletions(-) -- eCosCentric Limited http://www.eCosCentric.com/ The eCos experts Barnwell House, Barnwell Drive, Cambridge, UK. Tel: +44 1223 245571 Registered in England and Wales: Reg No 4422071. ** Visit us at NEW:UK - the UK Embedded & Electronics Exhibition ** ** ARM Partner Pavilion/Stand #114. 18-19 April. Birmingham NEC ** ------["Si fractum non sit, noli id reficere"]------ Opinions==mine --------------090401080301080007060209 Content-Type: text/plain; name="vfpd16.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="vfpd16.patch" Content-length: 8020 Index: arm-tdep.c =================================================================== RCS file: /cvs/src/src/gdb/arm-tdep.c,v retrieving revision 1.360 diff -u -5 -p -r1.360 arm-tdep.c --- arm-tdep.c 27 Mar 2012 15:46:33 -0000 1.360 +++ arm-tdep.c 19 Apr 2012 14:19:39 -0000 @@ -57,10 +57,11 @@ #include "record.h" #include "features/arm-with-m.c" #include "features/arm-with-m-fpa-layout.c" +#include "features/arm-with-m-vfp-d16.c" #include "features/arm-with-iwmmxt.c" #include "features/arm-with-vfpv2.c" #include "features/arm-with-vfpv3.c" #include "features/arm-with-neon.c" @@ -9684,11 +9685,11 @@ arm_register_g_packet_guesses (struct gd { /* If we know from the executable this is an M-profile target, cater for remote targets whose register set layout is the same as the FPA layout. */ register_remote_g_packet_guess (gdbarch, - /* r0-r12,sp,lr,pc; f0-f7; fps,cpsr */ + /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */ (16 * INT_REGISTER_SIZE) + (8 * FP_REGISTER_SIZE) + (2 * INT_REGISTER_SIZE), tdesc_arm_with_m_fpa_layout); @@ -9696,10 +9697,18 @@ arm_register_g_packet_guesses (struct gd register_remote_g_packet_guess (gdbarch, /* r0-r12,sp,lr,pc; xpsr */ (16 * INT_REGISTER_SIZE) + INT_REGISTER_SIZE, tdesc_arm_with_m); + + /* M-profile plus M4F VFP. */ + register_remote_g_packet_guess (gdbarch, + /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */ + (16 * INT_REGISTER_SIZE) + + (16 * VFP_REGISTER_SIZE) + + (2 * INT_REGISTER_SIZE), + tdesc_arm_with_m_vfp_d16); } /* Otherwise we don't have a useful guess. */ } @@ -10331,10 +10340,11 @@ _initialize_arm_tdep (void) arm_elf_osabi_sniffer); /* Initialize the standard target descriptions. */ initialize_tdesc_arm_with_m (); initialize_tdesc_arm_with_m_fpa_layout (); + initialize_tdesc_arm_with_m_vfp_d16 (); initialize_tdesc_arm_with_iwmmxt (); initialize_tdesc_arm_with_vfpv2 (); initialize_tdesc_arm_with_vfpv3 (); initialize_tdesc_arm_with_neon (); Index: arm-tdep.h =================================================================== RCS file: /cvs/src/src/gdb/arm-tdep.h,v retrieving revision 1.56 diff -u -5 -p -r1.56 arm-tdep.h --- arm-tdep.h 27 Mar 2012 15:46:33 -0000 1.56 +++ arm-tdep.h 19 Apr 2012 14:19:39 -0000 @@ -69,10 +69,14 @@ enum gdb_regnum { /* Say how long FP registers are. Used for documentation purposes and code readability in this header. IEEE extended doubles are 80 bits. DWORD aligned they use 96 bits. */ #define FP_REGISTER_SIZE 12 +/* Say how long VFP double precision registers are. Used for documentation + purposes and code readability. These are fixed at 64 bits. */ +#define VFP_REGISTER_SIZE 8 + /* Number of machine registers. The only define actually required is gdbarch_num_regs. The other definitions are used for documentation purposes and code readability. */ /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS) (and called PS for processor status) so the status bits can be cleared Index: features/Makefile =================================================================== RCS file: /cvs/src/src/gdb/features/Makefile,v retrieving revision 1.26 diff -u -5 -p -r1.26 Makefile --- features/Makefile 10 Apr 2012 15:44:23 -0000 1.26 +++ features/Makefile 19 Apr 2012 14:19:39 -0000 @@ -28,11 +28,12 @@ # XML master copies. This relies on a GDB linked with expat and # configured for the correct architecture, so the files are again kept # in the GDB repository. To generate C files: # make GDB=/path/to/gdb XMLTOC="xml files" cfiles -WHICH = arm-with-iwmmxt arm-with-vfpv2 arm-with-vfpv3 arm-with-neon \ +WHICH = arm-with-iwmmxt arm-with-vfpv2 arm-with-vfpv3 \ + arm-with-m arm-with-m-fpa-layout arm-with-m-vfp-d16 arm-with-neon \ i386/i386 i386/i386-linux \ i386/i386-mmx i386/i386-mmx-linux \ i386/amd64 i386/amd64-linux \ i386/i386-avx i386/i386-avx-linux \ i386/amd64-avx i386/amd64-avx-linux \ Index: features/arm-with-m-vfp-d16.c =================================================================== RCS file: features/arm-with-m-vfp-d16.c diff -N features/arm-with-m-vfp-d16.c --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ features/arm-with-m-vfp-d16.c 19 Apr 2012 14:19:39 -0000 @@ -0,0 +1,54 @@ +/* THIS FILE IS GENERATED. Original: arm-with-m-vfp-d16.xml */ + +#include "defs.h" +#include "osabi.h" +#include "target-descriptions.h" + +struct target_desc *tdesc_arm_with_m_vfp_d16; +static void +initialize_tdesc_arm_with_m_vfp_d16 (void) +{ + struct target_desc *result = allocate_target_description (); + struct tdesc_feature *feature; + struct tdesc_type *field_type, *type; + + feature = tdesc_create_feature (result, "org.gnu.gdb.arm.m-profile"); + tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "sp", 13, 1, NULL, 32, "data_ptr"); + tdesc_create_reg (feature, "lr", 14, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "pc", 15, 1, NULL, 32, "code_ptr"); + tdesc_create_reg (feature, "xpsr", 25, 1, NULL, 32, "int"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.arm.vfp"); + tdesc_create_reg (feature, "d0", 26, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "d1", 27, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "d2", 28, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "d3", 29, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "d4", 30, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "d5", 31, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "d6", 32, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "d7", 33, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "d8", 34, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "d9", 35, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "d10", 36, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "d11", 37, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "d12", 38, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "d13", 39, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "d14", 40, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "d15", 41, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "fpscr", 42, 1, "float", 32, "int"); + + tdesc_arm_with_m_vfp_d16 = result; +} Index: features/arm-with-m-vfp-d16.xml =================================================================== RCS file: features/arm-with-m-vfp-d16.xml diff -N features/arm-with-m-vfp-d16.xml --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ features/arm-with-m-vfp-d16.xml 19 Apr 2012 14:19:39 -0000 @@ -0,0 +1,13 @@ + + + + + + + + + --------------090401080301080007060209--