From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 21010 invoked by alias); 9 Oct 2011 13:28:18 -0000 Received: (qmail 21001 invoked by uid 22791); 9 Oct 2011 13:28:17 -0000 X-SWARE-Spam-Status: No, hits=-1.5 required=5.0 tests=AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 09 Oct 2011 13:28:02 +0000 Received: from nat-jpt.mentorg.com ([192.94.33.2] helo=PR1-MAIL.mgc.mentorg.com) by relay1.mentorg.com with esmtp id 1RCtQ9-0006ox-3p from Yao_Qi@mentor.com ; Sun, 09 Oct 2011 06:28:01 -0700 Received: from [127.0.0.1] ([172.16.63.104]) by PR1-MAIL.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.1830); Sun, 9 Oct 2011 22:27:59 +0900 Message-ID: <4E91A158.5000306@codesourcery.com> Date: Sun, 09 Oct 2011 13:28:00 -0000 From: Yao Qi User-Agent: Mozilla/5.0 (X11; Linux i686; rv:6.0.2) Gecko/20110906 Thunderbird/6.0.2 MIME-Version: 1.0 To: Ulrich Weigand CC: "gdb-patches@sourceware.org" Subject: Re: [try 2nd 5/8] Displaced stepping for Thumb 32-bit insns References: <201109141339.p8EDddLk024568@d06av02.portsmouth.uk.ibm.com> In-Reply-To: <201109141339.p8EDddLk024568@d06av02.portsmouth.uk.ibm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2011-10/txt/msg00221.txt.bz2 On 09/14/2011 09:39 PM, Ulrich Weigand wrote: >> > 1. Failures in gdb.arch/thumb2-it.exp and gdb.base/gdb1555.exp. >> > These failures are caused by missing IT support in thumb displaced stepping. > Ah, right. Fortunately, I think IT support should be relatively easy to > add, in fact we should be able to just completely emulate it: > > - The first thing we do when we're about to displaced-step a Thumb insn > is to check the itstate and see whether we're in an IT block. > > - If so, we check whether the condition is true, given the current state > of the flags. > > - If the condition is false, we always use a NOP as the displaced > instruction; otherwise, compute the displaced instruction as usual. > > - In either case, set the CSPR register as if we're outside of any > IT block while actually executing the displaced instruction. (This > also makes sure that the breakpoint at the end will always be > executed.) > > - During fixup after execution is done, re-set IT state in the CSPR > to the proper value (advanced by one instruction). > > See also thumb_get_next_pc_raw for how to manipulate IT state ... > > Does this look good to you? > Yes, it looks right to me in general. However, it doesn't handle the case of `stepi' in condition blocks when displaced stepping is enabled, as gdb.arch/thumb2-it.exp tested. We expect inferior stops at the next true-condition instruction instead of next instruction after typing `stepi'. In this design, inferior will stop at the next instruction regardless of condition. We may adjust PC value in fixup to skip these false-condition instructions. -- Yao (齐尧)