From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 9767 invoked by alias); 23 May 2011 11:32:33 -0000 Received: (qmail 9759 invoked by uid 22791); 23 May 2011 11:32:32 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL,BAYES_00,TW_EG,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 23 May 2011 11:32:20 +0000 Received: (qmail 24071 invoked from network); 23 May 2011 11:32:19 -0000 Received: from unknown (HELO ?192.168.0.102?) (yao@127.0.0.2) by mail.codesourcery.com with ESMTPA; 23 May 2011 11:32:19 -0000 Message-ID: <4DDA45BA.5050400@codesourcery.com> Date: Mon, 23 May 2011 11:32:00 -0000 From: Yao Qi User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.14) Gecko/20110223 Lightning/1.0b2 Thunderbird/3.1.8 MIME-Version: 1.0 To: Ulrich Weigand CC: gdb-patches@sourceware.org Subject: Re: [try 2nd 5/8] Displaced stepping for Thumb 32-bit insns References: <201105171714.p4HHEBTp018414@d06av02.portsmouth.uk.ibm.com> In-Reply-To: <201105171714.p4HHEBTp018414@d06av02.portsmouth.uk.ibm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2011-05/txt/msg00522.txt.bz2 On 05/18/2011 01:14 AM, Ulrich Weigand wrote: >> > +static int >> > +thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1, >> > + uint16_t insn2, struct regcache *regs, >> > + struct displaced_step_closure *dsc) >> > +{ >> > + unsigned int rn = bits (insn1, 0, 3); >> > + >> > + if (rn == ARM_PC_REGNUM) >> > + return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, >> > + "copro load/store", dsc); >> > + >> > + if (debug_displaced) >> > + fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor " >> > + "load/store insn %.4x%.4x\n", insn1, insn2); >> > + >> > + dsc->modinsn[0] = insn1 & 0xfff0; >> > + dsc->modinsn[1] = insn2; >> > + dsc->numinsns = 2; > This doesn't look right: you're replacing the RN register if it is anything > *but* 15 -- but those cases do not need to be replaced! > Sorry, the condition check should be reversed. > In fact, unless I'm missing something, in Thumb mode no coprocessor > instruction actually uses the PC (either RN == 15 indicates some other > operation, or else it is specified as unpredictable). So those should > simply all be copied unmodified ... > I can understand almost of your comments except this one. I think you are right, but there are still some cases that PC is used in this category of instructions. thumb2_copy_copro_load_store covers instructions STC/STC2, VLDR/VSTR and LDC/LDC2 (literal and immediate). I re-read ARM ARM again, and find that, STC/STC2 doesn't use PC. ARM ARM said "if n == 15 && (wback || CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE;" VSTR doesn't use PC. ARM ARM said "if n == 15 && CurrentInstrSet() != InstrSet_ARM then UNPREDICTABLE;" However, LDC/LDC2/VLDR can use PC. VLDR{.32} , [PC, #+/-] LDC, LDC2 (literal or immediate) LDC{L} ,,[PC],