From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28120 invoked by alias); 3 Mar 2011 02:20:08 -0000 Received: (qmail 28110 invoked by uid 22791); 3 Mar 2011 02:20:06 -0000 X-SWARE-Spam-Status: No, hits=-1.7 required=5.0 tests=AWL,BAYES_00,TW_BT,TW_DB,TW_EG,TW_XT,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 03 Mar 2011 02:20:00 +0000 Received: (qmail 30012 invoked from network); 3 Mar 2011 02:19:57 -0000 Received: from unknown (HELO ?192.168.0.101?) (yao@127.0.0.2) by mail.codesourcery.com with ESMTPA; 3 Mar 2011 02:19:57 -0000 Message-ID: <4D6EFACA.70809@codesourcery.com> Date: Thu, 03 Mar 2011 02:20:00 -0000 From: Yao Qi User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.13) Gecko/20101208 Lightning/1.0b2 Thunderbird/3.1.7 MIME-Version: 1.0 To: gdb-patches@sourceware.org Subject: Re: Fix magic number in arm-tdep.c References: <201103021412.p22EC5vZ015623@d06av02.portsmouth.uk.ibm.com> In-Reply-To: <201103021412.p22EC5vZ015623@d06av02.portsmouth.uk.ibm.com> Content-Type: multipart/mixed; boundary="------------030700020401070502060207" X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2011-03/txt/msg00151.txt.bz2 This is a multi-part message in MIME format. --------------030700020401070502060207 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Content-length: 383 On 03/02/2011 10:12 PM, Ulrich Weigand wrote: > This is OK, but please keep the indentation in cases like: > >> > - nextpc = (rn == 15) ? pc_val + 8 >> > + nextpc = (rn == ARM_PC_REGNUM) ? pc_val + 8 >> > : get_frame_register_unsigned (frame, rn); > (? and : should remain in the same column). Thanks for the quick review. Fix the indent and applied. -- Yao (齐尧) --------------030700020401070502060207 Content-Type: text/x-patch; name="arm-magic-num-0303.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="arm-magic-num-0303.patch" Content-length: 10960 cvs diff: Diffing . Index: ChangeLog =================================================================== RCS file: /cvs/src/src/gdb/ChangeLog,v retrieving revision 1.12724 diff -u -r1.12724 ChangeLog --- ChangeLog 3 Mar 2011 01:15:45 -0000 1.12724 +++ ChangeLog 3 Mar 2011 02:16:01 -0000 @@ -1,3 +1,14 @@ +2011-03-03 Yao Qi + + * gdb/arm-tdep.c (shifted_reg_val): Replace magic number 15 with + ARM_PC_REGNUM. + (thumb_get_next_pc_raw, arm_get_next_pc_raw): Likewise. + (displaced_write_reg, displaced_read_reg): Likewise. + (copy_ldr_str_ldrb_strb, cleanup_block_load_all): Likewise. + (cleanup_block_load_pc, copy_block_xfer): Likewise. + (cleanup_branch): Replace magic number 14 and 15 with + ARM_LR_REGNUM and ARM_PC_REGNUM respectively. + 2011-03-02 Michael Snyder * maint.c (maintenance_do_deprecate): No need to check for NULL. Index: arm-tdep.c =================================================================== RCS file: /cvs/src/src/gdb/arm-tdep.c,v retrieving revision 1.332 diff -u -r1.332 arm-tdep.c --- arm-tdep.c 2 Mar 2011 05:33:37 -0000 1.332 +++ arm-tdep.c 3 Mar 2011 02:16:05 -0000 @@ -4144,7 +4144,7 @@ else shift = bits (inst, 7, 11); - res = (rm == 15 + res = (rm == ARM_PC_REGNUM ? (pc_val + (bit (inst, 4) ? 12 : 8)) : get_frame_register_unsigned (frame, rm)); @@ -4498,7 +4498,7 @@ rn = bits (inst1, 0, 3); base = get_frame_register_unsigned (frame, rn); - if (rn == 15) + if (rn == ARM_PC_REGNUM) { base = (base + 4) & ~(CORE_ADDR) 0x3; if (bit (inst1, 7)) @@ -4665,16 +4665,19 @@ || bits (this_instr, 4, 27) == 0x12fff3) { rn = bits (this_instr, 0, 3); - nextpc = (rn == 15) ? pc_val + 8 - : get_frame_register_unsigned (frame, rn); + nextpc = ((rn == ARM_PC_REGNUM) + ? (pc_val + 8) + : get_frame_register_unsigned (frame, rn)); + return nextpc; } /* Multiply into PC. */ c = (status & FLAG_C) ? 1 : 0; rn = bits (this_instr, 16, 19); - operand1 = (rn == 15) ? pc_val + 8 - : get_frame_register_unsigned (frame, rn); + operand1 = ((rn == ARM_PC_REGNUM) + ? (pc_val + 8) + : get_frame_register_unsigned (frame, rn)); if (bit (this_instr, 25)) { @@ -4774,8 +4777,10 @@ /* byte write to PC */ rn = bits (this_instr, 16, 19); - base = (rn == 15) ? pc_val + 8 - : get_frame_register_unsigned (frame, rn); + base = ((rn == ARM_PC_REGNUM) + ? (pc_val + 8) + : get_frame_register_unsigned (frame, rn)); + if (bit (this_instr, 24)) { /* pre-indexed */ @@ -5117,7 +5122,7 @@ { ULONGEST ret; - if (regno == 15) + if (regno == ARM_PC_REGNUM) { /* Compute pipeline offset: - When executing an ARM instruction, PC reads as the address of the @@ -5231,7 +5236,7 @@ displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc, int regno, ULONGEST val, enum pc_write_style write_pc) { - if (regno == 15) + if (regno == ARM_PC_REGNUM) { if (debug_displaced) fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n", @@ -5481,11 +5486,11 @@ if (dsc->u.branch.link) { - ULONGEST pc = displaced_read_reg (regs, from, 15); - displaced_write_reg (regs, dsc, 14, pc - 4, CANNOT_WRITE_PC); + ULONGEST pc = displaced_read_reg (regs, from, ARM_PC_REGNUM); + displaced_write_reg (regs, dsc, ARM_LR_REGNUM, pc - 4, CANNOT_WRITE_PC); } - displaced_write_reg (regs, dsc, 15, dsc->u.branch.dest, write_pc); + displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc); } /* Copy B/BL/BLX instructions with immediate destinations. */ @@ -5976,7 +5981,7 @@ of this can be found in Section "Saving from r15" in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */ - if (load || rt != 15) + if (load || rt != ARM_PC_REGNUM) { dsc->u.ldst.restore_r4 = 0; @@ -6077,7 +6082,7 @@ uint32_t memword; if (inc) - while (regno <= 15 && (regmask & (1 << regno)) == 0) + while (regno <= ARM_PC_REGNUM && (regmask & (1 << regno)) == 0) regno++; else while (regno >= 0 && (regmask & (1 << regno)) == 0) @@ -6159,7 +6164,7 @@ ULONGEST from = dsc->insn_addr; uint32_t status = displaced_read_reg (regs, from, ARM_PS_REGNUM); int load_executed = condition_true (dsc->u.block.cond, status), i; - unsigned int mask = dsc->u.block.regmask, write_reg = 15; + unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM; unsigned int regs_loaded = bitcount (mask); unsigned int num_to_shuffle = regs_loaded, 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