Re: [try 2nd 5/8] Displaced stepping for Thumb 32-bit insns

Ulrich Weigand
2011-05-27T22:11:30Z

Yao Qi wrote:
> On 05/18/2011 01:14 AM, Ulrich Weigand wrote:
> > In fact, unless I'm missing something, in Thumb mode no coprocessor
> > instruction actually uses the PC (either RN == 15 indicates some other
> > operation, or else it is specified as unpredictable). So those should
> > simply all be copied unmodified ...
>
> I can understand almost of your comments except this one. I think you
> are right, but there are still some cases that PC is used in this
> category of instructions.
>
> thumb2_copy_copro_load_store covers instructions STC/STC2, VLDR/VSTR and
> LDC/LDC2 (literal and immediate). I re-read ARM ARM again, and find that,
>
> STC/STC2 doesn't use PC. ARM ARM said "if n == 15 && (wback ||
> CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE;"
>
> VSTR doesn't use PC. ARM ARM said "if n == 15 && CurrentInstrSet() !=
> InstrSet_ARM then UNPREDICTABLE;"
>
> However, LDC/LDC2/VLDR can use PC.
>
> VLDR<c>{.32} <Sd>, [PC, #+/-<imm>]
>
> LDC, LDC2 (literal or immediate)
> LDC{L}<c> <coproc>,<CRd>,[PC],
>
> I can write a real VLDR instruction using PC successfully. Still no
> luck to fix 'Illegal instruction' when running program having LDC/LDC2
> using PC register, but I think LDC/LDC2 should be able to use PC
> register. Am I missing something here?

No, you're right -- I had overlooked those. LDC/LDC2/VLDR must
indeed be handled here.

Bye,
Ulrich

--
Dr. Ulrich Weigand
GNU Toolchain for Linux on System z and Cell BE
Ulrich.Weigand@de.ibm.com