From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 14107 invoked by alias); 25 Dec 2010 14:13:36 -0000 Received: (qmail 14099 invoked by uid 22791); 25 Dec 2010 14:13:35 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL,BAYES_00,TW_EG,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sat, 25 Dec 2010 14:13:30 +0000 Received: (qmail 19473 invoked from network); 25 Dec 2010 14:13:26 -0000 Received: from unknown (HELO ?192.168.0.101?) (yao@127.0.0.2) by mail.codesourcery.com with ESMTPA; 25 Dec 2010 14:13:26 -0000 Message-ID: <4D15FBFC.5060909@codesourcery.com> Date: Sat, 25 Dec 2010 14:22:00 -0000 From: Yao Qi User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.13) Gecko/20101208 Thunderbird/3.1.7 MIME-Version: 1.0 To: gdb-patches@sourceware.org Subject: Re: [patch 1/3] Displaced stepping for 16-bit Thumb instructions References: <4D15F9B8.5070705@codesourcery.com> In-Reply-To: <4D15F9B8.5070705@codesourcery.com> Content-Type: multipart/mixed; boundary="------------050902010905020101020001" X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2010-12/txt/msg00460.txt.bz2 This is a multi-part message in MIME format. --------------050902010905020101020001 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Content-length: 85 Patch 1 is about refactoring, without any effect on functionality. -- Yao (齐尧) --------------050902010905020101020001 Content-Type: text/x-patch; name="arm_disp_step_refactor_for_thumb_p1.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="arm_disp_step_refactor_for_thumb_p1.patch" Content-length: 4415 2010-12-25 Yao Qi * gdb/arm-tdep.c (arm_displaced_step_copy_insn): Move code to ... (arm_process_displaced_insn): .. here. Remove parameter INSN. (thumb_process_displaced_insn): New. * gdb/arm-linux-tdep.c (arm_linux_displaced_step_copy_insn): Update call to arm_process_displaced_insn. * gdb/arm-tdep.h : Update declaration of arm_process_displaced_insn. diff --git a/gdb/arm-linux-tdep.c b/gdb/arm-linux-tdep.c index 4758ded..06f386a 100644 --- a/gdb/arm-linux-tdep.c +++ b/gdb/arm-linux-tdep.c @@ -913,18 +913,10 @@ arm_linux_displaced_step_copy_insn (struct gdbarch *gdbarch, } else { - enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); - uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order); - - if (debug_displaced) - fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx " - "at %.8lx\n", (unsigned long) insn, - (unsigned long) from); - /* Override the default handling of SVC instructions. */ dsc->u.svc.copy_svc_os = arm_linux_copy_svc; - arm_process_displaced_insn (gdbarch, insn, from, to, regs, dsc); + arm_process_displaced_insn (gdbarch, from, to, regs, dsc); } arm_displaced_init_closure (gdbarch, from, to, dsc); diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index d4013c6..64aa500 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -5837,16 +5837,22 @@ decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to, else return copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */ } +static void +thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, + CORE_ADDR to, struct regcache *regs, + struct displaced_step_closure *dsc) +{ + error (_("Displaced stepping is only supported in ARM mode")); +} void -arm_process_displaced_insn (struct gdbarch *gdbarch, uint32_t insn, - CORE_ADDR from, CORE_ADDR to, struct regcache *regs, +arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, + CORE_ADDR to, struct regcache *regs, struct displaced_step_closure *dsc) { int err = 0; - - if (!displaced_in_arm_mode (regs)) - error (_("Displaced stepping is only supported in ARM mode")); + enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); + uint32_t insn; /* Most displaced instructions use a 1-instruction scratch space, so set this here and override below if/when necessary. */ @@ -5856,6 +5862,15 @@ arm_process_displaced_insn (struct gdbarch *gdbarch, uint32_t insn, dsc->cleanup = NULL; dsc->wrote_to_pc = 0; + if (!displaced_in_arm_mode (regs)) + return thumb_process_displaced_insn (gdbarch, from, to, regs, dsc); + + insn = read_memory_unsigned_integer (from, 4, byte_order_for_code); + if (debug_displaced) + fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx " + "at %.8lx\n", (unsigned long) insn, + (unsigned long) from); + if ((insn & 0xf0000000) == 0xf0000000) err = decode_unconditional (gdbarch, insn, regs, dsc); else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24)) @@ -5926,15 +5941,7 @@ arm_displaced_step_copy_insn (struct gdbarch *gdbarch, { struct displaced_step_closure *dsc = xmalloc (sizeof (struct displaced_step_closure)); - enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); - uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code); - - if (debug_displaced) - fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx " - "at %.8lx\n", (unsigned long) insn, - (unsigned long) from); - - arm_process_displaced_insn (gdbarch, insn, from, to, regs, dsc); + arm_process_displaced_insn (gdbarch, from, to, regs, dsc); arm_displaced_init_closure (gdbarch, from, to, dsc); return dsc; diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h index 61cdb5d..cfb85ff 100644 --- a/gdb/arm-tdep.h +++ b/gdb/arm-tdep.h @@ -284,9 +284,8 @@ enum pc_write_style }; extern void - arm_process_displaced_insn (struct gdbarch *gdbarch, uint32_t insn, - CORE_ADDR from, CORE_ADDR to, - struct regcache *regs, + arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, + CORE_ADDR to, struct regcache *regs, struct displaced_step_closure *dsc); extern void arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, --------------050902010905020101020001--