From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 24427 invoked by alias); 10 Dec 2010 15:07:06 -0000 Received: (qmail 24413 invoked by uid 22791); 10 Dec 2010 15:07:04 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL,BAYES_00,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 10 Dec 2010 15:06:59 +0000 Received: (qmail 19026 invoked from network); 10 Dec 2010 15:06:57 -0000 Received: from unknown (HELO ?192.168.0.102?) (yao@127.0.0.2) by mail.codesourcery.com with ESMTPA; 10 Dec 2010 15:06:57 -0000 Message-ID: <4D024205.1010704@codesourcery.com> Date: Fri, 10 Dec 2010 15:07:00 -0000 From: Yao Qi User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.13) Gecko/20101208 Thunderbird/3.1.7 MIME-Version: 1.0 To: gdb-patches@sourceware.org Subject: Re: [patch, arm] Consistent display of registers in corefile References: <4D022D1A.7030701@codesourcery.com> <201012101443.oBAEhFiT023638@glazunov.sibelius.xs4all.nl> In-Reply-To: <201012101443.oBAEhFiT023638@glazunov.sibelius.xs4all.nl> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2010-12/txt/msg00139.txt.bz2 On 12/10/2010 10:43 PM, Mark Kettenis wrote: >> Date: Fri, 10 Dec 2010 21:37:30 +0800 >> From: Yao Qi >> >> GDB trunk has a test failure on ARM, >> >> FAIL: gdb.base/gcore.exp: corefile restored general registers >> >> In short, this failure is caused by output of 'info registers' before >> coredump doesn't match output of 'info registers' when corefole is >> loaded again, there are mainly two differences, [1] and [2]. >> >> Output before coredump, >> r0 0x12008 73736^M >> r1 0xbea1f0c0 -1096683328^M >> [...] >> sp 0xbea1f0a4 0xbea1f0a4^M >> lr 0x849b 33947^M >> pc 0x83fc 0x83fc ^M >> cpsr 0x20000030 536870960^M >> >> Output when corefile is loaded, >> r0 0x12008 73736^M >> r1 0xbea1f0c0 3198283968^M // <---- [1] >> [...] >> sp 0xbea1f0a4 0xbea1f0a4^M >> lr 0x849b 33947^M >> pc 0x83fc 0x83fc ^M >> fps 0x727a622f 1920623151^M // <---- [2] >> cpsr 0x20000030 536870960^M >> >> The difference [1] is caused by different register types, uint32 vs. >> int32. In tdesc, the type of general register is "int", while in >> arm_register_type, it is regarded as builtin_uint32. This can be fixed >> when register type is handled in a consistent way (in reg_type.patch). > > I would suspect that the proper thing to do would be to align the > tdesc with the code instead of the other way around. The arm-core.xml > file seems to underspecify things by omitting the type=xxx clause on > many registers. Whoever wrote arm_register_type() at least had to > make a conscious decision about the signedness of the type used for > the general purpose registers. I prefer unsigned for general purpose registers. Any objections? If we agree on this, I'll add type="uint32" to r0-r12 in arm-core.xml. -- Yao (齐尧)