From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28754 invoked by alias); 26 Oct 2007 15:23:00 -0000 Received: (qmail 28746 invoked by uid 22791); 26 Oct 2007 15:22:58 -0000 X-Spam-Check-By: sourceware.org Received: from igw2.br.ibm.com (HELO igw2.br.ibm.com) (32.104.18.25) by sourceware.org (qpsmtpd/0.31) with ESMTP; Fri, 26 Oct 2007 15:22:50 +0000 Received: from mailhub3.br.ibm.com (mailhub3 [9.18.232.110]) by igw2.br.ibm.com (Postfix) with ESMTP id 316B717F447 for ; Fri, 26 Oct 2007 13:20:04 -0200 (BRDT) Received: from d24av02.br.ibm.com (d24av02.br.ibm.com [9.18.232.47]) by mailhub3.br.ibm.com (8.13.8/8.13.8/NCO v8.5) with ESMTP id l9QFMi2t2732222 for ; Fri, 26 Oct 2007 13:22:44 -0200 Received: from d24av02.br.ibm.com (loopback [127.0.0.1]) by d24av02.br.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id l9QFMhmv020726 for ; Fri, 26 Oct 2007 12:22:43 -0300 Received: from [9.18.198.198] ([9.18.198.198]) by d24av02.br.ibm.com (8.12.11.20060308/8.12.11) with ESMTP id l9QFMgS6020704; Fri, 26 Oct 2007 12:22:43 -0300 Message-ID: <47220646.4080903@linux.vnet.ibm.com> Date: Fri, 26 Oct 2007 15:29:00 -0000 From: Carlos Eduardo Seo User-Agent: Thunderbird 2.0.0.6 (X11/20070907) MIME-Version: 1.0 To: Ulrich Weigand , GDB Patches Mailing List Subject: Re: [patch] Add support for PPC Altivec registers in core files References: <200710261501.l9QF1BII002037@d12av02.megacenter.de.ibm.com> In-Reply-To: <200710261501.l9QF1BII002037@d12av02.megacenter.de.ibm.com> OpenPGP: id=8BFFA900 Content-Type: multipart/mixed; boundary="------------090206030707010004060208" X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2007-10/txt/msg00715.txt.bz2 This is a multi-part message in MIME format. --------------090206030707010004060208 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-length: 799 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Ulrich Weigand wrote: > > Thanks. There's still some minor issues I've pointed out below. > Patch is OK with those fixed. > Cleaned up the patch. Now it's OK to commit? > > Have a look at linux_nat_do_thread_registers in linux-nat.c. This > would need to be extended to write the Altivec register section > where applicable. You may also need additional BFD support for > this. Ok, thanks. I'll take a look at it. Regards, - -- Carlos Eduardo Seo Software Engineer IBM Linux Technology Center -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.7 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFHIgZFqvq7Aov/qQARAsX3AJ9K7G4vUah9vR8vg3GOvVTXGaCyuwCeKIWM 826ENWHF9h2m80bUhwEQL5s= =xZaO -----END PGP SIGNATURE----- --------------090206030707010004060208 Content-Type: text/x-patch; name="altivec-core.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="altivec-core.diff" Content-length: 9127 2007-10-26 Carlos Eduardo Seo * ppc-linux-tdep.c (ppc32_linux_reg_offsets): Corrected swapped offsets and VRSAVE offset. (ppc64_linux_reg_offsets): Corrected swapped offsets. (ppc32_linux_vrregset): Added. (ppc_linux_regset_from_core_section): Added support for .reg-ppc-vmx section. * ppc-tdep.h (ppc_altivec_support_p): Declare. (ppc_supply_vrregset): Declare. (ppc_collect_vrregset): Declare. * rs6000-tdep.c (ppc_altivec_support_p): Added. (ppc_supply_vrregset): Added. (ppc_collect_vrregset): Added. * corelow.c (get_core_registers): Added support for .reg-ppc-vmx section. Index: gdb/ppc-linux-tdep.c =================================================================== --- gdb/ppc-linux-tdep.c.orig +++ gdb/ppc-linux-tdep.c @@ -650,8 +650,8 @@ static const struct ppc_reg_offsets ppc3 /* AltiVec registers. */ /* .vr0_offset = */ 0, - /* .vrsave_offset = */ 512, - /* .vscr_offset = */ 512 + 12 + /* .vscr_offset = */ 512 + 12, + /* .vrsave_offset = */ 528 }; static const struct ppc_reg_offsets ppc64_linux_reg_offsets = @@ -675,8 +675,8 @@ static const struct ppc_reg_offsets ppc6 /* AltiVec registers. */ /* .vr0_offset = */ 0, - /* .vrsave_offset = */ 528, - /* .vscr_offset = */ 512 + 12 + /* .vscr_offset = */ 512 + 12, + /* .vrsave_offset = */ 528 }; static const struct regset ppc32_linux_gregset = { @@ -700,6 +700,13 @@ static const struct regset ppc32_linux_f NULL }; +static const struct regset ppc32_linux_vrregset = { + &ppc32_linux_reg_offsets, + ppc_supply_vrregset, + ppc_collect_vrregset, + NULL +}; + const struct regset * ppc_linux_gregset (int wordsize) { @@ -726,6 +733,8 @@ ppc_linux_regset_from_core_section (stru } if (strcmp (sect_name, ".reg2") == 0) return &ppc32_linux_fpregset; + if (strcmp (sect_name, ".reg-ppc-vmx") == 0) + return &ppc32_linux_vrregset; return NULL; } Index: gdb/ppc-tdep.h =================================================================== --- gdb/ppc-tdep.h.orig +++ gdb/ppc-tdep.h @@ -73,6 +73,10 @@ int spe_register_p (int regno); floating-point registers (f0 --- f31 and fpscr). */ int ppc_floating_point_unit_p (struct gdbarch *gdbarch); +/* Return non-zero if the architecture described by GDBARCH has + Altivec registers (vr0 --- vr31, vrsave and vscr). */ +int ppc_altivec_support_p (struct gdbarch *gdbarch); + /* Register set description. */ struct ppc_reg_offsets @@ -116,6 +120,14 @@ extern void ppc_supply_fpregset (const s struct regcache *regcache, int regnum, const void *fpregs, size_t len); +/* Supply register REGNUM in the Altivec register set REGSET + from the buffer specified by VRREGS and LEN to register cache + REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ + +extern void ppc_supply_vrregset (const struct regset *regset, + struct regcache *regcache, + int regnum, const void *vrregs, size_t len); + /* Collect register REGNUM in the general-purpose register set REGSET. from register cache REGCACHE into the buffer specified by GREGS and LEN. If REGNUM is -1, do this for all registers in @@ -134,6 +146,15 @@ extern void ppc_collect_fpregset (const const struct regcache *regcache, int regnum, void *fpregs, size_t len); +/* Collect register REGNUM in the Altivec register set + REGSET from register cache REGCACHE into the buffer specified by + VRREGS and LEN. If REGNUM is -1, do this for all registers in + REGSET. */ + +extern void ppc_collect_vrregset (const struct regset *regset, + const struct regcache *regcache, + int regnum, void *vrregs, size_t len); + /* Private data that this module attaches to struct gdbarch. */ struct gdbarch_tdep Index: gdb/rs6000-tdep.c =================================================================== --- gdb/rs6000-tdep.c.orig +++ gdb/rs6000-tdep.c @@ -194,6 +194,16 @@ ppc_floating_point_unit_p (struct gdbarc && tdep->ppc_fpscr_regnum >= 0); } +/* Return non-zero if the architecture described by GDBARCH has + Altivec registers (vr0 --- vr31, vrsave and vscr). */ +int +ppc_altivec_support_p (struct gdbarch *gdbarch) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + return (tdep->ppc_vr0_regnum >= 0 + && tdep->ppc_vrsave_regnum >= 0); +} /* Check that TABLE[GDB_REGNO] is not already initialized, and then set it to SIM_REGNO. @@ -436,6 +446,24 @@ ppc_fpreg_offset (struct gdbarch_tdep *t return -1; } +static int +ppc_vrreg_offset (struct gdbarch_tdep *tdep, + const struct ppc_reg_offsets *offsets, + int regnum) +{ + if (regnum >= tdep->ppc_vr0_regnum + && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs) + return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16; + + if (regnum == tdep->ppc_vrsave_regnum - 1) + return offsets->vscr_offset; + + if (regnum == tdep->ppc_vrsave_regnum) + return offsets->vrsave_offset; + + return -1; +} + /* Supply register REGNUM in the general-purpose register set REGSET from the buffer specified by GREGS and LEN to register cache REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ @@ -518,6 +546,50 @@ ppc_supply_fpregset (const struct regset regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); } +/* Supply register REGNUM in the Altivec register set REGSET + from the buffer specified by VRREGS and LEN to register cache + REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ + +void +ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache, + int regnum, const void *vrregs, size_t len) +{ + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep; + const struct ppc_reg_offsets *offsets; + size_t offset; + + if (!ppc_altivec_support_p (gdbarch)) + return; + + tdep = gdbarch_tdep (gdbarch); + offsets = regset->descr; + if (regnum == -1) + { + int i; + + for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset; + i < tdep->ppc_vr0_regnum + ppc_num_vrs; + i++, offset += 16) + ppc_supply_reg (regcache, i, vrregs, offset, 16); + + ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1), + vrregs, offsets->vscr_offset, 4); + + ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum, + vrregs, offsets->vrsave_offset, 4); + return; + } + + offset = ppc_vrreg_offset (tdep, offsets, regnum); + if (regnum != tdep->ppc_vrsave_regnum + && regnum != tdep->ppc_vrsave_regnum - 1) + ppc_supply_reg (regcache, regnum, vrregs, offset, 16); + else + ppc_supply_reg (regcache, regnum, + vrregs, offset, 4); +} + /* Collect register REGNUM in the general-purpose register set REGSET from register cache REGCACHE into the buffer specified by GREGS and LEN. If REGNUM is -1, do this for all registers in @@ -603,6 +675,52 @@ ppc_collect_fpregset (const struct regse ppc_collect_reg (regcache, regnum, fpregs, offset, regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); } + +/* Collect register REGNUM in the Altivec register set + REGSET from register cache REGCACHE into the buffer specified by + VRREGS and LEN. If REGNUM is -1, do this for all registers in + REGSET. */ + +void +ppc_collect_vrregset (const struct regset *regset, + const struct regcache *regcache, + int regnum, void *vrregs, size_t len) +{ + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep; + const struct ppc_reg_offsets *offsets; + size_t offset; + + if (!ppc_altivec_support_p (gdbarch)) + return; + + tdep = gdbarch_tdep (gdbarch); + offsets = regset->descr; + if (regnum == -1) + { + int i; + + for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset; + i < tdep->ppc_vr0_regnum + ppc_num_vrs; + i++, offset += 16) + ppc_collect_reg (regcache, i, vrregs, offset, 16); + + ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1), + vrregs, offsets->vscr_offset, 4); + + ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum, + vrregs, offsets->vrsave_offset, 4); + return; + } + + offset = ppc_vrreg_offset (tdep, offsets, regnum); + if (regnum != tdep->ppc_vrsave_regnum + && regnum != tdep->ppc_vrsave_regnum - 1) + ppc_collect_reg (regcache, regnum, vrregs, offset, 16); + else + ppc_collect_reg (regcache, regnum, + vrregs, offset, 4); +} /* Read a LEN-byte address from debugged memory address MEMADDR. */ Index: gdb/corelow.c =================================================================== --- gdb/corelow.c.orig +++ gdb/corelow.c @@ -499,6 +499,8 @@ get_core_registers (struct regcache *reg ".reg2", 2, "floating-point", 0); get_core_register_section (regcache, ".reg-xfp", 3, "extended floating-point", 0); + get_core_register_section (regcache, + ".reg-ppc-vmx", 3, "ppc Altivec", 0); /* Supply dummy value for all registers not found in the core. */ for (i = 0; i < gdbarch_num_regs (current_gdbarch); i++) --------------090206030707010004060208 Content-Type: application/octet-stream; name="altivec-core.diff.sig" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="altivec-core.diff.sig" Content-length: 90 iD8DBQBHIgZFqvq7Aov/qQARAkoLAJ9sNNxEZFTzz0CHA7YHMZfgufnP3wCg gH25UjNlj52uribuHwgQHngxxE4= --------------090206030707010004060208--