From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26069 invoked by alias); 24 Sep 2007 14:44:57 -0000 Received: (qmail 26033 invoked by uid 22791); 24 Sep 2007 14:44:56 -0000 X-Spam-Check-By: sourceware.org Received: from s200aog14.obsmtp.com (HELO s200aog14.obsmtp.com) (207.126.144.128) by sourceware.org (qpsmtpd/0.31) with ESMTP; Mon, 24 Sep 2007 14:44:49 +0000 Received: from source ([164.129.1.35]) (using TLSv1) by eu1sys200aob014.postini.com ([207.126.147.11]) with SMTP; Mon, 24 Sep 2007 14:44:46 UTC Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8A3E2DAAC for ; Mon, 24 Sep 2007 14:44:37 +0000 (GMT) Received: from mail1.bri.st.com (mail1.bri.st.com [164.129.8.218]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 32C104C1FD for ; Mon, 24 Sep 2007 14:44:37 +0000 (GMT) Received: from [164.129.15.13] (bri1043.bri.st.com [164.129.15.13]) by mail1.bri.st.com (MOS 3.7.5a-GA) with ESMTP id CJG51166 (AUTH stubbsa); Mon, 24 Sep 2007 15:44:35 +0100 (BST) Message-ID: <46F7CD53.704@st.com> Date: Mon, 24 Sep 2007 14:44:00 -0000 From: Andrew STUBBS User-Agent: Thunderbird 2.0.0.6 (Windows/20070728) MIME-Version: 1.0 To: GDB Patches Subject: [PATCH] SH simulator illegal instructions Content-Type: multipart/mixed; boundary="------------040703050809000807040606" X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2007-09/txt/msg00341.txt.bz2 This is a multi-part message in MIME format. --------------040703050809000807040606 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-length: 415 Hi, The SH simulator currently accepts some instructions in delay slots that should not be allowed. Specifically: mov.l @(,PC), mov.w @(,PC), mova @(,PC),R0 I have checked the remaining SH-4 instructions, and don't believe there are any more, however I have not checked other architecture variants. The attached patch add the proper check. :ADDPATCH sh sim: Andrew Stubbs --------------040703050809000807040606 Content-Type: text/plain; name="illslot.patch" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="illslot.patch" Content-length: 937 2007-09-24 Andrew Stubbs * gencode.c (tab): Add RAISE_EXCEPTION_IF_IN_DELAY_SLOT to the definition of PC relative 'mov.l'/'mov.w' and also 'mova'. --- orig/sim/sh/gencode.c 2007-03-06 13:58:46.000000000 +0000 +++ src/sim/sh/gencode.c 2007-09-24 15:02:18.000000000 +0100 @@ -993,6 +993,7 @@ "L (0);", }, { "n", "", "mov.l @(,PC),", "1101nnnni8p4....", + "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", "MA (1);", "R[n] = RLAT ((PH2T (PC) & ~3) + 4 + i);", "L (n);", @@ -1059,6 +1060,7 @@ "L (0);", }, { "n", "", "mov.w @(,PC),", "1001nnnni8p2....", + "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", "MA (1);", "R[n] = RSWAT (PH2T (PC + 4 + i));", "L (n);", @@ -1120,6 +1122,7 @@ }, { "0", "", "mova @(,PC),R0", "11000111i8p4....", + "RAISE_EXCEPTION_IF_IN_DELAY_SLOT ();", "R0 = ((i + 4 + PH2T (PC)) & ~0x3);", }, --------------040703050809000807040606--