[patch][rfc]: Update sh64 Simulator to Match Pending CGEN Changes

Dave Brolley
2006-08-22T18:36:19Z

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Hi,

Once the corresponding CGEN changes are approved, I would like to commit
this patch which brings the sh64 simulator up to date. The CGEN changes
in question were to allow the generation of a SID simulator with full
pipeline modelling and to add support for some unsupported insns. The
effects on the sh64 simulator are as follows:

1) Add code to support additional CGEN machines which were added.
2) Add code to support newly supported insns.
3) Regenerate all CGEN-generated source files. Some bit rot in the
invocation of CGEN was fixed here in the process.

Pending approval of the corresponding CGEN changes, is this ok to commit?

Dave

[-- Attachment #2: sim-sh64.ChangeLog --]
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opcodes/ChangeLog:
2006-08-22 Dave Brolley <brolley@redhat.com>

* Contribute the following changes:
2006-05-10 Dave Brolley <brolley@redhat.com>

* configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
* configure: Regenerated.

sim/sh64/ChangeLog:
2006-08-22 Dave Brolley <brolley@redhat.com>

* sh64-sim.h (sh64_movua): New function.
* sh64.c (sh64_movua): New function.
* Contribute the following changes:
2006-06-14 Dave Brolley <brolley@redhat.com>

* sh64-sim.h (sh64_fipr,sh64_fiprs,sh64_fldp,sh64_fstp,sh64_ftrv)
(sh64_fpref): New functions.
* sh64.c (sh64_fipr,sh64_fiprs,sh64_fldp,sh64_fstp,sh64_ftrv)
(sh64_fpref): New functions.
(sh_models): Add sh2e, sh2a, sh2a_nofpu, sh4_nofpu, sh4a,
sh4a_nofpu and sh4al.
(sh2e_mach): New MACH.
(sh2a_fpu_mach): New MACH.
(sh2a_nofpu_mach): New MACH.
(sh4_nofpu): New MACH.
(sh4a_mach): New MACH.
(sh4a_nofpu_mach): New MACH.
(sh4al_mach): New MACH.
* Makefile.in (stamp-*): Depend on $(CGEN_CPU_DIR)/sh-sim.cpu. Pass
archfile to CGEN script.
* arch.c: Regenerated.
* arch.h: Regenerated.
* cpu.c: Regenerated.
* cpu.h: Regenerated.
* cpuall.h: Regenerated.
* decode-compact.c: Regenerated.
* decode-compact.h: Regenerated.
* decode-media.c: Regenerated.
* decode-media.h: Regenerated.
* defs-compact.h: Regenerated.
* defs-media.h: Regenerated.
* sem-compact-switch.c: Regenerated.
* sem-compact.c: Regenerated.
* sem-media-switch.c: Regenerated.
* sem-media.c: Regenerated.
* sh-desc.c: Regenerated.
* sh-desc.h: Regenerated.
* sh-opc.h: Regenerated.

[-- Attachment #3: sim-sh64.patch.txt --]
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Index: opcodes/configure.in
===================================================================
RCS file: /cvs/src/src/opcodes/configure.in,v
retrieving revision 1.70
diff -c -p -r1.70 configure.in
*** opcodes/configure.in 31 May 2006 15:14:39 -0000 1.70
--- opcodes/configure.in 22 Aug 2006 17:22:37 -0000
*************** if test x${all_targets} = xfalse ; then
*** 215,221 ****
break;;
esac;
done
! ta="$ta sh-dis.lo" ;;
bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;;
bfd_tahoe_arch) ;;
bfd_tic30_arch) ta="$ta tic30-dis.lo" ;;
--- 215,221 ----
break;;
esac;
done
! ta="$ta sh-dis.lo cgen-bitset.lo" ;;
bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;;
bfd_tahoe_arch) ;;
bfd_tic30_arch) ta="$ta tic30-dis.lo" ;;
Index: sim/sh64/Makefile.in
===================================================================
RCS file: /cvs/src/src/sim/sh64/Makefile.in,v
retrieving revision 1.1
diff -c -p -r1.1 Makefile.in
*** sim/sh64/Makefile.in 1 Feb 2002 11:44:26 -0000 1.1
--- sim/sh64/Makefile.in 22 Aug 2006 17:22:47 -0000
*************** stamp-all: stamp-arch stamp-desc stamp-c
*** 104,153 ****
stamp-decode: stamp-decode-compact stamp-decode-media
stamp-defs: stamp-defs-compact stamp-defs-media

! stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh64-compact.cpu Makefile
! $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all isa=compact,media \
FLAGS="with-scache"
touch $@
! arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
@true

! stamp-desc: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu Makefile
! $(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) cpu=sh64 mach=all isa=compact,media
touch $@
desc.h: $(CGEN_MAINT) stamp-desc
@true

! stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu Makefile
$(MAKE) cgen-cpu $(CGEN_FLAGS_TO_PASS) \
! cpu=sh64 mach=sh4,sh5 isa=compact,media FLAGS="with-multiple-isa with-scache"
rm -f $(srcdir)/model.c
touch $@
cpu.h: $(CGEN_MAINT) stamp-cpu
@true

! stamp-defs-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu Makefile
$(MAKE) cgen-defs $(CGEN_FLAGS_TO_PASS) \
! cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact"
touch $@
defs-compact.h: $(CGEN_MAINT) stamp-defs-compact
@true

! stamp-defs-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu Makefile
$(MAKE) cgen-defs $(CGEN_FLAGS_TO_PASS) \
! cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media"
touch $@
defs-media.h: $(CGEN_MAINT) stamp-defs-media

! stamp-decode-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu Makefile
$(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \
! cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
touch $@
! sem-compact.c sem-compact-switch.c decode-compact.c decode-compact.h: $(CGEN_MAINT) stamp-compact
@true

! stamp-decode-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu Makefile
$(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \
! cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
touch $@
! sem-media.c sem-media-switch.c decode-media.c decode-media.h: $(CGEN_MAINT) stamp-media
@true
--- 104,155 ----
stamp-decode: stamp-decode-compact stamp-decode-media
stamp-defs: stamp-defs-compact stamp-defs-media

! stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
! $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all isa=compact,media archfile=$(CGEN_CPU_DIR)/sh.cpu \
FLAGS="with-scache"
touch $@
! arch.h ${srcdir}/arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
@true

! stamp-desc: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
! $(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) cpu=sh64 mach=all isa=compact,media archfile=$(CGEN_CPU_DIR)/sh.cpu
touch $@
desc.h: $(CGEN_MAINT) stamp-desc
@true

! stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-cpu $(CGEN_FLAGS_TO_PASS) \
! cpu=sh64 mach=sh4,sh5 isa=compact,media FLAGS="with-multiple-isa with-scache" archfile=$(CGEN_CPU_DIR)/sh.cpu
rm -f $(srcdir)/model.c
touch $@
cpu.h: $(CGEN_MAINT) stamp-cpu
@true

! stamp-defs-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-defs $(CGEN_FLAGS_TO_PASS) \
! cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact" archfile=$(CGEN_CPU_DIR)/sh.cpu
touch $@
defs-compact.h: $(CGEN_MAINT) stamp-defs-compact
@true

! stamp-defs-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-defs $(CGEN_FLAGS_TO_PASS) \
! cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media" archfile=$(CGEN_CPU_DIR)/sh.cpu
touch $@
defs-media.h: $(CGEN_MAINT) stamp-defs-media

! stamp-decode-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \
! cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)" \
! archfile=$(CGEN_CPU_DIR)/sh.cpu
touch $@
! sem-compact.c sem-compact-switch.c decode-compact.c decode-compact.h: $(CGEN_MAINT) stamp-decode-compact
@true

! stamp-decode-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \
! cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)" \
! archfile=$(CGEN_CPU_DIR)/sh.cpu
touch $@
! sem-media.c sem-media-switch.c decode-media.c decode-media.h: $(CGEN_MAINT) stamp-decode-media
@true
Index: sim/sh64/sh64-sim.h
===================================================================
RCS file: /cvs/src/src/sim/sh64/sh64-sim.h,v
retrieving revision 1.1
diff -c -p -r1.1 sh64-sim.h
*** sim/sh64/sh64-sim.h 1 Feb 2002 11:44:27 -0000 1.1
--- sim/sh64/sh64-sim.h 22 Aug 2006 17:22:50 -0000
***************
*** 1,5 ****
/* collection of junk waiting time to sort out
! Copyright (C) 2000 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.

This file is part of the GNU Simulators.
--- 1,5 ----
/* collection of junk waiting time to sort out
! Copyright (C) 2000, 2006 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.

This file is part of the GNU Simulators.
*************** extern IDESC * sh64_idesc_compact;
*** 42,47 ****
--- 42,48 ----

BI sh64_endian (SIM_CPU *);
VOID sh64_break (SIM_CPU *, PCADDR);
+ SI sh64_movua (SIM_CPU *, PCADDR, SI);
VOID sh64_trapa (SIM_CPU *, DI, PCADDR);
VOID sh64_compact_trapa (SIM_CPU *, UQI, PCADDR);

*************** DF sh64_ftrcdq (SIM_CPU *, DF);
*** 74,80 ****
SF sh64_ftrcsl (SIM_CPU *, SF);
DF sh64_ftrcsq (SIM_CPU *, SF);
VOID sh64_ftrvs (SIM_CPU *, unsigned, unsigned, unsigned);
!
BI sh64_fcmpeqs (SIM_CPU *, SF, SF);
BI sh64_fcmpeqd (SIM_CPU *, DF, DF);
BI sh64_fcmpges (SIM_CPU *, SF, SF);
--- 75,86 ----
SF sh64_ftrcsl (SIM_CPU *, SF);
DF sh64_ftrcsq (SIM_CPU *, SF);
VOID sh64_ftrvs (SIM_CPU *, unsigned, unsigned, unsigned);
! VOID sh64_fipr (SIM_CPU *cpu, unsigned m, unsigned n);
! SF sh64_fiprs (SIM_CPU *cpu, unsigned g, unsigned h);
! VOID sh64_fldp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f);
! VOID sh64_fstp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f);
! VOID sh64_ftrv (SIM_CPU *cpu, UINT ignored);
! VOID sh64_pref (SIM_CPU *cpu, SI addr);
BI sh64_fcmpeqs (SIM_CPU *, SF, SF);
BI sh64_fcmpeqd (SIM_CPU *, DF, DF);
BI sh64_fcmpges (SIM_CPU *, SF, SF);
Index: sim/sh64/sh64.c
===================================================================
RCS file: /cvs/src/src/sim/sh64/sh64.c,v
retrieving revision 1.2
diff -c -p -r1.2 sh64.c
*** sim/sh64/sh64.c 24 Jun 2002 13:26:07 -0000 1.2
--- sim/sh64/sh64.c 22 Aug 2006 17:22:50 -0000
***************
*** 1,5 ****
/* SH5 simulator support code
! Copyright (C) 2000, 2001 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.

This file is part of the GNU simulators.
--- 1,5 ----
/* SH5 simulator support code
! Copyright (C) 2000, 2001, 2006 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.

This file is part of the GNU simulators.
*************** sh64_ftrcsq(SIM_CPU *current_cpu, SF frg
*** 460,466 ****
return (DF) result;
}

! void
sh64_ftrvs(SIM_CPU *cpu, unsigned g, unsigned h, unsigned f)
{
int i, j;
--- 460,466 ----
return (DF) result;
}

! VOID
sh64_ftrvs(SIM_CPU *cpu, unsigned g, unsigned h, unsigned f)
{
int i, j;
*************** sh64_ftrvs(SIM_CPU *cpu, unsigned g, uns
*** 484,489 ****
--- 484,535 ----
}
}

+ VOID
+ sh64_fipr (SIM_CPU *cpu, unsigned m, unsigned n)
+ {
+ SF result = sh64_fmuls (cpu, sh64_h_fvc_get (cpu, m), sh64_h_fvc_get (cpu, n));
+ result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 1), sh64_h_frc_get (cpu, n + 1)));
+ result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 2), sh64_h_frc_get (cpu, n + 2)));
+ result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 3), sh64_h_frc_get (cpu, n + 3)));
+ sh64_h_frc_set (cpu, n + 3, result);
+ }
+
+ SF
+ sh64_fiprs (SIM_CPU *cpu, unsigned g, unsigned h)
+ {
+ SF temp = sh64_fmuls (cpu, sh64_h_fr_get (cpu, g), sh64_h_fr_get (cpu, h));
+ temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 1), sh64_h_fr_get (cpu, h + 1)));
+ temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 2), sh64_h_fr_get (cpu, h + 2)));
+ temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 3), sh64_h_fr_get (cpu, h + 3)));
+ return temp;
+ }
+
+ VOID
+ sh64_fldp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f)
+ {
+ sh64_h_fr_set (cpu, f, GETMEMSF (cpu, pc, rm + rn));
+ sh64_h_fr_set (cpu, f + 1, GETMEMSF (cpu, pc, rm + rn + 4));
+ }
+
+ VOID
+ sh64_fstp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f)
+ {
+ SETMEMSF (cpu, pc, rm + rn, sh64_h_fr_get (cpu, f));
+ SETMEMSF (cpu, pc, rm + rn + 4, sh64_h_fr_get (cpu, f + 1));
+ }
+
+ VOID
+ sh64_ftrv (SIM_CPU *cpu, UINT ignored)
+ {
+ /* TODO: Unimplemented. */
+ }
+
+ VOID
+ sh64_pref (SIM_CPU *cpu, SI addr)
+ {
+ /* TODO: Unimplemented. */
+ }
+
/* Count the number of arguments. */
static int
count_argc (cpu)
*************** sh64_break (SIM_CPU *current_cpu, PCADDR
*** 688,693 ****
--- 734,755 ----
sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
}

+ SI
+ sh64_movua (SIM_CPU *current_cpu, PCADDR pc, SI rn)
+ {
+ SI v;
+ int i;
+
+ /* Move the data one byte at a time to avoid alignment problems.
+ Be aware of endianness. */
+ v = 0;
+ for (i = 0; i < 4; ++i)
+ v = (v << 8) | (GETMEMQI (current_cpu, pc, rn + i) & 0xff);
+
+ v = T2H_4 (v);
+ return v;
+ }
+
void
set_isa (SIM_CPU *current_cpu, int mode)
{
*************** sh64_model_init()
*** 971,981 ****

static const MODEL sh_models [] =
{
! { "sh2", & sh2_mach, MODEL_SH5, NULL, sh64_model_init },
! { "sh3", & sh3_mach, MODEL_SH5, NULL, sh64_model_init },
! { "sh3e", & sh3_mach, MODEL_SH5, NULL, sh64_model_init },
! { "sh4", & sh4_mach, MODEL_SH5, NULL, sh64_model_init },
! { "sh5", & sh5_mach, MODEL_SH5, NULL, sh64_model_init },
{ 0 }
};

--- 1033,1050 ----

static const MODEL sh_models [] =
{
! { "sh2", & sh2_mach, MODEL_SH5, NULL, sh64_model_init },
! { "sh2e", & sh2e_mach, MODEL_SH5, NULL, sh64_model_init },
! { "sh2a", & sh2a_fpu_mach, MODEL_SH5, NULL, sh64_model_init },
! { "sh2a_nofpu", & sh2a_nofpu_mach, MODEL_SH5, NULL, sh64_model_init },
! { "sh3", & sh3_mach, MODEL_SH5, NULL, sh64_model_init },
! { "sh3e", & sh3_mach, MODEL_SH5, NULL, sh64_model_init },
! { "sh4", & sh4_mach, MODEL_SH5, NULL, sh64_model_init },
! { "sh4_nofpu", & sh4_nofpu_mach, MODEL_SH5, NULL, sh64_model_init },
! { "sh4a", & sh4a_mach, MODEL_SH5, NULL, sh64_model_init },
! { "sh4a_nofpu", & sh4a_nofpu_mach, MODEL_SH5, NULL, sh64_model_init },
! { "sh4al", & sh4al_mach, MODEL_SH5, NULL, sh64_model_init },
! { "sh5", & sh5_mach, MODEL_SH5, NULL, sh64_model_init },
{ 0 }
};

*************** const MACH sh2_mach =
*** 997,1006 ****
sh64_prepare_run
};

const MACH sh3_mach =
{
"sh3", "sh3", MACH_SH5,
! 16, 16, &sh_models[1], &sh5_imp_properties,
shcompact_init_cpu,
sh64_prepare_run
};
--- 1066,1099 ----
sh64_prepare_run
};

+ const MACH sh2e_mach =
+ {
+ "sh2e", "sh2e", MACH_SH5,
+ 16, 16, &sh_models[1], &sh5_imp_properties,
+ shcompact_init_cpu,
+ sh64_prepare_run
+ };
+
+ const MACH sh2a_fpu_mach =
+ {
+ "sh2a", "sh2a", MACH_SH5,
+ 16, 16, &sh_models[2], &sh5_imp_properties,
+ shcompact_init_cpu,
+ sh64_prepare_run
+ };
+
+ const MACH sh2a_nofpu_mach =
+ {
+ "sh2a_nofpu", "sh2a_nofpu", MACH_SH5,
+ 16, 16, &sh_models[3], &sh5_imp_properties,
+ shcompact_init_cpu,
+ sh64_prepare_run
+ };
+
const MACH sh3_mach =
{
"sh3", "sh3", MACH_SH5,
! 16, 16, &sh_models[4], &sh5_imp_properties,
shcompact_init_cpu,
sh64_prepare_run
};
*************** const MACH sh3_mach =
*** 1008,1014 ****
const MACH sh3e_mach =
{
"sh3e", "sh3e", MACH_SH5,
! 16, 16, &sh_models[2], &sh5_imp_properties,
shcompact_init_cpu,
sh64_prepare_run
};
--- 1101,1107 ----
const MACH sh3e_mach =
{
"sh3e", "sh3e", MACH_SH5,
! 16, 16, &sh_models[5], &sh5_imp_properties,
shcompact_init_cpu,
sh64_prepare_run
};
*************** const MACH sh3e_mach =
*** 1016,1022 ****
const MACH sh4_mach =
{
"sh4", "sh4", MACH_SH5,
! 16, 16, &sh_models[3], &sh5_imp_properties,
shcompact_init_cpu,
sh64_prepare_run
};
--- 1109,1147 ----
const MACH sh4_mach =
{
"sh4", "sh4", MACH_SH5,
! 16, 16, &sh_models[6], &sh5_imp_properties,
! shcompact_init_cpu,
! sh64_prepare_run
! };
!
! const MACH sh4_nofpu_mach =
! {
! "sh4_nofpu", "sh4_nofpu", MACH_SH5,
! 16, 16, &sh_models[7], &sh5_imp_properties,
! shcompact_init_cpu,
! sh64_prepare_run
! };
!
! const MACH sh4a_mach =
! {
! "sh4a", "sh4a", MACH_SH5,
! 16, 16, &sh_models[8], &sh5_imp_properties,
! shcompact_init_cpu,
! sh64_prepare_run
! };
!
! const MACH sh4a_nofpu_mach =
! {
! "sh4a_nofpu", "sh4a_nofpu", MACH_SH5,
! 16, 16, &sh_models[9], &sh5_imp_properties,
! shcompact_init_cpu,
! sh64_prepare_run
! };
!
! const MACH sh4al_mach =
! {
! "sh4al", "sh4al", MACH_SH5,
! 16, 16, &sh_models[10], &sh5_imp_properties,
shcompact_init_cpu,
sh64_prepare_run
};
*************** const MACH sh4_mach =
*** 1024,1030 ****
const MACH sh5_mach =
{
"sh5", "sh5", MACH_SH5,
! 32, 32, &sh_models[4], &sh5_imp_properties,
shmedia_init_cpu,
sh64_prepare_run
};
--- 1149,1155 ----
const MACH sh5_mach =
{
"sh5", "sh5", MACH_SH5,
! 32, 32, &sh_models[11], &sh5_imp_properties,
shmedia_init_cpu,
sh64_prepare_run
};