From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 14732 invoked by alias); 3 Aug 2004 14:23:56 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 14725 invoked from network); 3 Aug 2004 14:23:55 -0000 Received: from unknown (HELO mx1.redhat.com) (66.187.233.31) by sourceware.org with SMTP; 3 Aug 2004 14:23:55 -0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.12.10/8.12.10) with ESMTP id i73ENte3002148 for ; Tue, 3 Aug 2004 10:23:55 -0400 Received: from localhost.redhat.com (porkchop.devel.redhat.com [172.16.58.2]) by int-mx1.corp.redhat.com (8.11.6/8.11.6) with ESMTP id i73ENia17005; Tue, 3 Aug 2004 10:23:49 -0400 Received: from gnu.org (localhost [127.0.0.1]) by localhost.redhat.com (Postfix) with ESMTP id AB2C02BA0; Tue, 3 Aug 2004 08:59:42 -0400 (EDT) Message-ID: <410F8C3E.3060502@gnu.org> Date: Tue, 03 Aug 2004 14:23:00 -0000 From: Andrew Cagney User-Agent: Mozilla/5.0 (X11; U; NetBSD macppc; en-GB; rv:1.4.1) Gecko/20040801 MIME-Version: 1.0 To: Jim Blandy Cc: gdb-patches@sources.redhat.com Subject: Re: RFA: PowerPC sim & GDB: use fixed register numbering References: In-Reply-To: Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2004-08/txt/msg00067.txt.bz2 Have a look at the other sim-*.h files, you'll notice that most define an enum namespace and not a series of magic constants. Can we expand the table so that the constants aren't needed? > + enum sim_ppc_regnum > + { > + /* General-purpose registers, r0 -- r31. */ > + sim_ppc_r0_regnum = 0, > + sim_ppc_num_gprs = 32, > + > + /* Floating-point registers, f0 -- f31. */ > + sim_ppc_f0_regnum = 32, > + sim_ppc_num_fprs = 32, > + > + /* Altivec vector registers, vr0 -- vr31. */ > + sim_ppc_vr0_regnum = 64, > + sim_ppc_num_vrs = 32, > + > + /* SPE APU GPR upper halves. These are the upper 32 bits of the > + gprs; there is one upper-half register for each gpr, so it is > + appropriate to use sim_ppc_num_gprs for iterating through > + these. */ > + sim_ppc_rh0_regnum = 96, > + > + /* SPE APU GPR full registers. Each of these registers is the > + 64-bit concatenation of a 32-bit GPR (providing the lower bits) > + and a 32-bit upper-half register (providing the higher bits). > + As for the upper-half registers, it is appropriate to use > + sim_ppc_num_gprs with these. */ > + sim_ppc_ev0_regnum = 128, > + > + /* Segment registers, sr0 -- sr15. */ > + sim_ppc_sr0_regnum = 160, > + sim_ppc_num_srs = 16, > + > + /* Miscellaneous --- but non-SPR --- registers. */ > + sim_ppc_pc_regnum = 176, > + sim_ppc_ps_regnum = 177, > + sim_ppc_cr_regnum = 178, > + sim_ppc_fpscr_regnum = 179, > + sim_ppc_acc_regnum = 180, > + sim_ppc_vscr_regnum = 181, > + > + /* Special-purpose registers. Each SPR is given a number equal to > + its number in the ISA --- the number that appears in the mtspr > + / mfspr instructions --- plus 1024. */ > + sim_ppc_spr0_regnum = 1024, > + sim_ppc_num_sprs = 1024, > + }; Looking at: > + /* A table mapping register numbers (as received from GDB) to register > + names. This table does not handle special-purpose registers: the > + SPR whose number is N is assigned the register number 1024 + N. */ > + static const char *gdb_register_name_table[] = { > + > + /* General-purpose registers: 0 .. 31. */ > + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", > + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", > + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", > + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", > + > + /* Floating-point registers: 32 .. 63. */ > + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", > + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", > + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", > + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", > + > + /* Altivec registers: 64 .. 95. */ > + "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", > + "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", > + "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", > + "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31", > + > + /* SPE APU GPR upper halves: 96 .. 127. */ > + "rh0", "rh1", "rh2", "rh3", "rh4", "rh5", "rh6", "rh7", > + "rh8", "rh9", "rh10", "rh11", "rh12", "rh13", "rh14", "rh15", > + "rh16", "rh17", "rh18", "rh19", "rh20", "rh21", "rh22", "rh23", > + "rh24", "rh25", "rh26", "rh27", "rh28", "rh29", "rh30", "rh31", > + > + /* SPE APU full 64-bit vector registers: 128 .. 159. */ > + "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7", > + "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15", > + "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23", > + "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31", > + > + /* Segment registers: 160 .. 175. */ > + "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7", > + "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15", > + > + /* Miscellaneous (not special-purpose!) registers: 176 .. 181. */ > + "pc", "ps", "cr", "fpscr", "acc", "vscr" > + }; The old code, which did an under-the-covers call into gdb to map number -> name, was bad and definitly needed to be replaced. The above though could still do with some work - too much on the magic of those numbers in gdb/sim-ppc.h :-( Anyway, lets first get the enum in place. Andrew