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Message-ID: <405A0810.90409@gnu.org>
Date: Fri, 19 Mar 2004 00:10:00 -0000
From: Andrew Cagney <cagney@gnu.org>
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To: Kevin Buettner <kevinb@redhat.com>
Cc: gdb-patches@sources.redhat.com
Subject: Re: [rfa/ppc] prologue parser tweaks
References: <40577FA6.5080506@gnu.org> <20040318091532.63ae9d21@saguaro>
In-Reply-To: <20040318091532.63ae9d21@saguaro>
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>>> +
>>> +      if ((op & 0xfc1fffff) == 0x7c0802a6)
>>> +	{			/* mflr Rx */
>>> +	  /* Since shared library / PIC code, which needs to get its
>>> +	     address at runtime, can appear to save more than one link
>>> +	     register vis:
>>> +
>>> +	     *INDENT-OFF*
>>> +	     stwu r1,-304(r1)
>>> +	     mflr r3
>>> +	     bl 0xff570d0 (blrl)
>>> +	     stw r30,296(r1)
>>> +	     mflr r30
>>> +	     stw r31,300(r1)
>>> +	     stw r3,308(r1);
>>> +	     ...
>>> +	     *INDENT-ON*
>>> +
>>> +	     remember just the first one, but skip over additional
>>> +	     ones.  */
>>> +	  if (lr_reg < 0)
>>> +	    lr_reg = (op & 0x03e00000);
>>> +	  continue;
>>> +	}
>>>  
>>>        if ((op & 0xfc1fffff) == 0x7c0802a6)
>>>  	{			/* mflr Rx */
> 
> 
> The above is okay so long as you remove the old "mflr Rx" test.

I've checked this part in, I'll follow up the other part later.

Andrew


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2004-03-18  Andrew Cagney  <cagney@redhat.com>

	* rs6000-tdep.c (skip_prologue): Record only the first LR save.

Index: rs6000-tdep.c
===================================================================
RCS file: /cvs/src/src/gdb/rs6000-tdep.c,v
retrieving revision 1.184
diff -u -r1.184 rs6000-tdep.c
--- rs6000-tdep.c	15 Mar 2004 21:21:01 -0000	1.184
+++ rs6000-tdep.c	18 Mar 2004 20:14:38 -0000
@@ -551,9 +551,26 @@
 
       if ((op & 0xfc1fffff) == 0x7c0802a6)
 	{			/* mflr Rx */
-	  lr_reg = (op & 0x03e00000);
-	  continue;
+	  /* Since shared library / PIC code, which needs to get its
+	     address at runtime, can appear to save more than one link
+	     register vis:
+
+	     *INDENT-OFF*
+	     stwu r1,-304(r1)
+	     mflr r3
+	     bl 0xff570d0 (blrl)
+	     stw r30,296(r1)
+	     mflr r30
+	     stw r31,300(r1)
+	     stw r3,308(r1);
+	     ...
+	     *INDENT-ON*
 
+	     remember just the first one, but skip over additional
+	     ones.  */
+	  if (lr_reg < 0)
+	    lr_reg = (op & 0x03e00000);
+	  continue;
 	}
       else if ((op & 0xfc1fffff) == 0x7c000026)
 	{			/* mfcr Rx */

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