Re: [RFA] FR-V SIM: Check availability of GR and FR regs

[Dave Brolley <brolley@redhat.com>]

I'm not sure if it's ok to include gdb/sim-frv.h from within the 
simulator code. I thought the interface went the other way around (i.e. 
gdb includes sim/frv-sim.h).

Other than that, it looks ok to me.

Kevin Buettner wrote:

>The patch below adds tests for checking the availability of the GR and
>FR registers in frvbf_fetch_register() and frvbf_store_register().
>
>This patch fixes a gdb segfault that I was seeing when running the
>simulator against a program built with -mcpu=fr400.  The fr400 series
>only has 32 GRs and 32 FRs.  This was causing a segfault during
>simulator initialization that occurred as a result of the "target sim"
>command.
>
>The reason for this segfault was much the same as that for the SPR
>related segfault that you committed a patch for last week - basically,
>if the existence of the register is not checked for ahead of time, the
>simulator attempts to generate an exception for those registers which
>are unavailable.  We don't want to generate an "unavailable register"
>exception (or whatever it's really called) when attempting to
>fetch/store registers from GDB.
>
>I also took the opportunity to revise frvbf_{fetch,store}_register() to
>use the register constants defined in include/gdb/sim-frv.h.
>
>Okay?
>
>	* frv-sim.h (GR_REGNUM_MAX, FR_REGNUM_MAX, PC_REGNUM, SPR_REGNUM_MIN)
>	(SPR_REGNUM_MAX): Delete.
>	* frv.c (gdb/sim-frv.h): Include.
>	(frvbf_fetch_register, frvbf_store_register): Use register number
>	constants from gdb/sim-frv.h.  Check availability of general
>	purpose and float registers.
>
>Index: frv/frv-sim.h
>===================================================================
>RCS file: /cvs/src/src/sim/frv/frv-sim.h,v
>retrieving revision 1.4
>diff -u -p -r1.4 frv-sim.h
>--- frv/frv-sim.h	31 Oct 2003 18:23:47 -0000	1.4
>+++ frv/frv-sim.h	7 Nov 2003 06:08:39 -0000
>@@ -29,13 +29,6 @@ with this program; if not, write to the 
> #define H_SPR_ACCG4  1476
> #define H_SPR_ACCG63 1535
> 
>-/* gdb register numbers.  */
>-#define GR_REGNUM_MAX	63
>-#define FR_REGNUM_MAX  127
>-#define PC_REGNUM      128
>-#define SPR_REGNUM_MIN 129
>-#define SPR_REGNUM_MAX (SPR_REGNUM_MIN + 4096 - 1)
>-
> /* Initialization of the frv cpu.  */
> void frv_initialize (SIM_CPU *, SIM_DESC);
> void frv_term (SIM_DESC);
>Index: frv/frv.c
>===================================================================
>RCS file: /cvs/src/src/sim/frv/frv.c,v
>retrieving revision 1.4
>diff -u -p -r1.4 frv.c
>--- frv/frv.c	31 Oct 2003 18:23:47 -0000	1.4
>+++ frv/frv.c	7 Nov 2003 06:08:39 -0000
>@@ -27,6 +27,7 @@ with this program; if not, write to the 
> #include "cgen-engine.h"
> #include "cgen-par.h"
> #include "bfd.h"
>+#include "gdb/sim-frv.h"
> #include <math.h>
> 
> /* Maintain a flag in order to know when to write the address of the next
>@@ -38,17 +39,37 @@ int frvbf_write_next_vliw_addr_to_LR;
> int
> frvbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
> {
>-  if (rn <= GR_REGNUM_MAX)
>-    SETTSI (buf, GET_H_GR (rn));
>-  else if (rn <= FR_REGNUM_MAX)
>-    SETTSI (buf, GET_H_FR (rn - GR_REGNUM_MAX - 1));
>-  else if (rn == PC_REGNUM)
>+  if (SIM_FRV_GR0_REGNUM <= rn && rn <= SIM_FRV_GR63_REGNUM)
>+    {
>+      int hi_available, lo_available;
>+      int grn = rn - SIM_FRV_GR0_REGNUM;
>+
>+      frv_gr_registers_available (current_cpu, &hi_available, &lo_available);
>+
>+      if ((grn < 32 && !lo_available) || (grn >= 32 && !hi_available))
>+	return 0;
>+      else
>+	SETTSI (buf, GET_H_GR (grn));
>+    }
>+  else if (SIM_FRV_FR0_REGNUM <= rn && rn <= SIM_FRV_FR63_REGNUM)
>+    {
>+      int hi_available, lo_available;
>+      int frn = rn - SIM_FRV_FR0_REGNUM;
>+
>+      frv_fr_registers_available (current_cpu, &hi_available, &lo_available);
>+
>+      if ((frn < 32 && !lo_available) || (frn >= 32 && !hi_available))
>+	return 0;
>+      else
>+	SETTSI (buf, GET_H_FR (frn));
>+    }
>+  else if (rn == SIM_FRV_PC_REGNUM)
>     SETTSI (buf, GET_H_PC ());
>-  else if (rn >= SPR_REGNUM_MIN && rn <= SPR_REGNUM_MAX)
>+  else if (SIM_FRV_SPR0_REGNUM <= rn && rn <= SIM_FRV_SPR4095_REGNUM)
>     {
>       /* Make sure the register is implemented.  */
>       FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu);
>-      int spr = rn - SPR_REGNUM_MIN;
>+      int spr = rn - SIM_FRV_SPR0_REGNUM;
>       if (! control->spr[spr].implemented)
> 	return 0;
>       SETTSI (buf, GET_H_SPR (spr));
>@@ -67,17 +88,37 @@ frvbf_fetch_register (SIM_CPU *current_c
> int
> frvbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
> {
>-  if (rn <= GR_REGNUM_MAX)
>-    SET_H_GR (rn, GETTSI (buf));
>-  else if (rn <= FR_REGNUM_MAX)
>-    SET_H_FR (rn - GR_REGNUM_MAX - 1, GETTSI (buf));
>-  else if (rn == PC_REGNUM)
>+  if (SIM_FRV_GR0_REGNUM <= rn && rn <= SIM_FRV_GR63_REGNUM)
>+    {
>+      int hi_available, lo_available;
>+      int grn = rn - SIM_FRV_GR0_REGNUM;
>+
>+      frv_gr_registers_available (current_cpu, &hi_available, &lo_available);
>+
>+      if ((grn < 32 && !lo_available) || (grn >= 32 && !hi_available))
>+	return 0;
>+      else
>+	SET_H_GR (grn, GETTSI (buf));
>+    }
>+  else if (SIM_FRV_FR0_REGNUM <= rn && rn <= SIM_FRV_FR63_REGNUM)
>+    {
>+      int hi_available, lo_available;
>+      int frn = rn - SIM_FRV_FR0_REGNUM;
>+
>+      frv_fr_registers_available (current_cpu, &hi_available, &lo_available);
>+
>+      if ((frn < 32 && !lo_available) || (frn >= 32 && !hi_available))
>+	return 0;
>+      else
>+	SET_H_FR (frn, GETTSI (buf));
>+    }
>+  else if (rn == SIM_FRV_PC_REGNUM)
>     SET_H_PC (GETTSI (buf));
>-  else if (rn >= SPR_REGNUM_MIN && rn <= SPR_REGNUM_MAX)
>+  else if (SIM_FRV_SPR0_REGNUM <= rn && rn <= SIM_FRV_SPR4095_REGNUM)
>     {
>       /* Make sure the register is implemented.  */
>       FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu);
>-      int spr = rn - SPR_REGNUM_MIN;
>+      int spr = rn - SIM_FRV_SPR0_REGNUM;
>       if (! control->spr[spr].implemented)
> 	return 0;
>       SET_H_SPR (spr, GETTSI (buf));
>  
>