From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 27920 invoked by alias); 31 Oct 2003 18:28:30 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 27913 invoked from network); 31 Oct 2003 18:28:29 -0000 Received: from unknown (HELO touchme.toronto.redhat.com) (207.219.125.105) by sources.redhat.com with SMTP; 31 Oct 2003 18:28:29 -0000 Received: from redhat.com (vpn50-50.rdu.redhat.com [172.16.50.50]) by touchme.toronto.redhat.com (Postfix) with ESMTP id 23E6E800046; Fri, 31 Oct 2003 13:28:27 -0500 (EST) Message-ID: <3FA2A9C0.1000105@redhat.com> Date: Fri, 31 Oct 2003 18:28:00 -0000 From: Dave Brolley User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:1.4) Gecko/20030624 Netscape/7.1 (ax) X-Accept-Language: en-us, en MIME-Version: 1.0 To: Kevin Buettner Cc: gdb-patches@sources.redhat.com Subject: Re: [PATCH] FR-V: Improve handling of SPR registers References: <1031031004254.ZM30431@localhost.localdomain> In-Reply-To: <1031031004254.ZM30431@localhost.localdomain> Content-Type: multipart/mixed; boundary="------------050108090801070500050206" X-SW-Source: 2003-10/txt/msg00880.txt.bz2 This is a multi-part message in MIME format. --------------050108090801070500050206 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Content-length: 1251 This is the patch to which Kevin refers below. I've committed it. Dave Kevin Buettner wrote: >The patch below depends on some work that Dave Brolley has done on the >simulator. I'll commit the change below after Dave commits his patch. > >I'll eventually provide a pseudo-register for obtaining access iacc0 >as a unit (instead of separate upper and lower halves). But, before >that happens, I have some more de-deprecation to do first. > >Of all the SPRs the FR-V has, the simulator had only implemented >support for fetching / setting the link register. Dave's patch will >provide GDB with the ability to access all of them, making it very >easy to add support for other SPRs from GDB. The patch below (in >conjunction with Dave's patch) will enable support for all of the >SPRs presently known to GDB (including iacc0). > >I had considered (attempting) to provide support for all known FR-V >SPRs from GDB, but there were a number of drawbacks with doing this: >1) The g/G packet would get very large. 2) There are a lot of "holes" >in the register set do to reserved registers, unimplemented registers, >and the like. 3) I don't think it makes sense for all of the remaining >registers to be fetched/set via g/G packets. > >Kevin > > > --------------050108090801070500050206 Content-Type: text/plain; name="sim-spr.ChangeLog" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="sim-spr.ChangeLog" Content-length: 446 2003-10-31 Dave Brolley * frv-sim.h (REGNUM_LR): Removed. (SPR_REGNUM_MIN,SPR_REGNUM_MAX): New macros. * frv.c (frvbf_fetch_register): Fetch SPR registers based on SPR_REGNUM_MIN and SPR_REGNUM_MAX. Check whether SPRs are implemented. Return 0 for an unimplemented register. Return the length of the data for an implemented register. (frvbf_store_register): Ditto. --------------050108090801070500050206 Content-Type: text/plain; name="sim-spr.patch.txt" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="sim-spr.patch.txt" Content-length: 3029 Index: sim/frv/frv-sim.h =================================================================== RCS file: /cvs/src/src/sim/frv/frv-sim.h,v retrieving revision 1.3 diff -c -p -r1.3 frv-sim.h *** sim/frv/frv-sim.h 8 Oct 2003 18:19:32 -0000 1.3 --- sim/frv/frv-sim.h 31 Oct 2003 18:18:42 -0000 *************** with this program; if not, write to the *** 33,39 **** #define GR_REGNUM_MAX 63 #define FR_REGNUM_MAX 127 #define PC_REGNUM 128 ! #define LR_REGNUM 145 /* Initialization of the frv cpu. */ void frv_initialize (SIM_CPU *, SIM_DESC); --- 33,40 ---- #define GR_REGNUM_MAX 63 #define FR_REGNUM_MAX 127 #define PC_REGNUM 128 ! #define SPR_REGNUM_MIN 129 ! #define SPR_REGNUM_MAX (SPR_REGNUM_MIN + 4096 - 1) /* Initialization of the frv cpu. */ void frv_initialize (SIM_CPU *, SIM_DESC); Index: sim/frv/frv.c =================================================================== RCS file: /cvs/src/src/sim/frv/frv.c,v retrieving revision 1.3 diff -c -p -r1.3 frv.c *** sim/frv/frv.c 8 Oct 2003 18:19:32 -0000 1.3 --- sim/frv/frv.c 31 Oct 2003 18:18:43 -0000 *************** frvbf_fetch_register (SIM_CPU *current_c *** 44,55 **** SETTSI (buf, GET_H_FR (rn - GR_REGNUM_MAX - 1)); else if (rn == PC_REGNUM) SETTSI (buf, GET_H_PC ()); ! else if (rn == LR_REGNUM) ! SETTSI (buf, GET_H_SPR (H_SPR_LR)); else ! SETTSI (buf, 0xdeadbeef); ! return -1; } /* The contents of BUF are in target byte order. */ --- 44,65 ---- SETTSI (buf, GET_H_FR (rn - GR_REGNUM_MAX - 1)); else if (rn == PC_REGNUM) SETTSI (buf, GET_H_PC ()); ! else if (rn >= SPR_REGNUM_MIN && rn <= SPR_REGNUM_MAX) ! { ! /* Make sure the register is implemented. */ ! FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu); ! int spr = rn - SPR_REGNUM_MIN; ! if (! control->spr[spr].implemented) ! return 0; ! SETTSI (buf, GET_H_SPR (spr)); ! } else ! { ! SETTSI (buf, 0xdeadbeef); ! return 0; ! } ! return len; } /* The contents of BUF are in target byte order. */ *************** frvbf_store_register (SIM_CPU *current_c *** 63,72 **** SET_H_FR (rn - GR_REGNUM_MAX - 1, GETTSI (buf)); else if (rn == PC_REGNUM) SET_H_PC (GETTSI (buf)); ! else if (rn == LR_REGNUM) ! SET_H_SPR (H_SPR_LR, GETTSI (buf)); ! return -1; } /* Cover fns to access the general registers. */ --- 73,91 ---- SET_H_FR (rn - GR_REGNUM_MAX - 1, GETTSI (buf)); else if (rn == PC_REGNUM) SET_H_PC (GETTSI (buf)); ! else if (rn >= SPR_REGNUM_MIN && rn <= SPR_REGNUM_MAX) ! { ! /* Make sure the register is implemented. */ ! FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu); ! int spr = rn - SPR_REGNUM_MIN; ! if (! control->spr[spr].implemented) ! return 0; ! SET_H_SPR (spr, GETTSI (buf)); ! } ! else ! return 0; ! return len; } /* Cover fns to access the general registers. */ --------------050108090801070500050206--