Index: sim/frv/frv-sim.h
===================================================================
RCS file: /cvs/src/src/sim/frv/frv-sim.h,v
retrieving revision 1.3
diff -c -p -r1.3 frv-sim.h
*** sim/frv/frv-sim.h	8 Oct 2003 18:19:32 -0000	1.3
--- sim/frv/frv-sim.h	31 Oct 2003 18:18:42 -0000
*************** with this program; if not, write to the 
*** 33,39 ****
  #define GR_REGNUM_MAX	63
  #define FR_REGNUM_MAX  127
  #define PC_REGNUM      128
! #define LR_REGNUM      145
  
  /* Initialization of the frv cpu.  */
  void frv_initialize (SIM_CPU *, SIM_DESC);
--- 33,40 ----
  #define GR_REGNUM_MAX	63
  #define FR_REGNUM_MAX  127
  #define PC_REGNUM      128
! #define SPR_REGNUM_MIN 129
! #define SPR_REGNUM_MAX (SPR_REGNUM_MIN + 4096 - 1)
  
  /* Initialization of the frv cpu.  */
  void frv_initialize (SIM_CPU *, SIM_DESC);
Index: sim/frv/frv.c
===================================================================
RCS file: /cvs/src/src/sim/frv/frv.c,v
retrieving revision 1.3
diff -c -p -r1.3 frv.c
*** sim/frv/frv.c	8 Oct 2003 18:19:32 -0000	1.3
--- sim/frv/frv.c	31 Oct 2003 18:18:43 -0000
*************** frvbf_fetch_register (SIM_CPU *current_c
*** 44,55 ****
      SETTSI (buf, GET_H_FR (rn - GR_REGNUM_MAX - 1));
    else if (rn == PC_REGNUM)
      SETTSI (buf, GET_H_PC ());
!   else if (rn == LR_REGNUM)
!     SETTSI (buf, GET_H_SPR (H_SPR_LR));
    else
!     SETTSI (buf, 0xdeadbeef);
  
!   return -1;
  }
  
  /* The contents of BUF are in target byte order.  */
--- 44,65 ----
      SETTSI (buf, GET_H_FR (rn - GR_REGNUM_MAX - 1));
    else if (rn == PC_REGNUM)
      SETTSI (buf, GET_H_PC ());
!   else if (rn >= SPR_REGNUM_MIN && rn <= SPR_REGNUM_MAX)
!     {
!       /* Make sure the register is implemented.  */
!       FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu);
!       int spr = rn - SPR_REGNUM_MIN;
!       if (! control->spr[spr].implemented)
! 	return 0;
!       SETTSI (buf, GET_H_SPR (spr));
!     }
    else
!     {
!       SETTSI (buf, 0xdeadbeef);
!       return 0;
!     }
  
!   return len;
  }
  
  /* The contents of BUF are in target byte order.  */
*************** frvbf_store_register (SIM_CPU *current_c
*** 63,72 ****
      SET_H_FR (rn - GR_REGNUM_MAX - 1, GETTSI (buf));
    else if (rn == PC_REGNUM)
      SET_H_PC (GETTSI (buf));
!   else if (rn == LR_REGNUM)
!     SET_H_SPR (H_SPR_LR, GETTSI (buf));
  
!   return -1;
  }
  
  /* Cover fns to access the general registers.  */
--- 73,91 ----
      SET_H_FR (rn - GR_REGNUM_MAX - 1, GETTSI (buf));
    else if (rn == PC_REGNUM)
      SET_H_PC (GETTSI (buf));
!   else if (rn >= SPR_REGNUM_MIN && rn <= SPR_REGNUM_MAX)
!     {
!       /* Make sure the register is implemented.  */
!       FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu);
!       int spr = rn - SPR_REGNUM_MIN;
!       if (! control->spr[spr].implemented)
! 	return 0;
!       SET_H_SPR (spr, GETTSI (buf));
!     }
!   else
!     return 0;
  
!   return len;
  }
  
  /* Cover fns to access the general registers.  */