From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 13480 invoked by alias); 17 Jun 2003 14:27:17 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 13473 invoked from network); 17 Jun 2003 14:27:16 -0000 Received: from unknown (HELO localhost.redhat.com) (207.219.125.131) by sources.redhat.com with SMTP; 17 Jun 2003 14:27:16 -0000 Received: from redhat.com (localhost [127.0.0.1]) by localhost.redhat.com (Postfix) with ESMTP id 1E0842B5F; Tue, 17 Jun 2003 10:27:10 -0400 (EDT) Message-ID: <3EEF253D.9060502@redhat.com> Date: Tue, 17 Jun 2003 14:27:00 -0000 From: Andrew Cagney User-Agent: Mozilla/5.0 (X11; U; NetBSD macppc; en-US; rv:1.0.2) Gecko/20030223 X-Accept-Language: en-us, en MIME-Version: 1.0 To: cgd@broadcom.com Cc: Kevin Buettner , gdb-patches@sources.redhat.com Subject: Re: [WIP/RFC] MIPS registers overhaul References: <1030510002453.ZM3880@localhost.localdomain> <3EBD6131.30209@redhat.com> <1030514220025.ZM10373@localhost.localdomain> <3EC461C1.1080104@redhat.com> <3ECA8EC6.6030405@redhat.com> <3EECAB89.10609@redhat.com> <3EEE2B85.6030207@redhat.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2003-06/txt/msg00557.txt.bz2 > Careful. If the ABI is o32, and FR == 0/..., then there should be >> only 16 floating point registers in use. The original MIPS 1, and >> r5900 ABIs would both allow use of all 32 32 bit floating point >> registers. > > > I don't know that that is correct, at least about the "original MIPS > 1" behaviour. Sigh, yes: B 3.3 Formatted Operand Layout of [3.2]: FPU instructions that operate on formatted operand values specify the floating-point register (FPR) that holds a value. An FPR is not necessarily the same as a CP1 general register because an FPR is 64 bits wide; if this is wider than the CP1 general registers, an aligned set of adjacent CP1 general registers is used as the FPR. The 32-bit register model provides 16 FPRs specified by the even CP1 general register numbers. The 64-bit register model provides 32 FPRs, one per CP1 general register. Operands that are only 32 bits wide (W and S formats), use only half the space in an FPR. The FPR organization and the way that operand data is stored in them is shown in the following figures. A summary of the data transfer instructions can be found in section B 6.1 on page B-19. The key bit being that the terminology differentaties between a 32 bit CP1 register and a 64 bit FPR. This also suggests a better way of representing the registers to the user: MIPS I: $cp0, $cp1, ...: 32/64 bit raw co-processor registers MIPS I: $fp0, $fp2, ...: 64 bit co-processor registers note that these are little word ordered and contain 32 and 64 bit float values (This was suggested to me in a second hand off line discussion :-() MIPS III: $fp0, $fp1, ...: 64 bit floating point registers Andrew