From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 24264 invoked by alias); 17 Jul 2002 19:37:17 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 24256 invoked from network); 17 Jul 2002 19:37:14 -0000 Received: from unknown (HELO ns2.uk.superh.com) (193.128.105.170) by sources.redhat.com with SMTP; 17 Jul 2002 19:37:14 -0000 Received: from sh-uk-ex01.uk.w2k.superh.com (sh-uk-ex01 [192.168.16.17]) by ns2.uk.superh.com (8.11.6+Sun/8.11.6) with ESMTP id g6HJUVK28645; Wed, 17 Jul 2002 20:30:31 +0100 (BST) Received: from superh.com ([192.168.17.40]) by sh-uk-ex01.uk.w2k.superh.com with Microsoft SMTPSVC(5.0.2195.4905); Wed, 17 Jul 2002 20:36:21 +0100 Message-ID: <3D35C737.9F25B58F@superh.com> Date: Wed, 17 Jul 2002 12:50:00 -0000 From: Joern Rennecke Organization: SuperH UK Ltd. X-Accept-Language: en MIME-Version: 1.0 To: gdb-patches@sources.redhat.com CC: Elena Zannoni , Andrew Cagney Subject: sh64 simulator register numbers Content-Type: multipart/mixed; boundary="------------47880FC9300460DA4526DD09" X-OriginalArrivalTime: 17 Jul 2002 19:36:21.0764 (UTC) FILETIME=[3AC7BC40:01C22DC9] X-SW-Source: 2002-07/txt/msg00369.txt.bz2 This is a multi-part message in MIME format. --------------47880FC9300460DA4526DD09 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Content-length: 449 AFAICS the sh64 simulator doesn't need any changes for this renumbering, while gdb would need some decoupling from the simulator's register numbers. Should we create a header file that describes the register numbers when talking to hardware, and make gdb use that for its internal numbers? Or should it define the numbers inside sh-tdep.c ? -- -------------------------- SuperH 2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ T:+44 1454 462330 --------------47880FC9300460DA4526DD09 Content-Type: text/plain; charset=us-ascii; name="sh64-sim-regnos" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="sh64-sim-regnos" Content-length: 3281 Index: sim-sh.h =================================================================== RCS file: /cvs/src/src/include/gdb/sim-sh.h,v retrieving revision 1.2 diff -p -r1.2 sim-sh.h *** sim-sh.h 17 Jul 2002 18:43:26 -0000 1.2 --- sim-sh.h 17 Jul 2002 19:26:54 -0000 *************** enum *** 131,154 **** SIM_SH_R6_BANK_REGNUM, SIM_SH_R7_BANK_REGNUM /* 100..127: room for expansion. */ - }; ! enum ! { ! SIM_SH64_R0_REGNUM = 0, ! SIM_SH64_SP_REGNUM = 15, ! SIM_SH64_PC_REGNUM = 64, ! SIM_SH64_SR_REGNUM = 65, ! SIM_SH64_SSR_REGNUM = 66, ! SIM_SH64_SPC_REGNUM = 67, ! SIM_SH64_TR0_REGNUM = 68, ! SIM_SH64_FPCSR_REGNUM = 76, ! SIM_SH64_FR0_REGNUM = 77 }; enum { ! SIM_SH64_NR_REGS = 141, /* total number of architectural registers */ SIM_SH64_NR_R_REGS = 64, /* number of general registers */ SIM_SH64_NR_TR_REGS = 8, /* number of target registers */ SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */ --- 131,174 ---- SIM_SH_R6_BANK_REGNUM, SIM_SH_R7_BANK_REGNUM /* 100..127: room for expansion. */ ! /* SHmedia */ ! SIM_SH64_R0_REGNUM = 128, ! SIM_SH64_SP_REGNUM = SIM_SH64_R0_REGNUM+15, ! SIM_SH64_PC_REGNUM = SIM_SH64_R0_REGNUM+64, ! /* 64 64-bit control registers */ ! SIM_SH64_CR0_REGNUM = SIM_SH64_R0_REGNUM+65, ! /* Some of these have specific names. */ ! SIM_SH64_SR_REGNUM = SIM_SH64_CR0_REGNUM, /* Status reg */ ! SIM_SH64_SSR_REGNUM = SIM_SH64_CR0_REGNUM+1, /* Saved status reg */ ! SIM_SH64_PSSR_REGNUM = SIM_SH64_CR0_REGNUM+2, /* Panic-saved status reg*/ ! SIM_SH64_INTEVT_REGNUM=SIM_SH64_CR0_REGNUM+4, /* Interrupt event reg */ ! SIM_SH64_EXPEVT_REGNUM=SIM_SH64_CR0_REGNUM+5, /* Exception event reg */ ! SIM_SH64_PEXPEVT_REGNUM= SIM_SH64_CR0_REGNUM+6,/* Panic-saved Exception ! event reg */ ! SIM_SH64_TRA_REGNUM = SIM_SH64_CR0_REGNUM+7, /* TRAP exception reg */ ! SIM_SH64_SPC_REGNUM = SIM_SH64_CR0_REGNUM+8, /* Saved program counter */ ! SIM_SH64_PSPC_REGNUM = SIM_SH64_CR0_REGNUM+9, /* Panic-saved program ! counter */ ! SIM_SH64_RESVEC_REGNUM=SIM_SH64_CR0_REGNUM+10, /* Reset vector */ ! SIM_SH64_VBR_REGNUM = SIM_SH64_CR0_REGNUM+11, /* Vector base register */ ! SIM_SH64_TEA_REGNUM = SIM_SH64_CR0_REGNUM+13, /* Faulting effective ! address register */ ! SIM_SH64_DCR_REGNUM = SIM_SH64_CR0_REGNUM+16, /* Debug control reg */ ! SIM_SH64_KCR0_REGNUM = SIM_SH64_CR0_REGNUM+17, /* Kernel register 0 */ ! SIM_SH64_KCR1_REGNUM = SIM_SH64_CR0_REGNUM+18, /* Kernel register 1 */ ! SIM_SH64_CTC_REGNUM = SIM_SH64_CR0_REGNUM+62, /* Clock tick counter */ ! SIM_SH64_USR_REGNUM = SIM_SH64_CR0_REGNUM+63, /* User-accessible ! status register */ ! SIM_SH64_CR63_REGNUM = SIM_SH64_R0_REGNUM+128, ! SIM_SH64_TR0_REGNUM = SIM_SH64_R0_REGNUM+129, ! SIM_SH64_FPSCR_REGNUM= SIM_SH64_R0_REGNUM+137, ! SIM_SH64_FR0_REGNUM = SIM_SH64_R0_REGNUM+138 }; enum { ! SIM_SH64_NR_REGS = 202, /* total number of architectural registers */ SIM_SH64_NR_R_REGS = 64, /* number of general registers */ SIM_SH64_NR_TR_REGS = 8, /* number of target registers */ SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */ --------------47880FC9300460DA4526DD09--