From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 24209 invoked by alias); 3 Jul 2002 20:37:03 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 24152 invoked from network); 3 Jul 2002 20:37:00 -0000 Received: from unknown (HELO uk.superh.com) (193.128.105.170) by sources.redhat.com with SMTP; 3 Jul 2002 20:37:00 -0000 Received: from sh-uk-ex01.uk.w2k.superh.com (sh-uk-ex01 [192.168.16.17]) by uk.superh.com (8.11.6+Sun/8.11.6) with ESMTP id g63KUv520106; Wed, 3 Jul 2002 21:30:57 +0100 (BST) Received: from superh.com ([192.168.17.40]) by sh-uk-ex01.uk.w2k.superh.com with Microsoft SMTPSVC(5.0.2195.4905); Wed, 3 Jul 2002 21:36:04 +0100 Message-ID: <3D236046.4FAE0419@superh.com> Date: Wed, 03 Jul 2002 13:49:00 -0000 From: Joern Rennecke Organization: SuperH UK Ltd. X-Accept-Language: en MIME-Version: 1.0 To: Elena Zannoni CC: gdb-patches@sources.redhat.com Subject: Re: Unreviewed patches References: <3D205F19.1B99290F@superh.com> <15648.31077.572892.886182@localhost.redhat.com> <3D208CF1.AB7AC45A@superh.com> <15648.51312.63195.689336@localhost.redhat.com> <3D20D12F.6AB9E865@superh.com> <15649.65211.660582.965251@localhost.redhat.com> Content-Type: multipart/mixed; boundary="------------FFAD0C322ACEF3AC862A6EF9" X-OriginalArrivalTime: 03 Jul 2002 20:36:04.0999 (UTC) FILETIME=[40C58170:01C222D1] X-SW-Source: 2002-07/txt/msg00066.txt.bz2 This is a multi-part message in MIME format. --------------FFAD0C322ACEF3AC862A6EF9 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Content-length: 1012 Elena Zannoni wrote: > Hmm, I don't think we ever worried about that. We have broken > compatibility even between gcc and gdb, sometimes. And here the chance > is smaller, given that sim and gdb come from the same repo and are > built and linked together. All right, I have appended a patch that uses separate numbers for the sh-dsp registers. I've left the other numbers unchanged. regression tested on i686-px-linux-gnu X sh-elf; the tally before and after the patch is the same: # of expected passes 6681 # of unexpected failures 322 # of expected failures 60 # of unresolved testcases 29 # of unsupported tests 7 > Oh, yes, I see them. I guess they don't reply with 'accepted' in the > cgen world. Actually, he did reply, but it was a personal email. > But I cannot approve changes to the sh64 sim. So is the sh64 gdb currently without a maintainer? -- -------------------------- SuperH 2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ T:+44 1454 462330 --------------FFAD0C322ACEF3AC862A6EF9 Content-Type: text/plain; charset=us-ascii; name="sim-sh-patch-2" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="sim-sh-patch-2" Content-length: 21254 Wed Jul 3 21:33:14 2002 J"orn Rennecke include/gdb: * sim-sh.h: Add enum constants for sh[1-4], sh3e, sh3?-dsp, renumbering the sh-dsp registers to use distinct numbers. sim/sh: * Makefile (interp.o): Depend on $(srcroot)/include/gdb/sim-sh.h. * interp.c: Include "gdb/sim-sh.h". (sim_store_register, sim_fetch_register): Use constants defined there. gdb: * sh-tydep.c (sh_dsp_register_sim_regno): New function. (sh_gdbarch_init): Use it for sh-dsp. Index: include/gdb/sim-sh.h =================================================================== RCS file: /cvs/src/src/include/gdb/sim-sh.h,v retrieving revision 1.1 diff -p -r1.1 sim-sh.h *** include/gdb/sim-sh.h 10 May 2002 22:53:56 -0000 1.1 --- include/gdb/sim-sh.h 3 Jul 2002 19:46:29 -0000 *************** *** 1,5 **** /* This file defines the interface between the sh simulator and gdb. ! Copyright (C) 2002 Free Software Foundation, Inc. This file is part of GDB. --- 1,5 ---- /* This file defines the interface between the sh simulator and gdb. ! Copyright (C) 2000, 2002 Free Software Foundation, Inc. This file is part of GDB. *************** extern "C" { // } *** 27,51 **** /* The simulator makes use of the following register information. */ enum ! { ! SIM_SH64_R0_REGNUM = 0, ! SIM_SH64_SP_REGNUM = 15, ! SIM_SH64_PC_REGNUM = 64, ! SIM_SH64_SR_REGNUM = 65, ! SIM_SH64_SSR_REGNUM = 66, ! SIM_SH64_SPC_REGNUM = 67, ! SIM_SH64_TR0_REGNUM = 68, ! SIM_SH64_FPCSR_REGNUM = 76, ! SIM_SH64_FR0_REGNUM = 77 ! }; enum ! { ! SIM_SH64_NR_REGS = 141, /* total number of architectural registers */ ! SIM_SH64_NR_R_REGS = 64, /* number of general registers */ ! SIM_SH64_NR_TR_REGS = 8, /* number of target registers */ ! SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */ ! }; #ifdef __cplusplus } --- 27,158 ---- /* The simulator makes use of the following register information. */ enum ! { ! SIM_SH_R0_REGNUM = 0, ! SIM_SH_R1_REGNUM, ! SIM_SH_R2_REGNUM, ! SIM_SH_R3_REGNUM, ! SIM_SH_R4_REGNUM, ! SIM_SH_R5_REGNUM, ! SIM_SH_R6_REGNUM, ! SIM_SH_R7_REGNUM, ! SIM_SH_R8_REGNUM, ! SIM_SH_R9_REGNUM, ! SIM_SH_R10_REGNUM, ! SIM_SH_R11_REGNUM, ! SIM_SH_R12_REGNUM, ! SIM_SH_R13_REGNUM, ! SIM_SH_R14_REGNUM, ! SIM_SH_R15_REGNUM, ! SIM_SH_PC_REGNUM, ! SIM_SH_PR_REGNUM, ! SIM_SH_GBR_REGNUM, ! SIM_SH_VBR_REGNUM, ! SIM_SH_MACH_REGNUM, ! SIM_SH_MACL_REGNUM, ! SIM_SH_SR_REGNUM, ! SIM_SH_FPUL_REGNUM, ! SIM_SH_FPSCR_REGNUM, ! SIM_SH_FR0_REGNUM, /* FRn registers: sh3e / sh4 */ ! SIM_SH_FR1_REGNUM, ! SIM_SH_FR2_REGNUM, ! SIM_SH_FR3_REGNUM, ! SIM_SH_FR4_REGNUM, ! SIM_SH_FR5_REGNUM, ! SIM_SH_FR6_REGNUM, ! SIM_SH_FR7_REGNUM, ! SIM_SH_FR8_REGNUM, ! SIM_SH_FR9_REGNUM, ! SIM_SH_FR10_REGNUM, ! SIM_SH_FR11_REGNUM, ! SIM_SH_FR12_REGNUM, ! SIM_SH_FR13_REGNUM, ! SIM_SH_FR14_REGNUM, ! SIM_SH_FR15_REGNUM, ! SIM_SH_SSR_REGNUM, /* sh3{,e,-dsp}, sh4 */ ! SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */ ! SIM_SH_R0_BANK0_REGNUM, /* SIM_SH_Rn_BANKm_REGNUM: sh3[e] / sh4 */ ! SIM_SH_R1_BANK0_REGNUM, ! SIM_SH_R2_BANK0_REGNUM, ! SIM_SH_R3_BANK0_REGNUM, ! SIM_SH_R4_BANK0_REGNUM, ! SIM_SH_R5_BANK0_REGNUM, ! SIM_SH_R6_BANK0_REGNUM, ! SIM_SH_R7_BANK0_REGNUM, ! SIM_SH_R0_BANK1_REGNUM, ! SIM_SH_R1_BANK1_REGNUM, ! SIM_SH_R2_BANK1_REGNUM, ! SIM_SH_R3_BANK1_REGNUM, ! SIM_SH_R4_BANK1_REGNUM, ! SIM_SH_R5_BANK1_REGNUM, ! SIM_SH_R6_BANK1_REGNUM, ! SIM_SH_R7_BANK1_REGNUM, ! SIM_SH_XF0_REGNUM, ! SIM_SH_XF1_REGNUM, ! SIM_SH_XF2_REGNUM, ! SIM_SH_XF3_REGNUM, ! SIM_SH_XF4_REGNUM, ! SIM_SH_XF5_REGNUM, ! SIM_SH_XF6_REGNUM, ! SIM_SH_XF7_REGNUM, ! SIM_SH_XF8_REGNUM, ! SIM_SH_XF9_REGNUM, ! SIM_SH_XF10_REGNUM, ! SIM_SH_XF11_REGNUM, ! SIM_SH_XF12_REGNUM, ! SIM_SH_XF13_REGNUM, ! SIM_SH_XF14_REGNUM, ! SIM_SH_XF15_REGNUM, ! SIM_SH_SGR_REGNUM, ! SIM_SH_DBR_REGNUM, ! SIM_SH4_NUM_REGS, /* 77 */ ! ! /* sh[3]-dsp */ ! SIM_SH_DSR_REGNUM, ! SIM_SH_A0G_REGNUM, ! SIM_SH_A0_REGNUM, ! SIM_SH_A1G_REGNUM, ! SIM_SH_A1_REGNUM, ! SIM_SH_M0_REGNUM, ! SIM_SH_M1_REGNUM, ! SIM_SH_X0_REGNUM, ! SIM_SH_X1_REGNUM, ! SIM_SH_Y0_REGNUM, ! SIM_SH_Y1_REGNUM, ! SIM_SH_MOD_REGNUM, ! SIM_SH_RS_REGNUM, ! SIM_SH_RE_REGNUM, ! SIM_SH_R0_BANK_REGNUM, ! SIM_SH_R1_BANK_REGNUM, ! SIM_SH_R2_BANK_REGNUM, ! SIM_SH_R3_BANK_REGNUM, ! SIM_SH_R4_BANK_REGNUM, ! SIM_SH_R5_BANK_REGNUM, ! SIM_SH_R6_BANK_REGNUM, ! SIM_SH_R7_BANK_REGNUM ! /* 100..127: room for expansion. */ ! }; enum ! { ! SIM_SH64_R0_REGNUM = 0, ! SIM_SH64_SP_REGNUM = 15, ! SIM_SH64_PC_REGNUM = 64, ! SIM_SH64_SR_REGNUM = 65, ! SIM_SH64_SSR_REGNUM = 66, ! SIM_SH64_SPC_REGNUM = 67, ! SIM_SH64_TR0_REGNUM = 68, ! SIM_SH64_FPCSR_REGNUM = 76, ! SIM_SH64_FR0_REGNUM = 77 ! }; ! ! enum ! { ! SIM_SH64_NR_REGS = 141, /* total number of architectural registers */ ! SIM_SH64_NR_R_REGS = 64, /* number of general registers */ ! SIM_SH64_NR_TR_REGS = 8, /* number of target registers */ ! SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */ ! }; #ifdef __cplusplus } Index: sim/sh/interp.c =================================================================== RCS file: /cvs/src/src/sim/sh/interp.c,v retrieving revision 1.6 diff -p -r1.6 interp.c *** sim/sh/interp.c 18 Jun 2002 15:54:44 -0000 1.6 --- sim/sh/interp.c 3 Jul 2002 19:46:29 -0000 *************** *** 29,34 **** --- 29,35 ---- #include "bfd.h" #include "gdb/callback.h" #include "gdb/remote-sim.h" + #include "gdb/sim-sh.h" /* This file is local - if newlib changes, then so should this. */ #include "syscall.h" *************** sim_store_register (sd, rn, memory, leng *** 1790,1887 **** val = swap (* (int *)memory); switch (rn) { ! case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: ! case 8: case 9: case 10: case 11: case 12: case 13: case 14: case 15: saved_state.asregs.regs[rn] = val; break; ! case 16: saved_state.asregs.pc = val; break; ! case 17: PR = val; break; ! case 18: GBR = val; break; ! case 19: VBR = val; break; ! case 20: MACH = val; break; ! case 21: MACL = val; break; ! case 22: SET_SR (val); break; ! case 23: FPUL = val; break; ! case 24: SET_FPSCR (val); break; ! case 25: ! if (target_dsp) ! A0G = val; ! else case 26: ! if (target_dsp) ! A0 = val; ! else case 27: ! if (target_dsp) ! A1G = val; ! else case 28: ! if (target_dsp) ! A1 = val; ! else case 29: ! if (target_dsp) ! M0 = val; ! else case 30: ! if (target_dsp) ! M1 = val; ! else case 31: ! if (target_dsp) ! X0 = val; ! else case 32: ! if (target_dsp) ! X1 = val; ! else case 33: ! if (target_dsp) ! Y0 = val; ! else case 34: ! if (target_dsp) ! Y1 = val; ! else case 40: ! if (target_dsp) ! SET_MOD (val); ! else case 35: case 36: case 37: case 38: case 39: ! SET_FI (rn - 25, val); break; ! case 41: SSR = val; break; ! case 42: SPC = val; break; /* The rn_bank idiosyncracies are not due to hardware differences, but to a weird aliasing naming scheme for sh3 / sh3e / sh4. */ ! case 43: ! if (target_dsp) ! RS = val; ! else case 44: ! if (target_dsp) ! RE = val; ! else case 45: case 46: case 47: case 48: case 49: case 50: if (SR_MD && SR_RB) ! Rn_BANK (rn - 43) = val; else ! saved_state.asregs.regs[rn - 43] = val; break; ! case 51: case 52: case 53: case 54: case 55: case 56: case 57: case 58: ! if (target_dsp || ! SR_MD || ! SR_RB) ! SET_Rn_BANK (rn - 51, val); else ! saved_state.asregs.regs[rn - 51] = val; break; default: return 0; --- 1791,1912 ---- val = swap (* (int *)memory); switch (rn) { ! case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM: ! case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM: ! case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM: ! case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM: ! case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM: ! case SIM_SH_R15_REGNUM: saved_state.asregs.regs[rn] = val; break; ! case SIM_SH_PC_REGNUM: saved_state.asregs.pc = val; break; ! case SIM_SH_PR_REGNUM: PR = val; break; ! case SIM_SH_GBR_REGNUM: GBR = val; break; ! case SIM_SH_VBR_REGNUM: VBR = val; break; ! case SIM_SH_MACH_REGNUM: MACH = val; break; ! case SIM_SH_MACL_REGNUM: MACL = val; break; ! case SIM_SH_SR_REGNUM: SET_SR (val); break; ! case SIM_SH_FPUL_REGNUM: FPUL = val; break; ! case SIM_SH_FPSCR_REGNUM: SET_FPSCR (val); break; ! case SIM_SH_FR0_REGNUM: case SIM_SH_FR1_REGNUM: case SIM_SH_FR2_REGNUM: ! case SIM_SH_FR3_REGNUM: case SIM_SH_FR4_REGNUM: case SIM_SH_FR5_REGNUM: ! case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM: ! case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM: ! case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM: ! case SIM_SH_FR15_REGNUM: ! SET_FI (rn - SIM_SH_FR0_REGNUM, val); break; ! case SIM_SH_DSR_REGNUM: ! DSR = val; ! break; ! case SIM_SH_A0G_REGNUM: ! A0G = val; ! break; ! case SIM_SH_A0_REGNUM: ! A0 = val; ! break; ! case SIM_SH_A1G_REGNUM: ! A1G = val; ! break; ! case SIM_SH_A1_REGNUM: ! A1 = val; ! break; ! case SIM_SH_M0_REGNUM: ! M0 = val; ! break; ! case SIM_SH_M1_REGNUM: ! M1 = val; ! break; ! case SIM_SH_X0_REGNUM: ! X0 = val; ! break; ! case SIM_SH_X1_REGNUM: ! X1 = val; ! break; ! case SIM_SH_Y0_REGNUM: ! Y0 = val; ! break; ! case SIM_SH_Y1_REGNUM: ! Y1 = val; ! break; ! case SIM_SH_MOD_REGNUM: ! SET_MOD (val); ! break; ! case SIM_SH_RS_REGNUM: ! RS = val; ! break; ! case SIM_SH_RE_REGNUM: ! RE = val; ! break; ! case SIM_SH_SSR_REGNUM: SSR = val; break; ! case SIM_SH_SPC_REGNUM: SPC = val; break; /* The rn_bank idiosyncracies are not due to hardware differences, but to a weird aliasing naming scheme for sh3 / sh3e / sh4. */ ! case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM: ! case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM: ! case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM: ! case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM: if (SR_MD && SR_RB) ! Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) = val; else ! saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM] = val; break; ! case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM: ! case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM: ! case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM: ! case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM: ! if (SR_MD && SR_RB) ! saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM] = val; else ! Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM) = val; ! break; ! case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM: ! case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM: ! case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM: ! case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM: ! SET_Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM, val); break; default: return 0; *************** sim_fetch_register (sd, rn, memory, leng *** 1901,1996 **** init_pointers (); switch (rn) { ! case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: ! case 8: case 9: case 10: case 11: case 12: case 13: case 14: case 15: val = saved_state.asregs.regs[rn]; break; ! case 16: val = saved_state.asregs.pc; break; ! case 17: val = PR; break; ! case 18: val = GBR; break; ! case 19: val = VBR; break; ! case 20: val = MACH; break; ! case 21: val = MACL; break; ! case 22: val = GET_SR (); break; ! case 23: val = FPUL; break; ! case 24: val = GET_FPSCR (); break; ! case 25: ! val = target_dsp ? SEXT (A0G) : FI (0); break; ! case 26: ! val = target_dsp ? A0 : FI (1); break; ! case 27: ! val = target_dsp ? SEXT (A1G) : FI (2); break; ! case 28: ! val = target_dsp ? A1 : FI (3); break; ! case 29: ! val = target_dsp ? M0 : FI (4); break; ! case 30: ! val = target_dsp ? M1 : FI (5); break; ! case 31: ! val = target_dsp ? X0 : FI (6); break; ! case 32: ! val = target_dsp ? X1 : FI (7); break; ! case 33: ! val = target_dsp ? Y0 : FI (8); break; ! case 34: ! val = target_dsp ? Y1 : FI (9); break; ! case 35: case 36: case 37: case 38: case 39: ! val = FI (rn - 25); break; ! case 40: ! val = target_dsp ? MOD : FI (15); break; ! case 41: val = SSR; break; ! case 42: val = SPC; break; /* The rn_bank idiosyncracies are not due to hardware differences, but to a weird aliasing naming scheme for sh3 / sh3e / sh4. */ ! case 43: ! if (target_dsp) ! val = RS; ! else case 44: ! if (target_dsp) ! val = RE; ! else case 45: case 46: case 47: case 48: case 49: case 50: ! val = (SR_MD && SR_RB ! ? Rn_BANK (rn - 43) ! : saved_state.asregs.regs[rn - 43]); ! break; ! case 51: case 52: case 53: case 54: case 55: case 56: case 57: case 58: ! val = (target_dsp || ! SR_MD || ! SR_RB ! ? Rn_BANK (rn - 51) ! : saved_state.asregs.regs[rn - 51]); break; default: return 0; --- 1926,2045 ---- init_pointers (); switch (rn) { ! case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM: ! case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM: ! case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM: ! case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM: ! case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM: ! case SIM_SH_R15_REGNUM: val = saved_state.asregs.regs[rn]; break; ! case SIM_SH_PC_REGNUM: val = saved_state.asregs.pc; break; ! case SIM_SH_PR_REGNUM: val = PR; break; ! case SIM_SH_GBR_REGNUM: val = GBR; break; ! case SIM_SH_VBR_REGNUM: val = VBR; break; ! case SIM_SH_MACH_REGNUM: val = MACH; break; ! case SIM_SH_MACL_REGNUM: val = MACL; break; ! case SIM_SH_SR_REGNUM: val = GET_SR (); break; ! case SIM_SH_FPUL_REGNUM: val = FPUL; break; ! case SIM_SH_FPSCR_REGNUM: val = GET_FPSCR (); break; ! case SIM_SH_FR0_REGNUM: case SIM_SH_FR1_REGNUM: case SIM_SH_FR2_REGNUM: ! case SIM_SH_FR3_REGNUM: case SIM_SH_FR4_REGNUM: case SIM_SH_FR5_REGNUM: ! case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM: ! case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM: ! case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM: ! case SIM_SH_FR15_REGNUM: ! val = FI (rn - SIM_SH_FR0_REGNUM); break; ! case SIM_SH_DSR_REGNUM: ! val = DSR; break; ! case SIM_SH_A0G_REGNUM: ! val = SEXT (A0G); break; ! case SIM_SH_A0_REGNUM: ! val = A0; break; ! case SIM_SH_A1G_REGNUM: ! val = SEXT (A1G); break; ! case SIM_SH_A1_REGNUM: ! val = A1; break; ! case SIM_SH_M0_REGNUM: ! val = M0; break; ! case SIM_SH_M1_REGNUM: ! val = M1; break; ! case SIM_SH_X0_REGNUM: ! val = X0; break; ! case SIM_SH_X1_REGNUM: ! val = X1; ! break; ! case SIM_SH_Y0_REGNUM: ! val = Y0; ! break; ! case SIM_SH_Y1_REGNUM: ! val = Y1; ! break; ! case SIM_SH_MOD_REGNUM: ! val = MOD; break; ! case SIM_SH_RS_REGNUM: ! val = RS; break; ! case SIM_SH_RE_REGNUM: ! val = RE; break; ! case SIM_SH_SSR_REGNUM: val = SSR; break; ! case SIM_SH_SPC_REGNUM: val = SPC; break; /* The rn_bank idiosyncracies are not due to hardware differences, but to a weird aliasing naming scheme for sh3 / sh3e / sh4. */ ! case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM: ! case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM: ! case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM: ! case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM: ! val = (SR_MD && SR_RB ! ? Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) ! : saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM]); ! break; ! case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM: ! case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM: ! case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM: ! case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM: ! val = (! SR_MD || ! SR_RB ! ? Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM) ! : saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM]); ! break; ! case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM: ! case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM: ! case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM: ! case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM: ! val = Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM); break; default: return 0; Index: gdb/sh-tdep.c =================================================================== RCS file: /cvs/src/src/gdb/sh-tdep.c,v retrieving revision 1.65 diff -p -r1.65 sh-tdep.c *** gdb/sh-tdep.c 26 Jun 2002 15:28:46 -0000 1.65 --- gdb/sh-tdep.c 3 Jul 2002 20:32:49 -0000 *************** *** 54,59 **** --- 54,61 ---- void (*sh_show_regs) (void); CORE_ADDR (*skip_prologue_hard_way) (CORE_ADDR); void (*do_pseudo_register) (int); + static int sh_dsp_register_sim_regno (int); + #define SH_DEFAULT_NUM_REGS 59 *************** sh_gdbarch_init (struct gdbarch_info inf *** 4280,4285 **** --- 4282,4288 ---- set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); set_gdbarch_pop_frame (gdbarch, sh_pop_frame); set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh); + set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); skip_prologue_hard_way = sh_skip_prologue_hard_way; do_pseudo_register = sh_do_pseudo_register; *************** sh_gdbarch_init (struct gdbarch_info inf *** 4314,4319 **** --- 4317,4323 ---- set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); set_gdbarch_register_byte (gdbarch, sh_default_register_byte); + set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); tdep->DSR_REGNUM = 24; tdep->A0G_REGNUM = 25; tdep->A0_REGNUM = 26; *************** _initialize_sh_tdep (void) *** 4600,4603 **** --- 4604,4648 ---- gdbarch_register (bfd_arch_sh, sh_gdbarch_init, sh_dump_tdep); add_com ("regs", class_vars, sh_show_regs_command, "Print all registers"); + } + + enum + { + DSP_DSR_REGNUM = 24, + DSP_A0G_REGNUM, + DSP_A0_REGNUM, + DSP_A1G_REGNUM, + DSP_A1_REGNUM, + DSP_M0_REGNUM, + DSP_M1_REGNUM, + DSP_X0_REGNUM, + DSP_X1_REGNUM, + DSP_Y0_REGNUM, + DSP_Y1_REGNUM, + + DSP_MOD_REGNUM = 40, + + DSP_RS_REGNUM = 43, + DSP_RE_REGNUM, + + DSP_R0_BANK_REGNUM = 51, + DSP_R7_BANK_REGNUM = DSP_R0_BANK_REGNUM + 7 + }; + + static int + sh_dsp_register_sim_regno (int nr) + { + if (legacy_register_sim_regno (nr) < 0) + return legacy_register_sim_regno (nr); + if (nr >= DSP_DSR_REGNUM && nr < DSP_Y1_REGNUM) + return nr - DSP_DSR_REGNUM + SIM_SH_DSR_REGNUM; + if (nr == DSP_MOD_REGNUM) + return SIM_SH_MOD_REGNUM; + if (nr == DSP_RS_REGNUM) + return SIM_SH_RS_REGNUM; + if (nr == DSP_RE_REGNUM) + return SIM_SH_RE_REGNUM; + if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM) + return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; + return nr; } --------------FFAD0C322ACEF3AC862A6EF9--