include/gdb: Wed May 15 11:56:40 2002 J"orn Rennecke * sim-sh.h: Add constants for sh1-sh4 AND sh{3}-dsp. sim/sh: Wed May 15 11:56:40 2002 J"orn Rennecke * interp.c (sim_fetch_register, sim_store_register): Use them. Index: include/gdb/sim-sh.h =================================================================== RCS file: /cvs/src/src/include/gdb/sim-sh.h,v retrieving revision 1.1 diff -p -r1.1 sim-sh.h *** include/gdb/sim-sh.h 10 May 2002 22:53:56 -0000 1.1 --- include/gdb/sim-sh.h 15 May 2002 11:55:03 -0000 *************** extern "C" { // } *** 28,33 **** --- 28,62 ---- enum { + SIM_SH_R0_REGNUM = 0, SIM_SH_R1_REGNUM, SIM_SH_R2_REGNUM, SIM_SH_R3_REGNUM, + SIM_SH_R4_REGNUM, SIM_SH_R5_REGNUM, SIM_SH_R6_REGNUM, SIM_SH_R7_REGNUM, + SIM_SH_R8_REGNUM, SIM_SH_R9_REGNUM, SIM_SH_R10_REGNUM, SIM_SH_R11_REGNUM, + SIM_SH_R12_REGNUM, SIM_SH_R13_REGNUM, SIM_SH_R14_REGNUM, SIM_SH_R15_REGNUM, + SIM_SH_PC_REGNUM, SIM_SH_PR_REGNUM, + SIM_SH_GBR_REGNUM, SIM_SH_VBR_REGNUM, + SIM_SH_MACH_REGNUM, SIM_SH_MACL_REGNUM, SIM_SH_SR_REGNUM, + SIM_SH_FPUL_REGNUM, SIM_SH_FPSCR_REGNUM, + SIM_SH_FR0_REGNUM = 25, /* sh3e / sh4 */ + /* sh[3]-dsp */ + SIM_SH_DSR_REGNUM = 24, + SIM_SH_A0G_REGNUM, SIM_SH_A0_REGNUM, + SIM_SH_A1G_REGNUM, SIM_SH_A1_REGNUM, + SIM_SH_M0_REGNUM, SIM_SH_M1_REGNUM, + SIM_SH_X0_REGNUM, SIM_SH_X1_REGNUM, + SIM_SH_Y0_REGNUM, SIM_SH_Y1_REGNUM, + SIM_SH_MOD_REGNUM = 40, + SIM_SH_SSR_REGNUM = 41, SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */ + SIM_SH_RS_REGNUM = 43, SIM_SH_RE_REGNUM, /* sh[3]-dsp */ + SIM_SH_R0_BANK0_REGNUM = 43, SIM_SH_R7_BANK0_REGNUM = 50, /* sh3[e] / sh4 */ + SIM_SH_R0_BANK1_REGNUM = 51, SIM_SH_R7_BANK1_REGNUM = 58, /* sh3[e] / sh4 */ + SIM_SH_R0_BANK_REGNUM = 51, SIM_SH_R7_BANK_REGNUM = 58, /* sh[3]-dsp */ + SIM_SH_XF0_REGNUM = 59, + SIM_SH_SGR_REGNUM = 75, + SIM_SH_DBR_REGNUM = 76, + SIM_SH4_NUM_REGS, + /* 77..127: room for expansion. */ + + SIM_SH64_R0_REGNUM = 0, SIM_SH64_SP_REGNUM = 15, SIM_SH64_PC_REGNUM = 64, Index: sim/sh/interp.c =================================================================== RCS file: /cvs/src/src/sim/sh/interp.c,v retrieving revision 1.4 diff -p -r1.4 interp.c *** sim/sh/interp.c 30 Jan 2001 23:03:56 -0000 1.4 --- sim/sh/interp.c 15 May 2002 11:55:08 -0000 *************** *** 29,34 **** --- 29,35 ---- #include "bfd.h" #include "callback.h" #include "remote-sim.h" + #include "gdb/sim-sh.h" /* This file is local - if newlib changes, then so should this. */ #include "syscall.h" *************** sim_store_register (sd, rn, memory, leng *** 1790,1887 **** val = swap (* (int *)memory); switch (rn) { ! case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: ! case 8: case 9: case 10: case 11: case 12: case 13: case 14: case 15: saved_state.asregs.regs[rn] = val; break; ! case 16: saved_state.asregs.pc = val; break; ! case 17: PR = val; break; ! case 18: GBR = val; break; ! case 19: VBR = val; break; ! case 20: MACH = val; break; ! case 21: MACL = val; break; ! case 22: SET_SR (val); break; ! case 23: FPUL = val; break; ! case 24: SET_FPSCR (val); break; ! case 25: if (target_dsp) A0G = val; ! else case 26: if (target_dsp) A0 = val; ! else case 27: if (target_dsp) A1G = val; ! else case 28: if (target_dsp) A1 = val; ! else case 29: if (target_dsp) M0 = val; ! else case 30: if (target_dsp) M1 = val; ! else case 31: if (target_dsp) X0 = val; ! else case 32: if (target_dsp) X1 = val; ! else case 33: if (target_dsp) Y0 = val; ! else case 34: if (target_dsp) Y1 = val; ! else case 40: if (target_dsp) SET_MOD (val); ! else case 35: case 36: case 37: case 38: case 39: ! SET_FI (rn - 25, val); break; ! case 41: SSR = val; break; ! case 42: SPC = val; break; /* The rn_bank idiosyncracies are not due to hardware differences, but to a weird aliasing naming scheme for sh3 / sh3e / sh4. */ ! case 43: if (target_dsp) RS = val; ! else case 44: if (target_dsp) RE = val; ! else case 45: case 46: case 47: case 48: case 49: case 50: if (SR_MD && SR_RB) ! Rn_BANK (rn - 43) = val; else ! saved_state.asregs.regs[rn - 43] = val; break; ! case 51: case 52: case 53: case 54: case 55: case 56: case 57: case 58: if (target_dsp || ! SR_MD || ! SR_RB) ! SET_Rn_BANK (rn - 51, val); else ! saved_state.asregs.regs[rn - 51] = val; break; default: return 0; --- 1791,1899 ---- val = swap (* (int *)memory); switch (rn) { ! case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM: ! case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM: ! case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM: ! case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM: ! case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM: ! case SIM_SH_R15_REGNUM: saved_state.asregs.regs[rn] = val; break; ! case SIM_SH_PC_REGNUM: saved_state.asregs.pc = val; break; ! case SIM_SH_PR_REGNUM: PR = val; break; ! case SIM_SH_GBR_REGNUM: GBR = val; break; ! case SIM_SH_VBR_REGNUM: VBR = val; break; ! case SIM_SH_MACH_REGNUM: MACH = val; break; ! case SIM_SH_MACL_REGNUM: MACL = val; break; ! case SIM_SH_SR_REGNUM: SET_SR (val); break; ! case SIM_SH_FPUL_REGNUM: FPUL = val; break; ! case SIM_SH_FPSCR_REGNUM: SET_FPSCR (val); break; ! case SIM_SH_A0G_REGNUM: if (target_dsp) A0G = val; ! else case SIM_SH_A0_REGNUM: if (target_dsp) A0 = val; ! else case SIM_SH_A1G_REGNUM: if (target_dsp) A1G = val; ! else case SIM_SH_A1_REGNUM: if (target_dsp) A1 = val; ! else case SIM_SH_M0_REGNUM: if (target_dsp) M0 = val; ! else case SIM_SH_M1_REGNUM: if (target_dsp) M1 = val; ! else case SIM_SH_X0_REGNUM: if (target_dsp) X0 = val; ! else case SIM_SH_X1_REGNUM: if (target_dsp) X1 = val; ! else case SIM_SH_Y0_REGNUM: if (target_dsp) Y0 = val; ! else case SIM_SH_Y1_REGNUM: if (target_dsp) Y1 = val; ! else case SIM_SH_MOD_REGNUM: if (target_dsp) SET_MOD (val); ! else case SIM_SH_FR0_REGNUM+10: ! case SIM_SH_FR0_REGNUM+11: case SIM_SH_FR0_REGNUM+12: ! case SIM_SH_FR0_REGNUM+13: case SIM_SH_FR0_REGNUM+14: ! SET_FI (rn - SIM_SH_FR0_REGNUM, val); break; ! case SIM_SH_SSR_REGNUM: SSR = val; break; ! case SIM_SH_SPC_REGNUM: SPC = val; break; /* The rn_bank idiosyncracies are not due to hardware differences, but to a weird aliasing naming scheme for sh3 / sh3e / sh4. */ ! case SIM_SH_RS_REGNUM: if (target_dsp) RS = val; ! else case SIM_SH_RE_REGNUM: if (target_dsp) RE = val; ! else case SIM_SH_R0_BANK0_REGNUM+2: case SIM_SH_R0_BANK0_REGNUM+3: ! case SIM_SH_R0_BANK0_REGNUM+4: case SIM_SH_R0_BANK0_REGNUM+5: ! case SIM_SH_R0_BANK0_REGNUM+6: case SIM_SH_R0_BANK0_REGNUM+7: if (SR_MD && SR_RB) ! Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) = val; else ! saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM] = val; break; ! case SIM_SH_R0_BANK_REGNUM+0: case SIM_SH_R0_BANK_REGNUM+1: ! case SIM_SH_R0_BANK_REGNUM+2: case SIM_SH_R0_BANK_REGNUM+3: ! case SIM_SH_R0_BANK_REGNUM+4: case SIM_SH_R0_BANK_REGNUM+5: ! case SIM_SH_R0_BANK_REGNUM+6: case SIM_SH_R0_BANK_REGNUM+7: if (target_dsp || ! SR_MD || ! SR_RB) ! SET_Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM, val); else ! saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM] = val; break; default: return 0; *************** sim_fetch_register (sd, rn, memory, leng *** 1901,1996 **** init_pointers (); switch (rn) { ! case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: ! case 8: case 9: case 10: case 11: case 12: case 13: case 14: case 15: val = saved_state.asregs.regs[rn]; break; ! case 16: val = saved_state.asregs.pc; break; ! case 17: val = PR; break; ! case 18: val = GBR; break; ! case 19: val = VBR; break; ! case 20: val = MACH; break; ! case 21: val = MACL; break; ! case 22: val = GET_SR (); break; ! case 23: val = FPUL; break; ! case 24: val = GET_FPSCR (); break; ! case 25: ! val = target_dsp ? SEXT (A0G) : FI (0); ! break; ! case 26: ! val = target_dsp ? A0 : FI (1); ! break; ! case 27: ! val = target_dsp ? SEXT (A1G) : FI (2); ! break; ! case 28: ! val = target_dsp ? A1 : FI (3); ! break; ! case 29: ! val = target_dsp ? M0 : FI (4); ! break; ! case 30: ! val = target_dsp ? M1 : FI (5); ! break; ! case 31: ! val = target_dsp ? X0 : FI (6); ! break; ! case 32: ! val = target_dsp ? X1 : FI (7); ! break; ! case 33: ! val = target_dsp ? Y0 : FI (8); ! break; ! case 34: ! val = target_dsp ? Y1 : FI (9); ! break; ! case 35: case 36: case 37: case 38: case 39: ! val = FI (rn - 25); ! break; ! case 40: ! val = target_dsp ? MOD : FI (15); break; ! case 41: val = SSR; break; ! case 42: val = SPC; break; /* The rn_bank idiosyncracies are not due to hardware differences, but to a weird aliasing naming scheme for sh3 / sh3e / sh4. */ ! case 43: if (target_dsp) val = RS; ! else case 44: if (target_dsp) val = RE; ! else case 45: case 46: case 47: case 48: case 49: case 50: val = (SR_MD && SR_RB ! ? Rn_BANK (rn - 43) ! : saved_state.asregs.regs[rn - 43]); break; ! case 51: case 52: case 53: case 54: case 55: case 56: case 57: case 58: val = (target_dsp || ! SR_MD || ! SR_RB ! ? Rn_BANK (rn - 51) ! : saved_state.asregs.regs[rn - 51]); break; default: return 0; --- 1913,2019 ---- init_pointers (); switch (rn) { ! case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM: ! case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM: ! case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM: ! case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM: ! case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM: ! case SIM_SH_R15_REGNUM: val = saved_state.asregs.regs[rn]; break; ! case SIM_SH_PC_REGNUM: val = saved_state.asregs.pc; break; ! case SIM_SH_PR_REGNUM: val = PR; break; ! case SIM_SH_GBR_REGNUM: val = GBR; break; ! case SIM_SH_VBR_REGNUM: val = VBR; break; ! case SIM_SH_MACH_REGNUM: val = MACH; break; ! case SIM_SH_MACL_REGNUM: val = MACL; break; ! case SIM_SH_SR_REGNUM: val = GET_SR (); break; ! case SIM_SH_FPUL_REGNUM: val = FPUL; break; ! case SIM_SH_FPSCR_REGNUM: val = GET_FPSCR (); break; ! case SIM_SH_A0G_REGNUM: ! if (target_dsp) ! val = SEXT (A0G); ! else case SIM_SH_A0_REGNUM: ! if (target_dsp) ! val = A0; ! else case SIM_SH_A1G_REGNUM: ! if (target_dsp) ! val = SEXT (A1G); ! else case SIM_SH_A1_REGNUM: ! if (target_dsp) ! val = A1; ! else case SIM_SH_M0_REGNUM: ! if (target_dsp) ! val = M0; ! else case SIM_SH_M1_REGNUM: ! if (target_dsp) ! val = M1; ! else case SIM_SH_X0_REGNUM: ! if (target_dsp) ! val = X0; ! else case SIM_SH_X1_REGNUM: ! if (target_dsp) ! val = X1; ! else case SIM_SH_Y0_REGNUM: ! if (target_dsp) ! val = Y0; ! else case SIM_SH_Y1_REGNUM: ! if (target_dsp) ! val = Y1; ! else case SIM_SH_MOD_REGNUM: ! if (target_dsp) ! val = MOD; ! else case SIM_SH_FR0_REGNUM+10: ! case SIM_SH_FR0_REGNUM+11: case SIM_SH_FR0_REGNUM+12: ! case SIM_SH_FR0_REGNUM+13: case SIM_SH_FR0_REGNUM+14: ! val = FI (rn - SIM_SH_FR0_REGNUM); break; ! case SIM_SH_SSR_REGNUM: val = SSR; break; ! case SIM_SH_SPC_REGNUM: val = SPC; break; /* The rn_bank idiosyncracies are not due to hardware differences, but to a weird aliasing naming scheme for sh3 / sh3e / sh4. */ ! case SIM_SH_RS_REGNUM: if (target_dsp) val = RS; ! else case SIM_SH_RE_REGNUM: if (target_dsp) val = RE; ! else case SIM_SH_R0_BANK0_REGNUM+2: case SIM_SH_R0_BANK0_REGNUM+3: ! case SIM_SH_R0_BANK0_REGNUM+4: case SIM_SH_R0_BANK0_REGNUM+5: ! case SIM_SH_R0_BANK0_REGNUM+6: case SIM_SH_R0_BANK0_REGNUM+7: val = (SR_MD && SR_RB ! ? Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) ! : saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM]); break; ! case SIM_SH_R0_BANK_REGNUM+0: case SIM_SH_R0_BANK_REGNUM+1: ! case SIM_SH_R0_BANK_REGNUM+2: case SIM_SH_R0_BANK_REGNUM+3: ! case SIM_SH_R0_BANK_REGNUM+4: case SIM_SH_R0_BANK_REGNUM+5: ! case SIM_SH_R0_BANK_REGNUM+6: case SIM_SH_R0_BANK_REGNUM+7: val = (target_dsp || ! SR_MD || ! SR_RB ! ? Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM) ! : saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM]); break; default: return 0;