From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 17154 invoked by alias); 3 Jan 2002 06:58:40 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 17074 invoked from network); 3 Jan 2002 06:58:36 -0000 Received: from unknown (HELO localhost.cygnus.com) (24.114.42.213) by sources.redhat.com with SMTP; 3 Jan 2002 06:58:36 -0000 Received: from cygnus.com (localhost [127.0.0.1]) by localhost.cygnus.com (Postfix) with ESMTP id 7FAAF3C4F; Thu, 3 Jan 2002 01:58:33 -0500 (EST) Message-ID: <3C340119.70201@cygnus.com> Date: Wed, 02 Jan 2002 22:58:00 -0000 From: Andrew Cagney User-Agent: Mozilla/5.0 (X11; U; NetBSD macppc; en-US; rv:0.9.6) Gecko/20011207 X-Accept-Language: en-us MIME-Version: 1.0 To: matthew green Cc: gdb-patches@sources.redhat.com Subject: Re: [patch] AltiVec support for PSIM. References: <12687.1009590505@cygnus.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2002-01/txt/msg00007.txt.bz2 > 2001-12-29 matthew green > > * sim/configure.in (extra_subdirs): Add testsuite for ppc. > * sim/configure: Regenerate. > > * sim/ppc/idecode_expression.h (ALTIVEC_SET_CR6): New macro. > (ALTIVEC_SET_SAT): Likewise. > * sim/ppc/main.c (zalloc): Fix typo in error message. This bit is a separate patch and can, separatly, just go straight in. > * sim/ppc/ppc-cache-rules (VS, vS, VS_BITMASK): New cache entries. > (VA, vA, vA_BITMASK, VB, vB, vB_BITMASK, VC, vC, vC_BITMASK): Likewise. > * sim/ppc/ppc-instructions (PPC_INSN_INT_VR): New model macros. > (PPC_INSN_VR, PPC_INSN_VR_CR, PPC_INSN_VR_VSCR, PPC_INSN_FROM_VSCR, > PPC_INSN_TO_VSCR): Likewise. > (model_trace_altivec_busy_p, model_trace_altivec_make_busy): New model > functions. > (struct _model_busy, struct _model_data): New vr_busy and vscr_busy > elements. > (model_trace_release): Add vr_busy and vrcr_busy support. > (model_new_cycle): Likewise. > (model_make): Likewise. > (ppc_insn_int_vr, ppc_insn_vr, ppc_insn_vr_cr): New model functions. > (ppc_insn_vr_vscr, ppc_insn_from_vscr, ppc_insn_to_vscr): Likewise. > (altivec_signed_saturate_8, altivec_signed_saturate_16): Likewise. > (altivec_signed_saturate_32, altivec_unsigned_saturate_8): Likewise. > (altivec_unsigned_saturate_16, altivec_unsigned_saturate_32): Likewise. > (lvebx, lvehx, lvewx, lvsl, lvsr, lvx, lvxl): New AltiVec instructions. > (mfvrsave, mfvscr, mtvrsave, mtvscr, stvebx, stvehx, stvewx): Likewise. > (stvx, stvxl, vaddcuw, vaddfp, vaddsbs, vaddshs, vaddsws): Likewise. > (vaddubm, vaddubs, vadduhm, vadduhs, vadduwm, vadduws, vand): Likewise. > (vandc, vavgsb, vavgsh, vavgsw, vavgub, vavguh, vavguw): Likewise. > (vcfsx, vcfux, vcmpbfp, vcmpeqfp, vcmpequb, vcmpequh): Likewise. > (vcmpequw, vcmpgefp, vcmpgtfp, vcmpgtsb, vcmpgtsh, vcmpgtsw): Likewise. > (vcmpgtub, vcmpgtuh, vcmpgtuw, vctsxs, vctuxs, vexptefp): Likewise. > (vlogefp, vmaddfp, vmaxfp, vmaxsb, vmaxsh, vmaxsw, vmaxub): Likewise. > (vmaxuh, vmaxuw, vmhaddshs, vmhraddshs, vminfp, vminsb): Likewise. > (vminsh, vminsw, vminub, vminuh, vminuw, vmladduhm, vmrghb): Likewise. > (vmrghh, vmrghw, vmrglb, vmrglh, vmrglw, vmsummbm, vmsumshm): Likewise. > (vmsumshs, vmsumubm, vmsumuhm, vmsumuhs, vmulesb, vmulesh): Likewise. > (vmuleub, vmuleuh, vmulosb, vmulosh, vmuloub, vmulouh): Likewise. > (vnmsubfp, vnor, vor, vperm, vpkpx, vpkshss, vpkshus): Likewise. > (vpkswss, vpkswus, vpkuhum, vpkuhus, vpkuwum, vpkuwus, vrefp): Likewise. > (vrfim, vrfin, vrfip, vrfiz, vrlb, vrlh, vrlw, vrsqrtefp): Likewise. > (vsel, vsl, vslb, vsldoi, vslh, vslo, vslw, vspltb, vsplth): Likewise. > (vspltisb, vspltish, vspltisw, vspltw, vsr, vsrab, vsrah): Likewise. > (vsraw, vsrb, vsrh, vsro, vsrw, vsubcuw, vsubfp, vsubsbs): Likewise. > (vsubshs, vsubsws, vsububm, vsububs, vsubuhm, vsubuhs): Likewise. > (vsubuwm, vsubuws, vsum2sws, vsum4sbs, vsum4shs, vsum4ubs): Likewise. > (vsumsws, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb): Likewise. > (vupklsh, vxor): Likewise. > * sim/ppc/ppc-spr-table (VRSAVE): New SPR number 256. > * sim/ppc/psim.c (psim_read_register): Add vreg and 16-bit support. > * sim/ppc/psim.c (psim_write_register): Likewise. > * sim/ppc/registers.c (register_description): Add vr and vscr support. > * sim/ppc/registers.h (vreg): New datatype for AltiVec registers. > (vscreg): New datatype for AltiVec Vector Status and Control Register. > (_registers): Add the VSCR and 32 AltiVec registers. > (registers_types): Add reg_vr and reg_vscr. > (VR, VSCR): New macros for VR registers and VSCR regsiters. > * sim/ppc/sim-endian.h (AV_BINDEX, AV_HINDEX): New macros. > > * sim/testsuite/sim/ppc/psim.exp: New file. > * sim/testsuite/sim/ppc/testutils.inc: New file. > * sim/testsuite/sim/ppc/*.s: New testsuite. I'm ok with testsuite changes are fine. (Well actually the more testsuite changes the better.) The tricky bit is with the file ppc-instructions. IBM, and not me, owns the copyright on the contents of that file (I've this amazing piece of paper from an IBM lawyer) so it is wrong / misleading to add those instructions to that file. Especially when, if I remember the politics correctly, the Altivec stuff is a Motorola special. I'm ok with adding the altivec instructions if they are in a separate file and if you've clarified their copyright status with Motorola. That just leaves the problem of how to generate an altivec enabled simulator from two files. I can think of two alternatives: steal code from the more up-to-date sim/igen generator as that supports a ``:include:'' directive; pull a nasty hack such as `cat ppc-instructions altivec.igen > tmp.igen` comes to mind (it does defeat igen's ability to refer back to source code lines though). Given that I suspect you're going to need to be able to generate multiple simulators - with / without Altivec, stealing code from sim/igen might be the better medium to long term option. Since, as illustrated by MIPS, sim/igen supports this. Andrew