From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 5825 invoked by alias); 4 Feb 2019 19:45:57 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 5812 invoked by uid 89); 4 Feb 2019 19:45:56 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_PASS autolearn=ham version=3.3.2 spammy=HTo:D*ca X-HELO: mx2.freebsd.org Received: from mx2.freebsd.org (HELO mx2.freebsd.org) (8.8.178.116) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 04 Feb 2019 19:45:55 +0000 Received: from mx1.freebsd.org (mx1.freebsd.org [96.47.72.80]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client CN "mx1.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx2.freebsd.org (Postfix) with ESMTPS id 0D5A98A71A; Mon, 4 Feb 2019 19:45:53 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from smtp.freebsd.org (smtp.freebsd.org [96.47.72.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "smtp.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 5163B6F068; Mon, 4 Feb 2019 19:45:52 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from John-Baldwins-MacBook-Pro-3.local (ralph.baldwin.cx [66.234.199.215]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client did not present a certificate) (Authenticated sender: jhb) by smtp.freebsd.org (Postfix) with ESMTPSA id C77365279; Mon, 4 Feb 2019 19:45:51 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Subject: Re: [PATCH 2/9] Support fs_base and gs_base on FreeBSD/i386. To: Simon Marchi Cc: gdb-patches@sourceware.org References: From: John Baldwin Openpgp: preference=signencrypt Message-ID: <3902e7d4-f8df-7b05-45a0-8b5d5fc33980@FreeBSD.org> Date: Mon, 04 Feb 2019 19:45:00 -0000 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.12; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 5163B6F068 X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-2.97 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_SHORT(-0.98)[-0.980,0]; ASN(0.00)[asn:11403, ipnet:96.47.64.0/20, country:US]; NEURAL_HAM_MEDIUM(-0.99)[-0.992,0]; NEURAL_HAM_LONG(-1.00)[-0.999,0] X-IsSubscribed: yes X-SW-Source: 2019-02/txt/msg00017.txt.bz2 On 2/2/19 7:26 AM, Simon Marchi wrote: > On 2019-01-22 13:42, John Baldwin wrote: >> The i386 BSD native target uses the same ptrace operations >> (PT_[GS]ET[FG]SBASE) as the amd64 BSD native target to fetch and store >> the registers. >> >> The amd64 BSD native now uses 'tdep->fsbase_regnum' instead of >> hardcoding AMD64_FSBASE_REGNUM and AMD64_GSBASE_REGNUM to support >> 32-bit targets. In addition, the store operations explicitly zero the >> new register value before fetching it from the register cache to >> ensure 32-bit values are zero-extended. > > To be clear, this happens when debugging a 32-bits process on a 64-bits > OS? When debugging a 32-bits process on a 32-bits OS, the code in > i386-bsd-nat.c would be used? Correct. >> gdb/ChangeLog: >> >> * amd64-bsd-nat.c (amd64bsd_fetch_inferior_registers): Use >> tdep->fsbase_regnum instead of constants for fs_base and gs_base. >> (amd64bsd_store_inferior_registers): Likewise. >> * amd64-fbsd-nat.c (amd64_fbsd_nat_target::read_description): >> Enable segment base registers. >> * i386-bsd-nat.c (i386bsd_fetch_inferior_registers): Use >> PT_GETFSBASE and PT_GETGSBASE. >> (i386bsd_store_inferior_registers): Use PT_SETFSBASE and PT_SETGSBASE. >> * i386-fbsd-nat.c (i386_fbsd_nat_target::read_description): Enable >> segment base registers. >> * i386-fbsd-tdep.c (i386fbsd_core_read_description): Likewise. >> --- >> gdb/ChangeLog | 14 ++++++++++++ >> gdb/amd64-bsd-nat.c | 26 ++++++++++++++------- >> gdb/amd64-fbsd-nat.c | 4 ++-- >> gdb/i386-bsd-nat.c | 54 ++++++++++++++++++++++++++++++++++++++++++++ >> gdb/i386-fbsd-nat.c | 2 +- >> gdb/i386-fbsd-tdep.c | 2 +- >> 6 files changed, 90 insertions(+), 12 deletions(-) >> >> diff --git a/gdb/ChangeLog b/gdb/ChangeLog >> index 4afd5b664e..056a60fa23 100644 >> --- a/gdb/ChangeLog >> +++ b/gdb/ChangeLog >> @@ -1,3 +1,17 @@ >> +2019-01-22 John Baldwin >> + >> + * amd64-bsd-nat.c (amd64bsd_fetch_inferior_registers): Use >> + tdep->fsbase_regnum instead of constants for fs_base and gs_base. >> + (amd64bsd_store_inferior_registers): Likewise. >> + * amd64-fbsd-nat.c (amd64_fbsd_nat_target::read_description): >> + Enable segment base registers. >> + * i386-bsd-nat.c (i386bsd_fetch_inferior_registers): Use >> + PT_GETFSBASE and PT_GETGSBASE. >> + (i386bsd_store_inferior_registers): Use PT_SETFSBASE and >> PT_SETGSBASE. >> + * i386-fbsd-nat.c (i386_fbsd_nat_target::read_description): Enable >> + segment base registers. >> + * i386-fbsd-tdep.c (i386fbsd_core_read_description): Likewise. >> + >> 2019-01-22 John Baldwin >> >> * amd64-fbsd-nat.c (amd64_fbsd_nat_target::read_description): >> diff --git a/gdb/amd64-bsd-nat.c b/gdb/amd64-bsd-nat.c >> index a2a91abb91..0f47ff6c61 100644 >> --- a/gdb/amd64-bsd-nat.c >> +++ b/gdb/amd64-bsd-nat.c >> @@ -43,6 +43,9 @@ amd64bsd_fetch_inferior_registers (struct regcache >> *regcache, int regnum) >> { >> struct gdbarch *gdbarch = regcache->arch (); >> pid_t pid = get_ptrace_pid (regcache->ptid ()); >> +#ifdef PT_GETFSBASE >> + const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); >> +#endif > > TDEP is used in both #ifdef PT_GETFSBASE and #ifdef PT_GETGSBASE, but is > only declared here in an #ifdef PT_GETFSBASE. I suppose it's not > actually an issue because they will always be present together. But we > might as well use "#if defined(PT_GETFSBASE) || defined(PT_GETGSBASE)" > for the declaration. Ok. I could also just perhaps collapse the other two #ifdef's instead of using separate ones. FreeBSD always provides both if it provides one. None of the other BSD's provide these currently. I suspect if they did they would always provide both. >> @@ -134,11 +140,13 @@ amd64bsd_store_inferior_registers (struct >> regcache *regcache, int regnum) >> } >> >> #ifdef PT_SETFSBASE >> - if (regnum == -1 || regnum == AMD64_FSBASE_REGNUM) >> + if (regnum == -1 || regnum == tdep->fsbase_regnum) >> { >> register_t base; >> >> - regcache->raw_collect (AMD64_FSBASE_REGNUM, &base); >> + /* Clear the full base value to support 32-bit targets. */ >> + base = 0; >> + regcache->raw_collect (tdep->fsbase_regnum, &base); > > It's probably safer to clear the value to 0 as you did, so that's fine. > But I would have thought that when debugging 32-bits processes, the high > bits would be ignored at some point. The kernel would know that this is > a 32 bits register, so it would just take the 32 low bits of what it > receives, and it magically works whatever the original data type is > because it's little endian. I had originally just done this out of paranoia, but I checked and FreeBSD's amd64 kernel will actually fail attempts to set the base address higher than 4G with EINVAL rather than silently truncating. -- John Baldwin                                                                            Â