From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 1304 invoked by alias); 2 Jun 2009 17:58:50 -0000 Received: (qmail 1293 invoked by uid 22791); 2 Jun 2009 17:58:45 -0000 X-SWARE-Spam-Status: No, hits=0.1 required=5.0 tests=AWL,BAYES_50,J_CHICKENPOX_24,J_CHICKENPOX_25,J_CHICKENPOX_41,J_CHICKENPOX_53 X-Spam-Check-By: sourceware.org Received: from web36205.mail.mud.yahoo.com (HELO web36205.mail.mud.yahoo.com) (209.191.68.231) by sourceware.org (qpsmtpd/0.43rc1) with SMTP; Tue, 02 Jun 2009 17:58:36 +0000 Received: (qmail 21967 invoked by uid 60001); 2 Jun 2009 17:58:34 -0000 Message-ID: <345036.20508.qm@web36205.mail.mud.yahoo.com> Received: from [123.237.143.201] by web36205.mail.mud.yahoo.com via HTTP; Tue, 02 Jun 2009 10:58:34 PDT Date: Tue, 02 Jun 2009 17:58:00 -0000 From: paawan oza Subject: Re: Submition of i386.record.floating.point.patch To: Hui Zhu Cc: gdb-patches@sourceware.org MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="0-968222875-1243965514=:20508" Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2009-06/txt/msg00022.txt.bz2 --0-968222875-1243965514=:20508 Content-Type: text/plain; charset=us-ascii Content-length: 26444 Hi Hui, I think, you have applied the old patch which I had sent earlier with in tar format. the correct patch was in the email body. I am attaching correct patch, please find it attached. the patch is tested against the example program which I have sent. Regards, Oza. --- On Tue, 6/2/09, Hui Zhu wrote: > From: Hui Zhu > Subject: Re: Submition of i386.record.floating.point.patch > To: "paawan oza" > Cc: gdb-patches@sourceware.org > Date: Tuesday, June 2, 2009, 12:27 PM > On Mon, Jun 1, 2009 at 22:54, paawan > oza > wrote: > > > > Hi, > > > > I am sorry for the inconvenience caused last time, > during patch submition. > > this time I am trying to post everything in email > body. > > > > > ****************************************************** > > ChangeLog: > > > ****************************************************** > > Current: gdb-6.8.50.20090531 > > 2009-05-31 Oza > > > > * i386-tdep.c: Support for floating point > recording. > > * i386-tdep.h: floating point registers > enumaration added. > > > ------------------------------------------------------- > > > > > ****************************************************** > > README: > > > ****************************************************** > > Patch description: > > > > -> Provides floating point support for i386 > (reversible debugging:record-replay) > > -> previously gdb was not recording floating point > registers, now all the floating point registers which are > likely to be changed by floating point instructions, are > recorded and replayed. > > -> the patch intends to provide the full support > for all i386 floating point instructions. > > > --------------------------------------------------------- > > > > > > > > > ****************************************************** > > Patch:i386-record-floats.patch > > > ****************************************************** > > diff -urN gdb.orig/i386-tdep.c gdb.new/i386-tdep.c > > --- gdb.orig/i386-tdep.c 2009-05-29 > 17:08:40.000000000 -0400 > > +++ gdb.new/i386-tdep.c 2009-06-01 20:02:23.000000000 > -0400 > > @@ -543,6 +543,9 @@ > > /* The maximum number of saved registers. This > should include all > > registers mentioned above, and %eip. */ > > #define I386_NUM_SAVED_REGS I386_NUM_GREGS > > +#define I386_SAVE_FPU_REGS 0xFFFD > > +#define I386_SAVE_FPU_ENV 0xFFFE > > +#define I386_SAVE_FPU_ENV_REG_STACK 0xFFFF > > > > struct i386_frame_cache > > { > > @@ -2985,6 +2988,54 @@ > > return 0; > > } > > > > +/* Record the value of floating point registers which > will be changed by the current instruction > > + to "record_arch_list". > > + return -1 if something is wrong. */ > > + > > +static int i386_record_floats(struct i386_record_s > *ir, uint32_t iregnum) > > +{ > > + int i; > > + > > + /* Oza : push/pop of fpu stack is going to happen > > + currently we store st0-st7 registers, but we > need not store all registers all the time. > > + using fstatus, we use 11-13 bits which gives > us stack top and hence we optimize our storage. */ > > + if (I386_SAVE_FPU_REGS == iregnum) > > + { > > + for > (i=I386_ST0_REGNUM;i<=I386_ST7_REGNUM;i++) > > + { > > + if (record_arch_list_add_reg > (ir->regcache,i)) > > + return -1; > > + } > > + } > > + else if (I386_SAVE_FPU_ENV == iregnum) > > + { > > + for (i=I386_FCTRL;i<=I386_FOP;i++) > > + { > > + if (record_arch_list_add_reg > (ir->regcache,i)) > > + return -1; > > + } > > + } > > + else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) > > + { > > + for (i=I386_ST0_REGNUM;i<=I386_FOP;i++) > > + { > > + if (record_arch_list_add_reg > (ir->regcache,i)) > > + return -1; > > + } > > + } > > + else if (iregnum >= I386_ST0_REGNUM && > iregnum <= I386_FOP) > > + { > > + if (record_arch_list_add_reg > (ir->regcache,iregnum)) > > + return -1; > > + } > > + else > > + { > > + /* param Error */ > > + return -1; > > + } > > + return 0; > > +} > > + > > /* Parse the current instruction and record the > values of the registers and > > memory that will be changed in current > instruction to "record_arch_list". > > Return -1 if something wrong. */ > > @@ -4035,7 +4086,6 @@ > > break; > > > > /* floats */ > > - /* It just record the memory change of > instrcution. */ > > case 0xd8: > > case 0xd9: > > case 0xda: > > @@ -4056,39 +4106,49 @@ > > return -1; > > switch (ir.reg) > > { > > - case 0x00: > > - case 0x01: > > case 0x02: > > - case 0x03: > > + case 0x12: > > + case 0x22: > > + case 0x32: > > + /* for FCOM, FICOM nothing to do > */ > > + break; > > + case 0x03: > > + case 0x13: > > + case 0x23: > > + case 0x33: > > + /* FCOMP, FICOMP pop FPU stack, > store all */ > > + if (i386_record_floats(&ir, > I386_SAVE_FPU_REGS)) > > + return -1; > > + break; > > + case 0x00: > > + case 0x01: > > case 0x04: > > case 0x05: > > case 0x06: > > case 0x07: > > case 0x10: > > - case 0x11: > > - case 0x12: > > - case 0x13: > > + case 0x11: > > case 0x14: > > case 0x15: > > case 0x16: > > case 0x17: > > case 0x20: > > case 0x21: > > - case 0x22: > > - case 0x23: > > case 0x24: > > case 0x25: > > case 0x26: > > case 0x27: > > case 0x30: > > case 0x31: > > - case 0x32: > > - case 0x33: > > case 0x34: > > case 0x35: > > case 0x36: > > case 0x37: > > - break; > > + /* FADD, FMUL, FSUB, FSUBR, FDIV, > FDIVR, FIADD, FIMUL, FISUB, FISUBR, FIDIV, FIDIVR > > + ModR/M.reg is an extension of > code, always affects st(0) register */ > > + if (i386_record_floats(&ir, > I386_ST0_REGNUM)) > > + return -1; > > + break; > > case 0x08: > > case 0x0a: > > case 0x0b: > > @@ -4096,6 +4156,7 @@ > > case 0x19: > > case 0x1a: > > case 0x1b: > > + case 0x1d: > > case 0x28: > > case 0x29: > > case 0x2a: > > @@ -4103,11 +4164,16 @@ > > case 0x38: > > case 0x39: > > case 0x3a: > > - case 0x3b: > > + case 0x3b: > > + case 0x3c: > > + case 0x3d: > > switch (ir.reg & 7) > > { > > case 0: > > - break; > > + /* FLD, FILD */ > > + if > (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) > > + return -1; > > + break; > > case 1: > > switch (ir.reg >> 4) > > { > > @@ -4120,6 +4186,7 @@ > > return -1; > > break; > > case 3: > > + break; > > default: > > if > (record_arch_list_add_mem (addr, 2)) > > return -1; > > @@ -4130,15 +4197,42 @@ > > switch (ir.reg >> 4) > > { > > case 0: > > + if > (record_arch_list_add_mem (addr, 4)) > > + return -1; > > + if (3 == (ir.reg & > 7)) > > + { > > + /* FSTP m32fp */ > > + if > (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) > > + return -1; > > + } > > + break; > > case 1: > > if > (record_arch_list_add_mem (addr, 4)) > > return -1; > > + if ((3 == (ir.reg > & 7)) || (5 == (ir.reg & 7)) || (7 == (ir.reg & > 7))) > > + { > > + /* FSTP */ > > + if > (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) > > + return -1; > > + } > > break; > > case 2: > > if > (record_arch_list_add_mem (addr, 8)) > > return -1; > > + if (3 == (ir.reg & > 7)) > > + { > > + /* FSTP m64fp */ > > + if > (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) > > + return -1; > > + } > > break; > > case 3: > > + if ((3 <= (ir.reg > & 7)) && (6 <= (ir.reg & 7))) > > + { > > + /* FISTP, FBLD, > FILD, FBSTP */ > > + if > (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) > > + return -1; > > + } > > default: > > if > (record_arch_list_add_mem (addr, 2)) > > return -1; > > @@ -4147,54 +4241,71 @@ > > break; > > } > > break; > > - case 0x0c: > > - case 0x0d: > > - case 0x1d: > > - case 0x2c: > > - case 0x3c: > > - case 0x3d: > > - break; > > - case 0x0e: > > + case 0x0c: > > + /* FLDENV */ > > + if (i386_record_floats(&ir, > I386_SAVE_FPU_ENV_REG_STACK)) > > + return -1; > > + break; > > + case 0x0d: > > + /* FLDCW */ > > + if (i386_record_floats(&ir, > I386_FCTRL)) > > + return -1; > > + break; > > + case 0x2c: > > + /* FRTSTOR */ > > + if (i386_record_floats(&ir, > I386_SAVE_FPU_ENV_REG_STACK)) > > + return -1; > > + break; > > + case 0x0e: > > if (ir.dflag) > > { > > - if (record_arch_list_add_mem > (addr, 28)) > > - return -1; > > + if (record_arch_list_add_mem > (addr, 28)) > > + return -1; > > } > > else > > { > > - if (record_arch_list_add_mem > (addr, 14)) > > - return -1; > > + if (record_arch_list_add_mem > (addr, 14)) > > + return -1; > > } > > break; > > - case 0x0f: > > - case 0x2f: > > + case 0x0f: > > + case 0x2f: > > if (record_arch_list_add_mem > (addr, 2)) > > return -1; > > break; > > - case 0x1f: > > - case 0x3e: > > + case 0x1f: > > + case 0x3e: > > if (record_arch_list_add_mem > (addr, 10)) > > return -1; > > + /* FSTP, FBSTP */ > > + if (i386_record_floats(&ir, > I386_SAVE_FPU_REGS)) > > + return -1; > > break; > > - case 0x2e: > > + case 0x2e: > > if (ir.dflag) > > { > > - if (record_arch_list_add_mem > (addr, 28)) > > - return -1; > > - addr += 28; > > + if (record_arch_list_add_mem > (addr, 28)) > > + return -1; > > + addr += 28; > > } > > else > > { > > - if (record_arch_list_add_mem > (addr, 14)) > > - return -1; > > - addr += 14; > > + if (record_arch_list_add_mem > (addr, 14)) > > + return -1; > > + addr += 14; > > } > > if (record_arch_list_add_mem > (addr, 80)) > > return -1; > > + /* FSAVE */ > > + if (i386_record_floats(&ir, > I386_SAVE_FPU_ENV_REG_STACK)) > > + return -1; > > break; > > - case 0x3f: > > + case 0x3f: > > if (record_arch_list_add_mem > (addr, 8)) > > return -1; > > + /* FISTP */ > > + if (i386_record_floats(&ir, > I386_SAVE_FPU_REGS)) > > + return -1; > > break; > > default: > > ir.addr -= 2; > > @@ -4202,9 +4313,180 @@ > > goto no_support; > > break; > > } > > - } > > + } > > + /* opcode is an extension of modR/M byte > */ > > + else > > + { > > + switch (opcode) > > + { > > + case 0xd8: > > + if (i386_record_floats(&ir, > I386_ST0_REGNUM)) > > + return -1; > > + break; > > + case 0xd9: > > + if (0x0c == (ir.modrm >> > 4)) > > + { > > + if ((ir.modrm & 0x0f) > <= 7) > > + { > > + if > (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) > > + return -1; > > + } > > + else > > + { > > + if > (i386_record_floats(&ir, I386_ST0_REGNUM)) > > + return -1; > > + /* if only st(0) is > changing, then we have already recorded */ > > + if ((ir.modrm & > 0x0f) - 0x08) > > + { > > + if > (i386_record_floats(&ir, I386_ST0_REGNUM + ((ir.modrm > & 0x0f) - 0x08))) > > + return -1; > > + } > > + } > > + } > > + else > > + { > > + switch(ir.modrm) > > + { > > + case 0xe0: > > + case 0xe1: > > + case 0xf0: > > + case 0xf5: > > + case 0xf8: > > + case 0xfa: > > + case 0xfc: > > + case 0xfe: > > + case 0xff: > > + if > (i386_record_floats(&ir, I386_ST0_REGNUM)) > > + return -1; > > + break; > > + case 0xf1: > > + case 0xf2: > > + case 0xf3: > > + case 0xf4: > > + case 0xf6: > > + case 0xf7: > > + case 0xe8: > > + case 0xe9: > > + case 0xea: > > + case 0xeb: > > + case 0xec: > > + case 0xed: > > + case 0xee: > > + case 0xf9: > > + case 0xfb: > > + if > (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) > > + return -1; > > + break; > > + case 0xfd: > > + if > (i386_record_floats(&ir, I386_ST0_REGNUM)) > > + return -1; > > + if > (i386_record_floats(&ir, I386_ST1_REGNUM)) > > + return -1; > > + break; > > + } > > + } > > + break; > > + case 0xda: > > + if (0xe9 == ir.modrm) > > + { > > + if (i386_record_floats(&ir, > I386_SAVE_FPU_REGS)) > > + return -1; > > + } > > + else if ((0x0c == ir.modrm > >> 4) || (0x0d == ir.modrm >> 4)) > > + { > > + if > (i386_record_floats(&ir, I386_ST0_REGNUM)) > > + return -1; > > + if (((ir.modrm & 0x0f) > > 0) && ((ir.modrm & 0x0f) <= 7)) > > + { > > + if > (i386_record_floats(&ir, I386_ST0_REGNUM + (ir.modrm > & 0x0f))) > > + return -1; > > + } > > + else if ((ir.modrm & > 0x0f) - 0x08) > > + { > > + if > (i386_record_floats(&ir, I386_ST0_REGNUM + ((ir.modrm > & 0x0f) - 0x08))) > > + return -1; > > + } > > + } > > + break; > > + case 0xdb: > > + if (0xe3 == ir.modrm) > > + { > > + if (i386_record_floats(&ir, > I386_SAVE_FPU_ENV)) > > + return -1; > > + } > > + else if ((0x0c == ir.modrm > >> 4) || (0x0d == ir.modrm >> 4)) > > + { > > + if > (i386_record_floats(&ir, I386_ST0_REGNUM)) > > + return -1; > > + if (((ir.modrm & 0x0f) > > 0) && ((ir.modrm & 0x0f) <= 7)) > > + { > > + if > (i386_record_floats(&ir, I386_ST0_REGNUM + (ir.modrm > & 0x0f))) > > + return -1; > > + } > > + else if ((ir.modrm & > 0x0f) - 0x08) > > + { > > + if > (i386_record_floats(&ir, I386_ST0_REGNUM + ((ir.modrm > & 0x0f) - 0x08))) > > + return -1; > > + } > > + } > > + break; > > + case 0xdc: > > + if ((0x0c == ir.modrm >> > 4) || (0x0d == ir.modrm >> 4) || (0x0f == ir.modrm > >> 4)) > > + { > > + if ((ir.modrm & 0x0f) > <= 7) > > + { > > + if > (i386_record_floats(&ir, I386_ST0_REGNUM + (ir.modrm > & 0x0f))) > > + return -1; > > + } > > + else > > + { > > + if > (i386_record_floats(&ir, I386_ST0_REGNUM + ((ir.modrm > & 0x0f) - 0x08))) > > + return -1; > > + } > > + } > > + break; > > + case 0xdd: > > + if (0x0c == ir.modrm >> > 4) > > + { > > + if > (i386_record_floats(&ir,I386_FTAG)) > > + return -1; > > + } > > + else if ((0x0d == ir.modrm > >> 4) || (0x0e == ir.modrm >> 4)) > > + { > > + if ((ir.modrm & 0x0f) > <= 7) > > + { > > + if > (i386_record_floats(&ir, I386_ST0_REGNUM + (ir.modrm > & 0x0f))) > > + return -1; > > + } > > + else > > + { > > + if > (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) > > + return -1; > > + } > > + } > > + break; > > + case 0xde: > > + if ((0x0c == ir.modrm >> > 4) || (0x0e == ir.modrm >> 4) || (0x0f == ir.modrm > >> 4) || (0xd9 == ir.modrm)) > > + { > > + if > (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) > > + return -1; > > + } > > + break; > > + case 0xdf: > > + if (0xe0 == ir.modrm) > > + { > > + if > (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) > > + return -1; > > + } > > + else if ((0x0f == ir.modrm > >> 4) || (0x0e == ir.modrm >> 4)) > > + { > > + if > (i386_record_floats(&ir, I386_SAVE_FPU_REGS)) > > + return -1; > > + } > > + break; > > + } > > + } > > break; > > - > > /* string ops */ > > /* movsS */ > > case 0xa4: > > @@ -4623,10 +4905,17 @@ > > /* fwait */ > > /* XXX */ > > case 0x9b: > > - printf_unfiltered (_("Process record doesn't > support instruction " > > - "fwait.\n")); > > - ir.addr -= 1; > > - goto no_support; > > + if (target_read_memory (ir.addr, &tmpu8, > 1)) > > + { > > + if (record_debug) > > + printf_unfiltered (_("Process record: > error reading memory at " > > + "addr > 0x%s len = 1.\n"), > > + paddr_nz > (ir.addr)); > > + return -1; > > + } > > + opcode = (uint32_t) tmpu8; > > + ir.addr++; > > + goto reswitch; > > break; > > > > /* int3 */ > > diff -urN gdb.orig/i386-tdep.h gdb.new/i386-tdep.h > > --- gdb.orig/i386-tdep.h 2009-05-17 > 17:56:44.000000000 -0400 > > +++ gdb.new/i386-tdep.h 2009-05-31 16:33:14.000000000 > -0400 > > @@ -145,7 +145,22 @@ > > I386_ES_REGNUM, /* %es */ > > I386_FS_REGNUM, /* %fs */ > > I386_GS_REGNUM, /* %gs */ > > - I386_ST0_REGNUM /* %st(0) */ > > + I386_ST0_REGNUM, /* %st(0) */ > > + I386_ST1_REGNUM, /* %st(1) */ > > + I386_ST2_REGNUM, /* %st(2) */ > > + I386_ST3_REGNUM, /* %st(3) */ > > + I386_ST4_REGNUM, /* %st(4) */ > > + I386_ST5_REGNUM, /* %st(5) */ > > + I386_ST6_REGNUM, /* %st(6) */ > > + I386_ST7_REGNUM, /* %st(7) */ > > + I386_FCTRL, /* floating > point env regs : FCTRL-FOP */ > > + I386_FSTAT, > > + I386_FTAG, > > + I386_FISEG, > > + I386_FIOFF, > > + I386_FOSEG, > > + I386_FOOFF, > > + I386_FOP > > }; > > > > About this part, I think this is my mistake. I didn't > take fp work > for now very clear (Or I am still not clear with x86 fp). > FCTRL, FOP and so on are the fp reg of amd64. For > now, prec is still > not support amd64 (I am working on it). > And amd64's support are in amd64-tedp.... files. > Change i386_regnum > is not a good idea. > > I suggest you divide fp patch to 2 parts. One is for i386, > the other for amd64. > For now, just send i386 patch for review. And send > amd64 patch when > prec support amd64. > > > > > #define I386_NUM_GREGS 16 > > > > > > > > > > > ******************************************************* > > test-example which does basic verification for the > patch. > > > ******************************************************* > > > > #include > > #include > > > > int main() > > { > > float no1,no2,no3,no4,no5,no6,no7; > > double x = 100.345, y = 25.7789; > > long double ldx = 88888888888888888888.88, > ldy = 9999999999999999999.99; > > float result,resultd,resultld; > > no1 = 10.45; > > no2 = 20.77; > > no3 = 156.89874646; > > no4 = 14.56; > > no5 = 11.11; > > no6 = 66.77; > > no7 = 88.88; > > > > result = no1 + no2 + no3 + no4 + no5 + no6 > + no7; > > printf("result is %f\n",result); > > > > result = fmodf(no2,no1); > > printf("result is %f\n",result); > > > > resultd = fmod(x,y); > > printf("result is %f\n",resultd); > > > > resultld = fmodl(ldy,ldy); > > printf("result is %f\n",resultld); > > > > result = fabsf(no1); > > printf("result is %f\n",result); > > > > result = no3 / no4; > > printf("result is %f\n",result); > > > > result = no1 * no2 * no3 * no4; > > printf("result is %f\n",result); > > > > result = sin(30); > > printf("result is %f\n",result); > > > > result = cos(30); > > printf("result is %f\n",result); > > > > result = tan(30); > > printf("result is %f\n",result); > > > > result = atan(30); > > printf("result is %f\n",result); > > > > result = sqrt(no3); > > printf("result is %f\n",result); > > > > result = log10(no3); > > printf("result is %f\n",result); > > > > result = log(no3); > > printf("result is %f\n",result); > > > > result = exp10(no3); > > printf("result is %f\n",result); > > > > result = exp(no3); > > printf("result is %f\n",result); > > > > ldy = 88888888888888888888.88; > > if (ldx == ldy) > > ldy = 7777777777777777777777777777.777; > > else > > ldy = 666666666666666666666666666.666; > > > > } > > With this example, what I got is: > gdb ./a.out > GNU gdb (GDB) 6.8.50.20090602-cvs > Copyright (C) 2009 Free Software Foundation, Inc. > License GPLv3+: GNU GPL version 3 or later > This is free software: you are free to change and > redistribute it. > There is NO WARRANTY, to the extent permitted by law. > Type "show copying" > and "show warranty" for details. > This GDB was configured as "i686-pc-linux-gnu". > For bug reporting instructions, please see: > ... > Setting up the environment for debugging gdb. > Function "internal_error" not defined. > Make breakpoint pending on future shared library load? (y > or [n]) > [answered N; input not from terminal] > Function "info_command" not defined. > Make breakpoint pending on future shared library load? (y > or [n]) > [answered N; input not from terminal] > /home/teawater/gdb/bgdb/gdb/.gdbinit:8: Error in sourced > command file: > No breakpoint number 0. > (gdb) start > During symbol reading, DW_AT_name missing from > DW_TAG_base_type. > Temporary breakpoint 1 at 0x8048608: file 1.c, line 7. > Starting program: /home/teawater/gdb/bgdb/gdb/a.out > > Temporary breakpoint 1, main () at 1.c:7 > 7 double > x = 100.345, y = 25.7789; > (gdb) record > (gdb) c > Continuing. > result is 369.438751 > Process record doesn't support instruction fwait. > Process record doesn't support instruction 0x9b at address > 0xb7fa35fa. > Process record: failed to record execution log. > > Program received signal SIGTRAP, Trace/breakpoint trap. > 0xb7fa35fa in ?? () from /lib/tls/i686/cmov/libm.so.6 > (gdb) > > > Thanks, > Hui > --0-968222875-1243965514=:20508 Content-Type: text/x-patch; name="i386-record-floats.patch" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="i386-record-floats.patch" Content-length: 21899 ZGlmZiAtdXJOIGdkYi5vcmlnL2kzODYtdGRlcC5jIGdkYi5uZXcvaTM4Ni10 ZGVwLmMKLS0tIGdkYi5vcmlnL2kzODYtdGRlcC5jCTIwMDktMDUtMjkgMTc6 MDg6NDAuMDAwMDAwMDAwIC0wNDAwCisrKyBnZGIubmV3L2kzODYtdGRlcC5j CTIwMDktMDYtMDEgMjA6MDI6MjMuMDAwMDAwMDAwIC0wNDAwCkBAIC01NDMs NiArNTQzLDkgQEAKIC8qIFRoZSBtYXhpbXVtIG51bWJlciBvZiBzYXZlZCBy ZWdpc3RlcnMuICBUaGlzIHNob3VsZCBpbmNsdWRlIGFsbAogICAgcmVnaXN0 ZXJzIG1lbnRpb25lZCBhYm92ZSwgYW5kICVlaXAuICAqLwogI2RlZmluZSBJ Mzg2X05VTV9TQVZFRF9SRUdTCUkzODZfTlVNX0dSRUdTCisjZGVmaW5lIEkz ODZfU0FWRV9GUFVfUkVHUwkJMHhGRkZECisjZGVmaW5lIEkzODZfU0FWRV9G UFVfRU5WCQkweEZGRkUKKyNkZWZpbmUgSTM4Nl9TQVZFX0ZQVV9FTlZfUkVH X1NUQUNLCTB4RkZGRgogCiBzdHJ1Y3QgaTM4Nl9mcmFtZV9jYWNoZQogewpA QCAtMjk4NSw2ICsyOTg4LDU0IEBACiAgIHJldHVybiAwOwogfQogCisvKiBS ZWNvcmQgdGhlIHZhbHVlIG9mIGZsb2F0aW5nIHBvaW50IHJlZ2lzdGVycyB3 aGljaCB3aWxsIGJlIGNoYW5nZWQgYnkgdGhlIGN1cnJlbnQgaW5zdHJ1Y3Rp b24KKyAgIHRvICJyZWNvcmRfYXJjaF9saXN0Ii4KKyAgIHJldHVybiAtMSBp ZiBzb21ldGhpbmcgaXMgd3JvbmcuICovICAKKworc3RhdGljIGludCBpMzg2 X3JlY29yZF9mbG9hdHMoc3RydWN0IGkzODZfcmVjb3JkX3MgKmlyLCB1aW50 MzJfdCBpcmVnbnVtKQoreworICBpbnQgaTsKKworICAvKiBPemEgOiBwdXNo L3BvcCBvZiBmcHUgc3RhY2sgaXMgZ29pbmcgdG8gaGFwcGVuIAorICAgICBj dXJyZW50bHkgd2Ugc3RvcmUgc3QwLXN0NyByZWdpc3RlcnMsIGJ1dCB3ZSBu ZWVkIG5vdCBzdG9yZSBhbGwgcmVnaXN0ZXJzIGFsbCB0aGUgdGltZS4KKyAg ICAgdXNpbmcgZnN0YXR1cywgd2UgdXNlIDExLTEzIGJpdHMgd2hpY2ggZ2l2 ZXMgdXMgc3RhY2sgdG9wIGFuZCBoZW5jZSB3ZSBvcHRpbWl6ZSBvdXIgc3Rv cmFnZS4gKi8KKyAgaWYgKEkzODZfU0FWRV9GUFVfUkVHUyA9PSBpcmVnbnVt KQorICAgIHsKKyAgICAgIGZvciAoaT1JMzg2X1NUMF9SRUdOVU07aTw9STM4 Nl9TVDdfUkVHTlVNO2krKykKKyAgICAgICAgeworICAgICAgICAgIGlmIChy ZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLT5yZWdjYWNoZSxpKSkKKyAg ICAgICAgICAgIHJldHVybiAtMTsgICAgCisgICAgICAgIH0KKyAgICB9Cisg IGVsc2UgaWYgKEkzODZfU0FWRV9GUFVfRU5WID09IGlyZWdudW0pCisgICAg eworICAgICAgZm9yIChpPUkzODZfRkNUUkw7aTw9STM4Nl9GT1A7aSsrKQor ICAgICAgeworICAgICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVn IChpci0+cmVnY2FjaGUsaSkpCisgICAgICAgICAgcmV0dXJuIC0xOyAgICAK KyAgICAgIH0KKyAgICB9CisgIGVsc2UgaWYgKEkzODZfU0FWRV9GUFVfRU5W X1JFR19TVEFDSyA9PSBpcmVnbnVtKQorICAgIHsKKyAgICAgIGZvciAoaT1J Mzg2X1NUMF9SRUdOVU07aTw9STM4Nl9GT1A7aSsrKQorICAgICAgeworICAg ICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci0+cmVnY2Fj aGUsaSkpCisgICAgICAgICAgcmV0dXJuIC0xOyAgICAKKyAgICAgIH0KKyAg ICB9CisgIGVsc2UgaWYgKGlyZWdudW0gPj0gSTM4Nl9TVDBfUkVHTlVNICYm IGlyZWdudW0gPD0gSTM4Nl9GT1ApCisgICAgeworICAgICAgaWYgKHJlY29y ZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXItPnJlZ2NhY2hlLGlyZWdudW0pKQor ICAgICAgICByZXR1cm4gLTE7CisgICAgfQorICBlbHNlCisgICAgeworICAg ICAgLyogcGFyYW0gRXJyb3IgKi8KKyAgICAgIHJldHVybiAtMTsKKyAgICB9 IAorICByZXR1cm4gMDsKK30KKwogLyogUGFyc2UgdGhlIGN1cnJlbnQgaW5z dHJ1Y3Rpb24gYW5kIHJlY29yZCB0aGUgdmFsdWVzIG9mIHRoZSByZWdpc3Rl cnMgYW5kCiAgICBtZW1vcnkgdGhhdCB3aWxsIGJlIGNoYW5nZWQgaW4gY3Vy cmVudCBpbnN0cnVjdGlvbiB0byAicmVjb3JkX2FyY2hfbGlzdCIuCiAgICBS ZXR1cm4gLTEgaWYgc29tZXRoaW5nIHdyb25nLiAqLwpAQCAtNDAzNSw3ICs0 MDg2LDYgQEAKICAgICAgIGJyZWFrOwogCiAgICAgICAvKiBmbG9hdHMgKi8K LSAgICAgIC8qIEl0IGp1c3QgcmVjb3JkIHRoZSBtZW1vcnkgY2hhbmdlIG9m IGluc3RyY3V0aW9uLiAqLwogICAgIGNhc2UgMHhkODoKICAgICBjYXNlIDB4 ZDk6CiAgICAgY2FzZSAweGRhOgpAQCAtNDA1NiwzOSArNDEwNiw0OSBAQAog CSAgICByZXR1cm4gLTE7CiAJICBzd2l0Y2ggKGlyLnJlZykKIAkgICAgewot CSAgICBjYXNlIDB4MDA6Ci0JICAgIGNhc2UgMHgwMToKIAkgICAgY2FzZSAw eDAyOgotCSAgICBjYXNlIDB4MDM6CisJICAgIGNhc2UgMHgxMjoKKwkgICAg Y2FzZSAweDIyOgorCSAgICBjYXNlIDB4MzI6CisJICAgICAgLyogZm9yIEZD T00sIEZJQ09NIG5vdGhpbmcgdG8gZG8gKi8KKyAgICAgICAgICAgICAgYnJl YWs7CisgICAgICAgICAgICBjYXNlIDB4MDM6CisJICAgIGNhc2UgMHgxMzoK KwkgICAgY2FzZSAweDIzOgorCSAgICBjYXNlIDB4MzM6CisgIAkgICAgICAv KiBGQ09NUCwgRklDT01QIHBvcCBGUFUgc3RhY2ssIHN0b3JlIGFsbCAqLwor CSAgICAgIGlmIChpMzg2X3JlY29yZF9mbG9hdHMoJmlyLCBJMzg2X1NBVkVf RlBVX1JFR1MpKQorICAgICAgICAgICAgICAgIHJldHVybiAtMTsKKyAgICAg ICAgICAgICAgYnJlYWs7CisJICAgIGNhc2UgMHgwMDoKKyAgICAgICAJICAg IGNhc2UgMHgwMToKIAkgICAgY2FzZSAweDA0OgogCSAgICBjYXNlIDB4MDU6 CiAJICAgIGNhc2UgMHgwNjoKIAkgICAgY2FzZSAweDA3OgogCSAgICBjYXNl IDB4MTA6Ci0JICAgIGNhc2UgMHgxMToKLQkgICAgY2FzZSAweDEyOgotCSAg ICBjYXNlIDB4MTM6CisgICAgICAgCSAgICBjYXNlIDB4MTE6CiAJICAgIGNh c2UgMHgxNDoKIAkgICAgY2FzZSAweDE1OgogCSAgICBjYXNlIDB4MTY6CiAJ ICAgIGNhc2UgMHgxNzoKIAkgICAgY2FzZSAweDIwOgogCSAgICBjYXNlIDB4 MjE6Ci0JICAgIGNhc2UgMHgyMjoKLQkgICAgY2FzZSAweDIzOgogCSAgICBj YXNlIDB4MjQ6CiAJICAgIGNhc2UgMHgyNToKIAkgICAgY2FzZSAweDI2Ogog CSAgICBjYXNlIDB4Mjc6CiAJICAgIGNhc2UgMHgzMDoKIAkgICAgY2FzZSAw eDMxOgotCSAgICBjYXNlIDB4MzI6Ci0JICAgIGNhc2UgMHgzMzoKIAkgICAg Y2FzZSAweDM0OgogCSAgICBjYXNlIDB4MzU6CiAJICAgIGNhc2UgMHgzNjoK IAkgICAgY2FzZSAweDM3OgotCSAgICAgIGJyZWFrOworCSAgICAgIC8qIEZB REQsIEZNVUwsIEZTVUIsIEZTVUJSLCBGRElWLCBGRElWUiwgRklBREQsIEZJ TVVMLCBGSVNVQiwgRklTVUJSLCBGSURJViwgRklESVZSICAKKyAgICAgICAg ICAgICAgTW9kUi9NLnJlZyBpcyBhbiBleHRlbnNpb24gb2YgY29kZSwgYWx3 YXlzIGFmZmVjdHMgc3QoMCkgcmVnaXN0ZXIgKi8KKwkgICAgICBpZiAoaTM4 Nl9yZWNvcmRfZmxvYXRzKCZpciwgSTM4Nl9TVDBfUkVHTlVNKSkKKyAgICAg ICAgICAgICAgICByZXR1cm4gLTE7CisgICAgICAgICAgICAgIGJyZWFrOyAg ICAgICAgICAgCSAgICAJICAgIAogCSAgICBjYXNlIDB4MDg6CiAJICAgIGNh c2UgMHgwYToKIAkgICAgY2FzZSAweDBiOgpAQCAtNDA5Niw2ICs0MTU2LDcg QEAKIAkgICAgY2FzZSAweDE5OgogCSAgICBjYXNlIDB4MWE6CiAJICAgIGNh c2UgMHgxYjoKKwkgICAgY2FzZSAweDFkOiAKIAkgICAgY2FzZSAweDI4Ogog CSAgICBjYXNlIDB4Mjk6CiAJICAgIGNhc2UgMHgyYToKQEAgLTQxMDMsMTEg KzQxNjQsMTYgQEAKIAkgICAgY2FzZSAweDM4OgogCSAgICBjYXNlIDB4Mzk6 CiAJICAgIGNhc2UgMHgzYToKLQkgICAgY2FzZSAweDNiOgorCSAgICBjYXNl IDB4M2I6CSAgIAorCSAgICBjYXNlIDB4M2M6IAorCSAgICBjYXNlIDB4M2Q6 IAogCSAgICAgIHN3aXRjaCAoaXIucmVnICYgNykKIAkJewogCQljYXNlIDA6 Ci0JCSAgYnJlYWs7CisJCSAgLyogRkxELCBGSUxEICovCisJICAgICAgICAg IGlmIChpMzg2X3JlY29yZF9mbG9hdHMoJmlyLCBJMzg2X1NBVkVfRlBVX1JF R1MpKQorICAgICAgICAgICAgICAgICAgICByZXR1cm4gLTE7ICAgIAorICAg ICAgICAgICAgICAgICAgYnJlYWs7CiAJCWNhc2UgMToKIAkJICBzd2l0Y2gg KGlyLnJlZyA+PiA0KQogCQkgICAgewpAQCAtNDEyMCw2ICs0MTg2LDcgQEAK IAkJCXJldHVybiAtMTsKIAkJICAgICAgYnJlYWs7CiAJCSAgICBjYXNlIDM6 CisJCSAgICAgIGJyZWFrOwogCQkgICAgZGVmYXVsdDoKIAkJICAgICAgaWYg KHJlY29yZF9hcmNoX2xpc3RfYWRkX21lbSAoYWRkciwgMikpCiAJCQlyZXR1 cm4gLTE7CkBAIC00MTMwLDE1ICs0MTk3LDQyIEBACiAJCSAgc3dpdGNoIChp ci5yZWcgPj4gNCkKIAkJICAgIHsKIAkJICAgIGNhc2UgMDoKKwkJICAgICAg aWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX21lbSAoYWRkciwgNCkpCisJCQly ZXR1cm4gLTE7CisJCSAgICAgIGlmICgzID09IChpci5yZWcgJiA3KSkKKyAg ICAgICAgICAgICAgICAgICAgICAgIHsKKyAgICAgICAgICAgICAgICAgICAg ICAgIC8qIEZTVFAgbTMyZnAgKi8KKwkJICAgICAgICBpZiAoaTM4Nl9yZWNv cmRfZmxvYXRzKCZpciwgSTM4Nl9TQVZFX0ZQVV9SRUdTKSkKKwkJICAgICAg ICAgIHJldHVybiAtMTsgICAgICAgICAgICAgICAgICAgICAgICAKKyAgICAg ICAgICAgICAgICAgICAgICAgIH0gCisgICAgICAgICAgICAgICAgICAgICAg YnJlYWs7CiAJCSAgICBjYXNlIDE6CiAJCSAgICAgIGlmIChyZWNvcmRfYXJj aF9saXN0X2FkZF9tZW0gKGFkZHIsIDQpKQogCQkJcmV0dXJuIC0xOworCQkg ICAgICBpZiAoKDMgPT0gKGlyLnJlZyAmIDcpKSB8fCAoNSA9PSAoaXIucmVn ICYgNykpIHx8ICg3ID09IChpci5yZWcgJiA3KSkpCisgICAgICAgICAgICAg ICAgICAgICAgICB7CisgICAgICAgICAgICAgICAgICAgICAgICAvKiBGU1RQ ICovCisJCSAgICAgICAgaWYgKGkzODZfcmVjb3JkX2Zsb2F0cygmaXIsIEkz ODZfU0FWRV9GUFVfUkVHUykpCisJCSAgICAgICAgICByZXR1cm4gLTE7ICAg ICAgICAgICAgICAgICAgICAgICAgCisgICAgICAgICAgICAgICAgICAgICAg ICB9IAogCQkgICAgICBicmVhazsKIAkJICAgIGNhc2UgMjoKIAkJICAgICAg aWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX21lbSAoYWRkciwgOCkpCiAJCQly ZXR1cm4gLTE7CisJCSAgICAgIGlmICgzID09IChpci5yZWcgJiA3KSkKKyAg ICAgICAgICAgICAgICAgICAgICAgIHsKKyAgICAgICAgICAgICAgICAgICAg ICAgIC8qIEZTVFAgbTY0ZnAgKi8KKwkJICAgICAgICBpZiAoaTM4Nl9yZWNv cmRfZmxvYXRzKCZpciwgSTM4Nl9TQVZFX0ZQVV9SRUdTKSkKKwkJICAgICAg ICAgIHJldHVybiAtMTsgICAgICAgICAgICAgICAgICAgICAgICAKKyAgICAg ICAgICAgICAgICAgICAgICAgIH0gCiAJCSAgICAgIGJyZWFrOwogCQkgICAg Y2FzZSAzOgorCQkgICAgICBpZiAoKDMgPD0gKGlyLnJlZyAmIDcpKSAmJiAo NiA8PSAoaXIucmVnICYgNykpKQorICAgICAgICAgICAgICAgICAgICAgICAg eworICAgICAgICAgICAgICAgICAgICAgICAgLyogRklTVFAsIEZCTEQsIEZJ TEQsIEZCU1RQICovCisJCSAgICAgICAgaWYgKGkzODZfcmVjb3JkX2Zsb2F0 cygmaXIsIEkzODZfU0FWRV9GUFVfUkVHUykpCisJCSAgICAgICAgICByZXR1 cm4gLTE7ICAgICAgICAgICAgICAgICAgICAgICAgCisgICAgICAgICAgICAg ICAgICAgICAgICB9ICAgICAgICAgICAgICAgICAgICAgICAgCiAJCSAgICBk ZWZhdWx0OgogCQkgICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfbWVt IChhZGRyLCAyKSkKIAkJCXJldHVybiAtMTsKQEAgLTQxNDcsNTQgKzQyNDEs NzEgQEAKIAkJICBicmVhazsKIAkJfQogCSAgICAgIGJyZWFrOwotCSAgICBj YXNlIDB4MGM6Ci0JICAgIGNhc2UgMHgwZDoKLQkgICAgY2FzZSAweDFkOgot CSAgICBjYXNlIDB4MmM6Ci0JICAgIGNhc2UgMHgzYzoKLQkgICAgY2FzZSAw eDNkOgotCSAgICAgIGJyZWFrOwotCSAgICBjYXNlIDB4MGU6CisgICAJICAg IGNhc2UgMHgwYzoKKwkgICAgICAvKiBGTERFTlYgKi8KKwkgICAgICBpZiAo aTM4Nl9yZWNvcmRfZmxvYXRzKCZpciwgSTM4Nl9TQVZFX0ZQVV9FTlZfUkVH X1NUQUNLKSkKKwkgICAgICAgIHJldHVybiAtMTsgIAorICAgICAgICAgICAg ICBicmVhazsKKwkgICAgY2FzZSAweDBkOiAKKyAgICAgICAgICAgICAgLyog RkxEQ1cgKi8KKwkgICAgICBpZiAoaTM4Nl9yZWNvcmRfZmxvYXRzKCZpciwg STM4Nl9GQ1RSTCkpCisJICAgICAgICByZXR1cm4gLTE7ICAKKyAgICAgICAg ICAgICAgYnJlYWs7CisJICAgIGNhc2UgMHgyYzogCisgICAgICAgICAgICAg IC8qIEZSVFNUT1IgKi8KKwkgICAgICBpZiAoaTM4Nl9yZWNvcmRfZmxvYXRz KCZpciwgSTM4Nl9TQVZFX0ZQVV9FTlZfUkVHX1NUQUNLKSkKKwkgICAgICAg IHJldHVybiAtMTsgIAorCSAgICAgIGJyZWFrOyAKKwkgICAgY2FzZSAweDBl OiAKIAkgICAgICBpZiAoaXIuZGZsYWcpCiAJCXsKLQkJICBpZiAocmVjb3Jk X2FyY2hfbGlzdF9hZGRfbWVtIChhZGRyLCAyOCkpCi0JCSAgICByZXR1cm4g LTE7CisJCWlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9tZW0gKGFkZHIsIDI4 KSkKKwkJICByZXR1cm4gLTE7CiAJCX0KIAkgICAgICBlbHNlCiAJCXsKLQkJ ICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfbWVtIChhZGRyLCAxNCkpCi0J CSAgICByZXR1cm4gLTE7CisJCWlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9t ZW0gKGFkZHIsIDE0KSkKKwkJICByZXR1cm4gLTE7CiAJCX0KIAkgICAgICBi cmVhazsKLQkgICAgY2FzZSAweDBmOgotCSAgICBjYXNlIDB4MmY6CisJICAg IGNhc2UgMHgwZjogIAorCSAgICBjYXNlIDB4MmY6ICAKIAkgICAgICBpZiAo cmVjb3JkX2FyY2hfbGlzdF9hZGRfbWVtIChhZGRyLCAyKSkKIAkJcmV0dXJu IC0xOwogCSAgICAgIGJyZWFrOwotCSAgICBjYXNlIDB4MWY6Ci0JICAgIGNh c2UgMHgzZToKKwkgICAgY2FzZSAweDFmOiAgCisJICAgIGNhc2UgMHgzZTog IAogCSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9tZW0gKGFkZHIs IDEwKSkKIAkJcmV0dXJuIC0xOworICAgICAgICAgICAgICAvKiBGU1RQLCBG QlNUUCAqLworICAgICAgICAgICAgICBpZiAoaTM4Nl9yZWNvcmRfZmxvYXRz KCZpciwgSTM4Nl9TQVZFX0ZQVV9SRUdTKSkKKwkgICAgICAgIHJldHVybiAt MTsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgCiAJICAgICAg YnJlYWs7Ci0JICAgIGNhc2UgMHgyZToKKwkgICAgY2FzZSAweDJlOiAKIAkg ICAgICBpZiAoaXIuZGZsYWcpCiAJCXsKLQkJICBpZiAocmVjb3JkX2FyY2hf bGlzdF9hZGRfbWVtIChhZGRyLCAyOCkpCi0JCSAgICByZXR1cm4gLTE7Ci0J CSAgYWRkciArPSAyODsKKwkJaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX21l bSAoYWRkciwgMjgpKQorCQkgIHJldHVybiAtMTsKKwkJYWRkciArPSAyODsK IAkJfQogCSAgICAgIGVsc2UKIAkJewotCQkgIGlmIChyZWNvcmRfYXJjaF9s aXN0X2FkZF9tZW0gKGFkZHIsIDE0KSkKLQkJICAgIHJldHVybiAtMTsKLQkJ ICBhZGRyICs9IDE0OworCQlpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfbWVt IChhZGRyLCAxNCkpCisJCSAgcmV0dXJuIC0xOworCQlhZGRyICs9IDE0Owog CQl9CiAJICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX21lbSAoYWRk ciwgODApKQogCQlyZXR1cm4gLTE7CisgICAgICAgICAgICAgIC8qIEZTQVZF ICovCisJICAgICAgaWYgKGkzODZfcmVjb3JkX2Zsb2F0cygmaXIsIEkzODZf U0FWRV9GUFVfRU5WX1JFR19TVEFDSykpCisJICAgICAgICByZXR1cm4gLTE7 ICAgCiAJICAgICAgYnJlYWs7Ci0JICAgIGNhc2UgMHgzZjoKKwkgICAgY2Fz ZSAweDNmOiAKIAkgICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfbWVt IChhZGRyLCA4KSkKIAkJcmV0dXJuIC0xOworCQkvKiBGSVNUUCAqLworICAg ICAgICAgICAgICBpZiAoaTM4Nl9yZWNvcmRfZmxvYXRzKCZpciwgSTM4Nl9T QVZFX0ZQVV9SRUdTKSkKKwkgICAgICAgIHJldHVybiAtMTsgICAKIAkgICAg ICBicmVhazsKIAkgICAgZGVmYXVsdDoKIAkgICAgICBpci5hZGRyIC09IDI7 CkBAIC00MjAyLDkgKzQzMTMsMTgwIEBACiAJICAgICAgZ290byBub19zdXBw b3J0OwogCSAgICAgIGJyZWFrOwogCSAgICB9Ci0JfQorCX0gICAKKyAgICAg ICAgLyogb3Bjb2RlIGlzIGFuIGV4dGVuc2lvbiBvZiBtb2RSL00gYnl0ZSAq LyAgICAgCisJZWxzZQorCXsgCisgICAgICAgICAgc3dpdGNoIChvcGNvZGUp CisgICAgICAgICAgICB7CisgICAgICAgICAgICBjYXNlIDB4ZDg6CisgICAg ICAgICAgICAgIGlmIChpMzg2X3JlY29yZF9mbG9hdHMoJmlyLCBJMzg2X1NU MF9SRUdOVU0pKQorICAgICAgICAgICAgICAgIHJldHVybiAtMTsJCisgICAg ICAgICAgICAgIGJyZWFrOworICAgICAgICAgICAgY2FzZSAweGQ5OiAgICAK KyAgICAgICAgICAgICAgaWYgKDB4MGMgPT0gKGlyLm1vZHJtID4+IDQpKQor ICAgICAgICAgICAgICAgIHsKKyAgICAgICAgICAgICAgICAgIGlmICgoaXIu bW9kcm0gJiAweDBmKSA8PSA3KQorICAgICAgICAgICAgICAgICAgICB7Cisg ICAgICAgICAgICAgICAgICAgIGlmIChpMzg2X3JlY29yZF9mbG9hdHMoJmly LCBJMzg2X1NBVkVfRlBVX1JFR1MpKQorICAgICAgICAgICAgICAgICAgICAg IHJldHVybiAtMTsJCisgICAgICAgICAgICAgICAgICAgIH0KKyAgICAgICAg ICAgICAgICAgIGVsc2UKKyAgICAgICAgICAgICAgICAgICAgeworICAgICAg ICAgICAgICAgICAgICBpZiAoaTM4Nl9yZWNvcmRfZmxvYXRzKCZpciwgSTM4 Nl9TVDBfUkVHTlVNKSkKKyAgICAgICAgICAgICAgICAgICAgICByZXR1cm4g LTE7CQorICAgICAgICAgICAgICAgICAgICAvKiBpZiBvbmx5IHN0KDApIGlz IGNoYW5naW5nLCB0aGVuIHdlIGhhdmUgYWxyZWFkeSByZWNvcmRlZCAqLwor ICAgICAgICAgICAgICAgICAgICBpZiAoKGlyLm1vZHJtICYgMHgwZikgLSAw eDA4KQorICAgICAgICAgICAgICAgICAgICAgIHsKKyAgICAgICAgICAgICAg ICAgICAgICBpZiAoaTM4Nl9yZWNvcmRfZmxvYXRzKCZpciwgSTM4Nl9TVDBf UkVHTlVNICsgKChpci5tb2RybSAmIDB4MGYpIC0gMHgwOCkpKQorICAgICAg ICAgICAgICAgICAgICAgICAgcmV0dXJuIC0xOwkgICAgICAgICAgICAgICAg ICAgICAgCisgICAgICAgICAgICAgICAgICAgICAgfSAKKyAgICAgICAgICAg ICAgICAgICAgfSAgCisgICAgICAgICAgICAgICAgfQorICAgICAgICAgICAg ICBlbHNlCisgICAgICAgICAgICAgICAgeworICAgICAgICAgICAgICAgIHN3 aXRjaChpci5tb2RybSkKKyAgICAgICAgICAgICAgICAgIHsKKyAgICAgICAg ICAgICAgICAgIGNhc2UgMHhlMDoKKyAgICAgICAgICAgICAgICAgIGNhc2Ug MHhlMToKKyAgICAgICAgICAgICAgICAgIGNhc2UgMHhmMDoKKyAgICAgICAg ICAgICAgICAgIGNhc2UgMHhmNToKKyAgICAgICAgICAgICAgICAgIGNhc2Ug MHhmODoKKyAgICAgICAgICAgICAgICAgIGNhc2UgMHhmYToKKyAgICAgICAg ICAgICAgICAgIGNhc2UgMHhmYzoKKyAgICAgICAgICAgICAgICAgIGNhc2Ug MHhmZToKKyAgICAgICAgICAgICAgICAgIGNhc2UgMHhmZjoKKyAgICAgICAg ICAgICAgICAgICAgaWYgKGkzODZfcmVjb3JkX2Zsb2F0cygmaXIsIEkzODZf U1QwX1JFR05VTSkpCisgICAgICAgICAgICAgICAgICAgICAgcmV0dXJuIC0x OworICAgICAgICAgICAgICAgICAgICBicmVhazsgICAgICAgICAgIAorICAg ICAgICAgICAgICAgICAgY2FzZSAweGYxOiAgCisgICAgICAgICAgICAgICAg ICBjYXNlIDB4ZjI6ICAKKyAgICAgICAgICAgICAgICAgIGNhc2UgMHhmMzog IAorICAgICAgICAgICAgICAgICAgY2FzZSAweGY0OgorICAgICAgICAgICAg ICAgICAgY2FzZSAweGY2OiAgICAgICAgCisgICAgICAgICAgICAgICAgICBj YXNlIDB4Zjc6ICAgIAorICAgICAgICAgICAgICAgICAgY2FzZSAweGU4OiAg CisgICAgICAgICAgICAgICAgICBjYXNlIDB4ZTk6ICAKKyAgICAgICAgICAg ICAgICAgIGNhc2UgMHhlYTogIAorICAgICAgICAgICAgICAgICAgY2FzZSAw eGViOgorICAgICAgICAgICAgICAgICAgY2FzZSAweGVjOiAgICAgICAgCisg ICAgICAgICAgICAgICAgICBjYXNlIDB4ZWQ6ICAgIAorICAgICAgICAgICAg ICAgICAgY2FzZSAweGVlOiAgIAorICAgICAgICAgICAgICAgICAgY2FzZSAw eGY5OiAgICAgCisgICAgICAgICAgICAgICAgICBjYXNlIDB4ZmI6CisgICAg ICAgICAgICAgICAgICAgIGlmIChpMzg2X3JlY29yZF9mbG9hdHMoJmlyLCBJ Mzg2X1NBVkVfRlBVX1JFR1MpKQorICAgICAgICAgICAgICAgICAgICAgIHJl dHVybiAtMTsJCisgICAgICAgICAgICAgICAgICAgIGJyZWFrOworICAgICAg ICAgICAgICAgICAgY2FzZSAweGZkOiAKKyAgICAgICAgICAgICAgICAgICAg aWYgKGkzODZfcmVjb3JkX2Zsb2F0cygmaXIsIEkzODZfU1QwX1JFR05VTSkp CisgICAgICAgICAgICAgICAgICAgICAgcmV0dXJuIC0xOworICAgICAgICAg ICAgICAgICAgICBpZiAoaTM4Nl9yZWNvcmRfZmxvYXRzKCZpciwgSTM4Nl9T VDFfUkVHTlVNKSkKKyAgICAgICAgICAgICAgICAgICAgICByZXR1cm4gLTE7 CisgICAgICAgICAgICAgICAgICAgIGJyZWFrOworICAgICAgICAgICAgICAg ICAgfSAKKyAgICAgICAgICAgICAgfQorICAgICAgICAgICAgICBicmVhazsK KyAgICAgICAgICAgIGNhc2UgMHhkYToKKyAgICAgICAgICAgICAgaWYgKDB4 ZTkgPT0gaXIubW9kcm0pCisgICAgICAgICAgICAgICAgeworCQlpZiAoaTM4 Nl9yZWNvcmRfZmxvYXRzKCZpciwgSTM4Nl9TQVZFX0ZQVV9SRUdTKSkKKyAg ICAgICAgICAgICAgICAgIHJldHVybiAtMTsgICAgICAgICAgICAgICAgICAg IAorICAgICAgICAgICAgICAgIH0KKyAgICAgICAgICAgICAgZWxzZSBpZiAo KDB4MGMgPT0gaXIubW9kcm0gPj4gNCkgfHwgKDB4MGQgPT0gaXIubW9kcm0g Pj4gNCkpCisgICAgICAgICAgICAgICAgeworICAgICAgICAgICAgICAgIGlm IChpMzg2X3JlY29yZF9mbG9hdHMoJmlyLCBJMzg2X1NUMF9SRUdOVU0pKQor ICAgICAgICAgICAgICAgICAgcmV0dXJuIC0xOwkgICAgICAgICAgICAgICAg CisgICAgICAgICAgICAgICAgaWYgKCgoaXIubW9kcm0gJiAweDBmKSA+IDAp ICYmICgoaXIubW9kcm0gJiAweDBmKSA8PSA3KSkKKyAgICAgICAgICAgICAg ICAgIHsKKyAgICAgICAgICAgICAgICAgIGlmIChpMzg2X3JlY29yZF9mbG9h dHMoJmlyLCBJMzg2X1NUMF9SRUdOVU0gKyAoaXIubW9kcm0gJiAweDBmKSkp CisgICAgICAgICAgICAgICAgICAgIHJldHVybiAtMTsJICAgICAgICAgICAg ICAgICAgICAgIAorICAgICAgICAgICAgICAgICAgfQorICAgICAgICAgICAg ICAgIGVsc2UgaWYgKChpci5tb2RybSAmIDB4MGYpIC0gMHgwOCkKKyAgICAg ICAgICAgICAgICAgIHsKKwkJICBpZiAoaTM4Nl9yZWNvcmRfZmxvYXRzKCZp ciwgSTM4Nl9TVDBfUkVHTlVNICsgKChpci5tb2RybSAmIDB4MGYpIC0gMHgw OCkpKQorICAgICAgICAgICAgICAgICAgICByZXR1cm4gLTE7CisgICAgICAg ICAgICAgICAgICB9CisgICAgICAgICAgICAgICAgfSAgCisgICAgICAgICAg ICAgIGJyZWFrOyAKKyAgICAgICAgICAgIGNhc2UgMHhkYjoKKyAgICAgICAg ICAgICAgaWYgKDB4ZTMgPT0gaXIubW9kcm0pCisgICAgICAgICAgICAgICAg eworCQlpZiAoaTM4Nl9yZWNvcmRfZmxvYXRzKCZpciwgSTM4Nl9TQVZFX0ZQ VV9FTlYpKQorICAgICAgICAgICAgICAgICAgcmV0dXJuIC0xOyAgICAgICAg ICAgICAgICAgICAgCisgICAgICAgICAgICAgICAgfQorICAgICAgICAgICAg ICBlbHNlIGlmICgoMHgwYyA9PSBpci5tb2RybSA+PiA0KSB8fCAoMHgwZCA9 PSBpci5tb2RybSA+PiA0KSkKKyAgICAgICAgICAgICAgICB7CisgICAgICAg ICAgICAgICAgaWYgKGkzODZfcmVjb3JkX2Zsb2F0cygmaXIsIEkzODZfU1Qw X1JFR05VTSkpCisgICAgICAgICAgICAgICAgICByZXR1cm4gLTE7CSAgICAg ICAgICAgICAgICAKKyAgICAgICAgICAgICAgICBpZiAoKChpci5tb2RybSAm IDB4MGYpID4gMCkgJiYgKChpci5tb2RybSAmIDB4MGYpIDw9IDcpKQorICAg ICAgICAgICAgICAgICAgeworICAgICAgICAgICAgICAgICAgaWYgKGkzODZf cmVjb3JkX2Zsb2F0cygmaXIsIEkzODZfU1QwX1JFR05VTSArIChpci5tb2Ry bSAmIDB4MGYpKSkKKyAgICAgICAgICAgICAgICAgICAgcmV0dXJuIC0xOwkg ICAgICAgICAgICAgICAgICAgICAgCisgICAgICAgICAgICAgICAgICB9Cisg ICAgICAgICAgICAgICAgZWxzZSBpZiAoKGlyLm1vZHJtICYgMHgwZikgLSAw eDA4KQorICAgICAgICAgICAgICAgICAgeworCQkgIGlmIChpMzg2X3JlY29y ZF9mbG9hdHMoJmlyLCBJMzg2X1NUMF9SRUdOVU0gKyAoKGlyLm1vZHJtICYg MHgwZikgLSAweDA4KSkpCisgICAgICAgICAgICAgICAgICAgIHJldHVybiAt MTsKKyAgICAgICAgICAgICAgICAgIH0KKyAgICAgICAgICAgICAgICB9ICAK KyAgICAgICAgICAgICAgYnJlYWs7CisgICAgICAgICAgICBjYXNlIDB4ZGM6 CisgICAgICAgICAgICAgIGlmICgoMHgwYyA9PSBpci5tb2RybSA+PiA0KSB8 fCAoMHgwZCA9PSBpci5tb2RybSA+PiA0KSB8fCAoMHgwZiA9PSBpci5tb2Ry bSA+PiA0KSkKKyAgICAgICAgICAgICAgICB7CisgICAgICAgICAgICAgICAg aWYgKChpci5tb2RybSAmIDB4MGYpIDw9IDcpCisgICAgICAgICAgICAgICAg ICB7CisgICAgICAgICAgICAgICAgICBpZiAoaTM4Nl9yZWNvcmRfZmxvYXRz KCZpciwgSTM4Nl9TVDBfUkVHTlVNICsgKGlyLm1vZHJtICYgMHgwZikpKQor ICAgICAgICAgICAgICAgICAgICByZXR1cm4gLTE7CSAgICAgICAgICAgICAg ICAgICAgICAKKyAgICAgICAgICAgICAgICAgIH0KKyAgICAgICAgICAgICAg ICBlbHNlCisgICAgICAgICAgICAgICAgICB7CisJCSAgaWYgKGkzODZfcmVj b3JkX2Zsb2F0cygmaXIsIEkzODZfU1QwX1JFR05VTSArICgoaXIubW9kcm0g JiAweDBmKSAtIDB4MDgpKSkKKyAgICAgICAgICAgICAgICAgICAgcmV0dXJu IC0xOworICAgICAgICAgICAgICAgICAgfQorICAgICAgICAgICAgICAgIH0g IAorICAgICAgICAgICAgICAgYnJlYWs7CisgICAgICAgICAgICBjYXNlIDB4 ZGQ6ICAgICAgICAgICAgIAorICAgICAgICAgICAgICBpZiAoMHgwYyA9PSBp ci5tb2RybSA+PiA0KQorICAgICAgICAgICAgICAgIHsKKyAgICAgICAgICAg ICAgICAgIGlmIChpMzg2X3JlY29yZF9mbG9hdHMoJmlyLEkzODZfRlRBRykp CisgICAgICAgICAgICAgICAgICAgIHJldHVybiAtMTsKKyAgICAgICAgICAg ICAgICB9CisgICAgICAgICAgICAgIGVsc2UgaWYgKCgweDBkID09IGlyLm1v ZHJtID4+IDQpIHx8ICgweDBlID09IGlyLm1vZHJtID4+IDQpKQorICAgICAg ICAgICAgICAgIHsgCisgICAgICAgICAgICAgICAgICBpZiAoKGlyLm1vZHJt ICYgMHgwZikgPD0gNykKKyAgICAgICAgICAgICAgICAgICAgeworICAgICAg ICAgICAgICAgICAgICAgIGlmIChpMzg2X3JlY29yZF9mbG9hdHMoJmlyLCBJ Mzg2X1NUMF9SRUdOVU0gKyAoaXIubW9kcm0gJiAweDBmKSkpCisgICAgICAg ICAgICAgICAgICAgICAgICByZXR1cm4gLTE7CSAKKyAgICAgICAgICAgICAg ICAgICAgfQorICAgICAgICAgICAgICAgICAgZWxzZQorICAgICAgICAgICAg ICAgICAgICB7CisgICAgICAgICAgICAgICAgICAgICAgaWYgKGkzODZfcmVj b3JkX2Zsb2F0cygmaXIsIEkzODZfU0FWRV9GUFVfUkVHUykpCisgICAgICAg ICAgICAgICAgICAgICAgICByZXR1cm4gLTE7CisgICAgICAgICAgICAgICAg ICAgIH0KKyAgICAgICAgICAgICAgICB9ICAgICAgICAgICAgCisgICAgICAg ICAgICAgIGJyZWFrOworICAgICAgICAgICAgY2FzZSAweGRlOgorICAgICAg ICAgICAgICBpZiAoKDB4MGMgPT0gaXIubW9kcm0gPj4gNCkgfHwgKDB4MGUg PT0gaXIubW9kcm0gPj4gNCkgfHwgKDB4MGYgPT0gaXIubW9kcm0gPj4gNCkg fHwgKDB4ZDkgPT0gaXIubW9kcm0pKQorICAgICAgICAgICAgICAgIHsgICAg ICAgICAgICAgICAgICAgCisgICAgICAgICAgICAgICAgICBpZiAoaTM4Nl9y ZWNvcmRfZmxvYXRzKCZpciwgSTM4Nl9TQVZFX0ZQVV9SRUdTKSkKKyAgICAg ICAgICAgICAgICAgICAgcmV0dXJuIC0xOwkgCisgICAgICAgICAgICAgICAg fSAgIAorICAgICAgICAgICAgICBicmVhazsKKyAgICAgICAgICAgIGNhc2Ug MHhkZjoKKwkgICAgICBpZiAoMHhlMCA9PSBpci5tb2RybSkKKyAgICAgICAg ICAgICAgICB7CisgICAgICAgICAgICAgICAgICBpZiAocmVjb3JkX2FyY2hf bGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4Nl9FQVhfUkVHTlVNKSkK KwkgICAJICAgIHJldHVybiAtMTsKKyAgICAgICAgICAgICAgICB9CisgICAg ICAgICAgICAgIGVsc2UgaWYgKCgweDBmID09IGlyLm1vZHJtID4+IDQpIHx8 ICgweDBlID09IGlyLm1vZHJtID4+IDQpKQorICAgICAgICAgICAgICAgIHsg CisgICAgICAgICAgICAgICAgICBpZiAoaTM4Nl9yZWNvcmRfZmxvYXRzKCZp ciwgSTM4Nl9TQVZFX0ZQVV9SRUdTKSkKKyAgICAgICAgICAgICAgICAgICAg cmV0dXJuIC0xOworICAgICAgICAgICAgICAgIH0gCisgICAgICAgICAgICAg IGJyZWFrOworICAgICAgICAgICAgfSAJICAKKyAgICAgICAgfSAgICAgICAg IAogICAgICAgYnJlYWs7Ci0KICAgICAgIC8qIHN0cmluZyBvcHMgKi8KICAg ICAgIC8qIG1vdnNTICovCiAgICAgY2FzZSAweGE0OgpAQCAtNDYyMywxMCAr NDkwNSwxNyBAQAogICAgICAgLyogZndhaXQgKi8KICAgICAgIC8qIFhYWCAq LwogICAgIGNhc2UgMHg5YjoKLSAgICAgIHByaW50Zl91bmZpbHRlcmVkIChf KCJQcm9jZXNzIHJlY29yZCBkb2Vzbid0IHN1cHBvcnQgaW5zdHJ1Y3Rpb24g IgotCQkJICAgImZ3YWl0LlxuIikpOwotICAgICAgaXIuYWRkciAtPSAxOwot ICAgICAgZ290byBub19zdXBwb3J0OworICAgICAgaWYgKHRhcmdldF9yZWFk X21lbW9yeSAoaXIuYWRkciwgJnRtcHU4LCAxKSkKKwl7CisJICBpZiAocmVj b3JkX2RlYnVnKQorCSAgICBwcmludGZfdW5maWx0ZXJlZCAoXygiUHJvY2Vz cyByZWNvcmQ6IGVycm9yIHJlYWRpbmcgbWVtb3J5IGF0ICIKKwkJCQkgImFk ZHIgMHglcyBsZW4gPSAxLlxuIiksCisJCQkgICAgICAgcGFkZHJfbnogKGly LmFkZHIpKTsKKwkgIHJldHVybiAtMTsKKwl9CisgICAgICBvcGNvZGUgPSAo dWludDMyX3QpIHRtcHU4OworICAgICAgaXIuYWRkcisrOworICAgICAgZ290 byByZXN3aXRjaDsgICAgIAogICAgICAgYnJlYWs7CiAKICAgICAgIC8qIGlu dDMgKi8KZGlmZiAtdXJOIGdkYi5vcmlnL2kzODYtdGRlcC5oIGdkYi5uZXcv aTM4Ni10ZGVwLmgKLS0tIGdkYi5vcmlnL2kzODYtdGRlcC5oCTIwMDktMDUt MTcgMTc6NTY6NDQuMDAwMDAwMDAwIC0wNDAwCisrKyBnZGIubmV3L2kzODYt dGRlcC5oCTIwMDktMDUtMzEgMTY6MzM6MTQuMDAwMDAwMDAwIC0wNDAwCkBA IC0xNDUsNyArMTQ1LDIyIEBACiAgIEkzODZfRVNfUkVHTlVNLAkJLyogJWVz ICovCiAgIEkzODZfRlNfUkVHTlVNLAkJLyogJWZzICovCiAgIEkzODZfR1Nf UkVHTlVNLAkJLyogJWdzICovCi0gIEkzODZfU1QwX1JFR05VTQkJLyogJXN0 KDApICovCisgIEkzODZfU1QwX1JFR05VTSwJCS8qICVzdCgwKSAqLworICBJ Mzg2X1NUMV9SRUdOVU0sCQkvKiAlc3QoMSkgKi8KKyAgSTM4Nl9TVDJfUkVH TlVNLAkJLyogJXN0KDIpICovCisgIEkzODZfU1QzX1JFR05VTSwJCS8qICVz dCgzKSAqLworICBJMzg2X1NUNF9SRUdOVU0sCQkvKiAlc3QoNCkgKi8KKyAg STM4Nl9TVDVfUkVHTlVNLAkJLyogJXN0KDUpICovCisgIEkzODZfU1Q2X1JF R05VTSwJCS8qICVzdCg2KSAqLworICBJMzg2X1NUN19SRUdOVU0sCQkvKiAl c3QoNykgKi8KKyAgSTM4Nl9GQ1RSTCwJCQkvKiBmbG9hdGluZyBwb2ludCBl bnYgcmVncyA6IEZDVFJMLUZPUCAqLwkKKyAgSTM4Nl9GU1RBVCwgICAgICAg ICAgICAgICAgICAgCisgIEkzODZfRlRBRywJCQkKKyAgSTM4Nl9GSVNFRywK KyAgSTM4Nl9GSU9GRiwKKyAgSTM4Nl9GT1NFRywKKyAgSTM4Nl9GT09GRiwK KyAgSTM4Nl9GT1AKIH07CiAKICNkZWZpbmUgSTM4Nl9OVU1fR1JFR1MJMTYK --0-968222875-1243965514=:20508--