From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 110834 invoked by alias); 1 Dec 2016 13:07:26 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 110727 invoked by uid 89); 1 Dec 2016 13:07:25 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-4.8 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD,SPF_HELO_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:1958 X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 01 Dec 2016 13:07:24 +0000 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 02EB576A0B; Thu, 1 Dec 2016 13:07:23 +0000 (UTC) Received: from [127.0.0.1] (ovpn03.gateway.prod.ext.phx2.redhat.com [10.5.9.3]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id uB1D7L0c013888; Thu, 1 Dec 2016 08:07:21 -0500 Subject: Re: [PATCH 2/2 v2] [AArch64] Recognize STR instruction in prologue To: Yao Qi , gdb-patches@sourceware.org References: <1480428758-2481-1-git-send-email-yao.qi@linaro.org> <1480591000-19457-1-git-send-email-yao.qi@linaro.org> <1480591000-19457-2-git-send-email-yao.qi@linaro.org> From: Pedro Alves Message-ID: <2b5ae431-5bfb-2adf-aafb-fa2cbda12619@redhat.com> Date: Thu, 01 Dec 2016 13:07:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <1480591000-19457-2-git-send-email-yao.qi@linaro.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-SW-Source: 2016-12/txt/msg00027.txt.bz2 Hi Yao, On 12/01/2016 11:16 AM, Yao Qi wrote: > + else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */ > + || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */ > + && (inst.opcode->op == OP_STR_POS > + || inst.opcode->op == OP_STRF_POS))) > + && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM > + && strcmp ("str", inst.opcode->name) == 0) > + { > + /* STR (immediate) */ > + unsigned int rt = inst.operands[0].reg.regno; > + int32_t imm = inst.operands[1].addr.offset.imm; > + unsigned rn = inst.operands[1].addr.base_regno; Mixed "unsigned int" vs "unsigned" style. > + int is64 "bool". > + = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8); > + gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt > + || inst.operands[0].type == AARCH64_OPND_Ft); > + > + if (inst.operands[0].type == AARCH64_OPND_Ft) > + { > + /* Only bottom 64-bit of each V register (D register) need > + to be preserved. */ > + gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D); > + rt += AARCH64_X_REGISTER_COUNT; > + } > + > + pv_area_store (stack, pv_add_constant (regs[rn], imm), > + is64 ? 8 : 4, regs[rt]); > + if (inst.operands[1].addr.writeback) > + regs[rn] = pv_add_constant (regs[rn], imm); > + } > else if (inst.opcode->iclass == testbranch) > { > /* Stop analysis on branch. */ > @@ -546,6 +575,52 @@ aarch64_analyze_prologue_test (void) > == -1); > } > } > + > + /* Test a prologue in which STR is used and frame pointer is not > + used. */ Thanks for the new comments. This helps. > + { > + struct aarch64_prologue_cache cache; > + cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch); > + > + const uint32_t insns[] = { "static const". Sorry, my fault. Othewrise, code-style-wise LGTM. Thanks much for updating. I've not payed attention to Aarch64-specifics, TBC. I just assume you got those right. :-) Thanks, Pedro Alves