From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23156 invoked by alias); 30 Oct 2017 01:57:21 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 23139 invoked by uid 89); 30 Oct 2017 01:57:19 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.0 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 spammy=2417, sim, family X-HELO: smtp-out6.electric.net Received: from smtp-out6.electric.net (HELO smtp-out6.electric.net) (192.162.217.192) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 30 Oct 2017 01:57:17 +0000 Received: from 1e8zKE-00063W-VR by out6c.electric.net with emc1-ok (Exim 4.87) (envelope-from ) id 1e8zKF-00064v-T6 for gdb-patches@sourceware.org; Sun, 29 Oct 2017 18:57:15 -0700 Received: by emcmailer; Sun, 29 Oct 2017 18:57:15 -0700 Received: from [188.39.184.226] (helo=glaexch1.ftdichip.com) by out6c.electric.net with esmtps (TLSv1:AES128-SHA:128) (Exim 4.87) (envelope-from ) id 1e8zKE-00063W-VR for gdb-patches@sourceware.org; Sun, 29 Oct 2017 18:57:14 -0700 Received: from GLAEXCH1.ftdi.local ([172.16.0.121]) by glaexch3 ([172.16.0.161]) with mapi id 14.01.0438.000; Mon, 30 Oct 2017 01:57:14 +0000 From: James Bowman To: "gdb-patches@sourceware.org" Subject: [PATCH] FT32: support for FT32B processor - part 2/2 Date: Mon, 30 Oct 2017 01:57:00 -0000 Message-ID: <2BB0A51F073B384698CACFD1D5A30FCC0DED3E34@glaexch1> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-Outbound-IP: 188.39.184.226 X-Env-From: james.bowman@ftdichip.com X-Proto: esmtps X-Revdns: 188-39-184-226.static.enta.net X-TLS: TLSv1:AES128-SHA:128 X-Authenticated_ID: X-PolicySMART: 10711027 X-SW-Source: 2017-10/txt/msg00873.txt.bz2 FT32B is a new FT32 family member. It has a code compression scheme, which requires the use of linker relaxations. The change is quite large, so submission is in several parts. Part 2 adds support for the compressed instructions to gdb and sim. This patch contains the gdb changes. The corresponding binutils patch is https://sourceware.org/ml/binutils/2017-10/msg00423.html OK to commit? James. gdb/ChangeLog: 2017-10-29 James Bowman * ft32-tdep.c (ft32_fetch_instruction): New function. (ft32_analyze_prologue): Use ft32_fetch_instruction(). sim/ChangeLog: 2017-10-29 James Bowman * ft32/interp.c (step_once): Add ft32 shortcode decoder. --- diff --git a/gdb/ft32-tdep.c b/gdb/ft32-tdep.c index 757301a..00aba23 100644 --- a/gdb/ft32-tdep.c +++ b/gdb/ft32-tdep.c @@ -139,6 +139,22 @@ ft32_store_return_value (struct type *type, struct reg= cache *regcache, } } =20 +static ULONGEST +ft32_fetch_instruction (CORE_ADDR a, int *isize, + enum bfd_endian byte_order) +{ + unsigned int sc[2]; + ULONGEST inst; + + CORE_ADDR a4 =3D a & ~3; + inst =3D read_memory_unsigned_integer (a4, 4, byte_order); + *isize =3D ft32_decode_shortcode (a4, inst, sc) ? 2 : 4; + if (*isize =3D=3D 2) + return sc[1 & (a >> 1)]; + else + return inst; +} + /* Decode the instructions within the given address range. Decide when we must have reached the end of the function prologue. If a frame_info pointer is provided, fill in its saved_regs etc. @@ -153,6 +169,7 @@ ft32_analyze_prologue (CORE_ADDR start_addr, CORE_ADDR = end_addr, enum bfd_endian byte_order =3D gdbarch_byte_order (gdbarch); CORE_ADDR next_addr; ULONGEST inst; + int isize =3D 0; int regnum, pushreg; struct bound_minimal_symbol msymbol; const int first_saved_reg =3D 13; /* The first saved register. */ @@ -186,16 +203,15 @@ ft32_analyze_prologue (CORE_ADDR start_addr, CORE_ADD= R end_addr, return end_addr; =20 cache->established =3D 0; - for (next_addr =3D start_addr; next_addr < end_addr;) + for (next_addr =3D start_addr; next_addr < end_addr; next_addr +=3D isiz= e) { - inst =3D read_memory_unsigned_integer (next_addr, 4, byte_order); + inst =3D ft32_fetch_instruction (next_addr, &isize, byte_order); =20 if (FT32_IS_PUSH (inst)) { pushreg =3D FT32_PUSH_REG (inst); cache->framesize +=3D 4; cache->saved_regs[FT32_R0_REGNUM + pushreg] =3D cache->framesize; - next_addr +=3D 4; } else if (FT32_IS_CALL (inst)) { @@ -210,7 +226,6 @@ ft32_analyze_prologue (CORE_ADDR start_addr, CORE_ADDR = end_addr, cache->saved_regs[FT32_R0_REGNUM + pushreg] =3D cache->framesize; } - next_addr +=3D 4; } } break; @@ -229,7 +244,7 @@ ft32_analyze_prologue (CORE_ADDR start_addr, CORE_ADDR = end_addr, /* It is a LINK? */ if (next_addr < end_addr) { - inst =3D read_memory_unsigned_integer (next_addr, 4, byte_order); + inst =3D ft32_fetch_instruction (next_addr, &isize, byte_order); if (FT32_IS_LINK (inst)) { cache->established =3D 1; @@ -241,7 +256,7 @@ ft32_analyze_prologue (CORE_ADDR start_addr, CORE_ADDR = end_addr, cache->saved_regs[FT32_PC_REGNUM] =3D cache->framesize + 4; cache->saved_regs[FT32_FP_REGNUM] =3D 0; cache->framesize +=3D FT32_LINK_SIZE (inst); - next_addr +=3D 4; + next_addr +=3D isize; } } =20 diff --git a/sim/ft32/interp.c b/sim/ft32/interp.c index 3bc08ee..b3dded1 100644 --- a/sim/ft32/interp.c +++ b/sim/ft32/interp.c @@ -340,16 +340,24 @@ step_once (SIM_DESC sd) uint32_t bit_len; uint32_t upper; uint32_t insnpc; + unsigned int sc[2]; + int isize; =20 - if (cpu->state.cycles >=3D cpu->state.next_tick_cycle) - { - cpu->state.next_tick_cycle +=3D 100000; - ft32_push (sd, cpu->state.pc); - cpu->state.pc =3D 12; /* interrupt 1. */ - } inst =3D ft32_read_item (sd, 2, cpu->state.pc); cpu->state.cycles +=3D 1; =20 + if ((STATE_ARCHITECTURE (sd)->mach =3D=3D bfd_mach_ft32b) + && ft32_decode_shortcode (cpu->state.pc, inst, sc)) + { + if ((cpu->state.pc & 3) =3D=3D 0) + inst =3D sc[0]; + else + inst =3D sc[1]; + isize =3D 2; + } + else + isize =3D 4; + /* Handle "call 8" (which is FT32's "break" equivalent) here. */ if (inst =3D=3D 0x00340002) { @@ -390,7 +398,7 @@ step_once (SIM_DESC sd) upper =3D (inst >> 27); =20 insnpc =3D cpu->state.pc; - cpu->state.pc +=3D 4; + cpu->state.pc +=3D isize; switch (upper) { case FT32_PAT_TOC: