From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19596 invoked by alias); 22 Dec 2008 12:06:07 -0000 Received: (qmail 19585 invoked by uid 22791); 22 Dec 2008 12:06:05 -0000 X-SWARE-Spam-Status: No, hits=0.5 required=5.0 tests=AWL,BAYES_50,MIME_QP_LONG_LINE X-Spam-Check-By: sourceware.org Received: from smtp-out4.blueyonder.co.uk (HELO smtp-out4.blueyonder.co.uk) (195.188.213.7) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 22 Dec 2008 12:05:09 +0000 Received: from [172.23.170.144] (helo=anti-virus03-07) by smtp-out4.blueyonder.co.uk with smtp (Exim 4.52) id 1LEjWx-00062d-JB for gdb-patches@sourceware.org; Mon, 22 Dec 2008 12:05:03 +0000 Received: from [77.103.178.228] (helo=bibi) by asmtp-out6.blueyonder.co.uk with esmtp (Exim 4.52) id 1LEjWs-0003CU-NI for gdb-patches@sourceware.org; Mon, 22 Dec 2008 12:05:02 +0000 From: "Jon Beniston" To: References: Subject: RE: [PATCH] Add support for the Lattice Mico32 (LM32) architecture Date: Mon, 22 Dec 2008 12:06:00 -0000 Message-ID: <266F97CB7CD14C6899877E7D69AA2030@bibi> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_0009_01C9642D.7C5A5310" In-Reply-To: Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2008-12/txt/msg00373.txt.bz2 This is a multi-part message in MIME format. ------=_NextPart_000_0009_01C9642D.7C5A5310 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-length: 2002 Hi, The attached patch superceeds the patch I sent last week to add support for Lattice Mico32. It fixes a bug and addresses some comments I have received with regard to copyright headers etc. Cheers, Jon ChangeLog gdb/ 2008-12-15 Jon Beniston * MAINTAINERS: Add Jon Beniston as lm32 maintainer. * Makefile.in: Add lm32 dependencies. * NEWS: Indicate lm32 is a new target. * configure.tgt: Add lm32 targets. * lm32-linux-tdep.c: New file. * lm32-linux-tdep.h: New file. * lm32-tdep.c: New file. gdb/testsuite 2008-12-15 Jon Beniston * gdb.asm/asm-source.exp: Add lm32 target. include/gdb/ 2008-12-15 Jon Beniston * sim-lm32.h: New file. sim/ 2008-12-15 Jon Beniston * MAINTAINERS: Add Jon Beniston as maintainer of lm32 sim. * configure.ac: Add lm32 target. * lm32: New directory. sim/common 2008-12-15 Jon Beniston * gennltvals.sh: Add lm32 target. * nltvals.def: Add lm32 syscall definitions. sim/lm32/ 2008-12-15 Jon Beniston * Makefile.in: New file. * arch.c: New file. * arch.h: New file. * config.in: New file. * configure: New file. * configure.ac: New file. * cpu.c: New file. * cpu.h: New file. * cpuall.h: New file. * decode.c: New file. * decode.h: New file. * dv-lm32cpu.c: New file. * dv-lm32timer.c: New file. * dv-lm32uart.c: New file. * lm32.c: New file. * lm32-sim.h: New file. * mloop.in: New file. * model.c: New file. * sem.c: New file. * sem-switch.c: New file. * sim-if.c: New file. * sim-main.c: New file. * tconfig.in: New file. * traps.c: New file. * user.c: New file. ------=_NextPart_000_0009_01C9642D.7C5A5310 Content-Type: application/octet-stream; name="lm32.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="lm32.patch" Content-length: 365320 Index: gdb/MAINTAINERS=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/gdb/MAINTAINERS,v=0A= retrieving revision 1.407=0A= diff -c -p -r1.407 MAINTAINERS=0A= *** gdb/MAINTAINERS 26 Nov 2008 16:32:59 -0000 1.407=0A= --- gdb/MAINTAINERS 20 Dec 2008 22:02:19 -0000=0A= *************** the native maintainer when resolving ABI=0A= *** 269,274 ****=0A= --- 269,277 ----=0A= ia64 --target=3Dia64-linux-gnu ,-Werror=0A= (--target=3Dia64-elf broken)=0A= =20=20=0A= + lm32 --target=3Dlm32-elf ,-Werror=0A= + Jon Beniston, jon@beniston.com=0A= +=20=0A= m32c --target=3Dm32c-elf ,-Werror=0A= Jim Blandy, jimb@codesourcery.com=0A= =20=20=0A= Index: gdb/Makefile.in=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/gdb/Makefile.in,v=0A= retrieving revision 1.1061=0A= diff -c -p -r1.1061 Makefile.in=0A= *** gdb/Makefile.in 2 Dec 2008 07:57:36 -0000 1.1061=0A= --- gdb/Makefile.in 20 Dec 2008 22:02:20 -0000=0A= *************** ALL_TARGET_OBS =3D \=0A= *** 481,486 ****=0A= --- 481,487 ----=0A= i386-sol2-tdep.o i386-tdep.o i387-tdep.o \=0A= i386-dicos-tdep.o \=0A= iq2000-tdep.o \=0A= + lm32-linux-tdep.o lm32-tdep.o \=0A= m32c-tdep.o \=0A= m32r-linux-tdep.o m32r-tdep.o \=0A= m68hc11-tdep.o \=0A= *************** ALLDEPFILES =3D \=0A= *** 1298,1304 ****=0A= irix5-nat.c \=0A= libunwind-frame.c \=0A= linux-fork.c \=0A= ! m68hc11-tdep.c \=0A= m32r-tdep.c \=0A= m32r-linux-nat.c m32r-linux-tdep.c \=0A= m68k-tdep.c \=0A= --- 1299,1306 ----=0A= irix5-nat.c \=0A= libunwind-frame.c \=0A= linux-fork.c \=0A= ! lm32-linux-tdep.c lm32-tdep.c \=0A= ! m68hc11-tdep.c \=0A= m32r-tdep.c \=0A= m32r-linux-nat.c m32r-linux-tdep.c \=0A= m68k-tdep.c \=0A= Index: gdb/NEWS=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/gdb/NEWS,v=0A= retrieving revision 1.296=0A= diff -c -p -r1.296 NEWS=0A= *** gdb/NEWS 2 Dec 2008 07:57:36 -0000 1.296=0A= --- gdb/NEWS 20 Dec 2008 22:02:22 -0000=0A= *************** info os processes=0A= *** 185,190 ****=0A= --- 185,191 ----=0A= * New targets=0A= =20=20=0A= x86 DICOS i[34567]86-*-dicos*=0A= + Lattice Mico32 lm32-*=0A= =20=20=0A= * Removed commands=0A= =20=20=0A= Index: gdb/configure.tgt=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/gdb/configure.tgt,v=0A= retrieving revision 1.206=0A= diff -c -p -r1.206 configure.tgt=0A= *** gdb/configure.tgt 27 Nov 2008 09:23:01 -0000 1.206=0A= --- gdb/configure.tgt 20 Dec 2008 22:02:22 -0000=0A= *************** iq2000-*-*)=0A= *** 231,236 ****=0A= --- 231,245 ----=0A= gdb_sim=3D../sim/iq2000/libsim.a=0A= ;;=0A= =20=20=0A= + lm32*-*-uclinux*)=09=09=0A= + gdb_target_obs=3D"lm32-tdep.o lm32-linux-tdep.o"=20=0A= + gdb_sim=3D../sim/lm32/libsim.a=0A= + build_gdbserver=3Dyes=0A= + ;;=0A= + lm32*-*-*)=09=09=0A= + gdb_target_obs=3D"lm32-tdep.o"=20=0A= + gdb_sim=3D../sim/lm32/libsim.a=0A= + ;;=0A= m32c-*-*)=0A= # Target: Renesas M32C family=0A= gdb_target_obs=3D"m32c-tdep.o prologue-value.o"=0A= Index: gdb/lm32-linux-tdep.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: gdb/lm32-linux-tdep.c=0A= diff -N gdb/lm32-linux-tdep.c=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- gdb/lm32-linux-tdep.c 20 Dec 2008 22:02:23 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,772 ----=0A= + /* Target-dependent code for GNU/Linux running on the Lattice Mico32.=0A= +=20=09=20=0A= + Copyright (C) 2008 Free Software Foundation, Inc.=0A= +=20=0A= + This file is part of GDB.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify= =0A= + it under the terms of the GNU General Public License as published by= =0A= + the Free Software Foundation; either version 3 of the License, or=0A= + (at your option) any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program. If not, see . = */=0A= +=20=0A= + #include "defs.h"=0A= + #include "gdbcore.h"=0A= + #include "target.h"=0A= + #include "frame.h"=0A= + #include "osabi.h"=0A= + #include "elf-bfd.h"=0A= + #include "frame-unwind.h"=0A= + #include "regset.h"=0A= + #include "gdb_string.h"=0A= + #include "frame-base.h"=0A= + #include "inferior.h"=0A= + #include "dis-asm.h"=20=20=20=0A= + #include "symfile.h"=0A= + #include "remote.h"=0A= + #include "arch-utils.h"=0A= + #include "regcache.h"=0A= + #include "trad-frame.h"=0A= + #include "reggroups.h"=0A= +=20=0A= + #include "elf/lm32.h"=0A= + #include "lm32-linux-tdep.h"=0A= + #include "opcodes/lm32-desc.h"=0A= +=20=0A= + #include =0A= + #include =0A= +=20=0A= + int lm32_software_single_step (struct frame_info *frame);=0A= +=20=0A= + /* Define the size (in bytes) of an lm32 instruction. */=0A= + static const int lm32_instr_size =3D 4;=0A= +=20=0A= + enum {=0A= + NORMAL_SIGTRAMP =3D 1,=0A= + /* RT_SIGTRAMP =3D 2 */=0A= + };=0A= +=20=0A= + #define LM32_ELF_NGREG 32=0A= + typedef unsigned char lm32_elf_greg_t[4];=0A= + typedef struct { lm32_elf_greg_t reg[LM32_ELF_NGREG]; } lm32_elf_gregset_= t;=0A= +=20=0A= + /* Macros to extract fields from an instruction */=0A= + #define LM32_OPCODE(insn) ((insn >> 26) & 0x3f)=0A= + #define LM32_REG0(insn) ((insn >> 21) & 0x1f)=0A= + #define LM32_REG1(insn) ((insn >> 16) & 0x1f)=0A= + #define LM32_REG2(insn) ((insn >> 11) & 0x1f)=0A= + #define LM32_UIMM16(insn) (insn & 0xffff)=0A= + #define LM32_IMM16(insn) ((((long)insn & 0xffff) << 16) >> 16)=0A= + #define LM32_IMM26(insn) ((((long)insn & 0x3ffffff) << 6) >> 6)=0A= +=20=0A= + struct gdbarch_tdep=0A= + {=0A= + /* gdbarch target dependent data here. Currently unused for LM32. */=0A= + };=0A= +=20=0A= + struct lm32_unwind_cache=0A= + {=0A= + /* The previous frame's inner most stack address. Used as this=0A= + frame ID's stack_addr. */=0A= + CORE_ADDR prev_sp;=0A= + /* The frame's base. Used when constructing a frame ID. */=0A= + CORE_ADDR base;=0A= + /* Size of frame */=0A= + int size;=0A= + /* Whether the function uses fp as a frame pointer */=0A= + int uses_fp;=0A= + /* Table indicating the location of each and every register. */=0A= + struct trad_frame_saved_reg *saved_regs;=0A= + };=0A= +=20=0A= + static int=0A= + lm32_linux_pc_in_sigtramp (CORE_ADDR pc, char *name)=0A= + {=0A= + char buf[lm32_instr_size];=0A= + LONGEST instr;=0A= + int retval =3D 0;=0A= +=20=0A= + if (target_read_memory (pc, buf, sizeof buf) !=3D 0)=0A= + return 0;=0A= +=20=0A= + instr =3D extract_unsigned_integer (buf, sizeof buf);=0A= +=20=0A= + if (instr =3D=3D 0x34080077) /* mvi r8, __NR_sigreturn =3D addi r8, r= 0, __NR_sigreturn */=0A= + retval =3D NORMAL_SIGTRAMP;=0A= + else=0A= + return 0;=0A= +=20=0A= + if (target_read_memory (pc + lm32_instr_size, buf, sizeof buf) !=3D 0)= =0A= + return 0;=0A= + instr =3D extract_unsigned_integer (buf, sizeof buf);=0A= + if (instr !=3D 0xac000007) /* scall */=0A= + return 0;=0A= +=20=0A= + /* If we get this far, we'll return a non-zero value, this means NORMAL= _SIGTRAMP */=0A= + return retval;=0A= + }=0A= +=20=0A= + static void=20=0A= + lm32_linux_supply_gregset (const struct regset *regset,=0A= + struct regcache *regcache,=0A= + int regnum, const void *gregs, size_t len)=0A= + {=0A= + int regi;=0A= + char zerobuf[MAX_REGISTER_SIZE];=0A= + const lm32_elf_gregset_t *gregsetp =3D gregs;=0A= +=20=0A= + fprintf(stderr, "%s:%d\n", __FILE__, __LINE__);=0A= + memset (zerobuf, 0, MAX_REGISTER_SIZE);=0A= +=20=0A= + regcache_raw_supply (regcache, LM32_R0_REGNUM, zerobuf);=0A= +=20=0A= + for (regi =3D 1; regi <=3D 32; regi++)=0A= + {=0A= + regcache_raw_supply (regcache, regi, &gregsetp->reg[regi]);=0A= + }=0A= + }=0A= +=20=0A= + static struct regset lm32_linux_gregset =3D=0A= + {=0A= + NULL,=0A= + lm32_linux_supply_gregset=0A= + };=0A= +=20=20=20=20=0A= + static const struct regset *=0A= + lm32_linux_regset_from_core_section (struct gdbarch *gdbarch,=0A= + const char *sect_name, size_t sect_size)=0A= + {=0A= + if (strcmp (sect_name, ".reg") =3D=3D 0=20=0A= + && sect_size >=3D sizeof (lm32_elf_gregset_t))=0A= + return &lm32_linux_gregset;=0A= +=20=0A= + return NULL;=0A= + }=0A= +=20=0A= + static void=0A= + lm32_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)= =0A= + {=0A= + /* Set the sigtramp frame sniffer. */=0A= + //frame_unwind_append_sniffer (gdbarch, lm32_linux_sigtramp_frame_sniff= er);=20=0A= + set_gdbarch_regset_from_core_section (gdbarch,=0A= + lm32_linux_regset_from_core_secti= on);=0A= + }=0A= +=20=0A= + static enum gdb_osabi=0A= + lm32_linux_elf_osabi_sniffer (bfd *abfd)=0A= + {=0A= + int elf_flags;=0A= +=20=0A= + elf_flags =3D elf_elfheader (abfd)->e_flags;=0A= +=20=0A= + if (elf_flags & EF_LM32_MACH)=0A= + return GDB_OSABI_LINUX;=0A= + else=0A= + return GDB_OSABI_UNKNOWN;=0A= + }=0A= + /* Add the available register groups */=0A= +=20=0A= + static void=0A= + lm32_add_reggroups (struct gdbarch *gdbarch)=0A= + {=0A= + reggroup_add (gdbarch, general_reggroup);=0A= + reggroup_add (gdbarch, all_reggroup);=0A= + reggroup_add (gdbarch, system_reggroup);=20=20=20=20=0A= + }=0A= +=20=0A= + /* Return whether a given register is in a given group */=0A= +=20=0A= + static int=20=0A= + lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,=0A= + struct reggroup *group)=0A= + {=0A= + if (group =3D=3D general_reggroup)=20=0A= + {=0A= + return ((regnum >=3D LM32_R0_REGNUM) && (regnum <=3D LM32_RA_REG= NUM))=0A= + || (regnum =3D=3D LM32_PC_REGNUM);=0A= + }=0A= + else if (group =3D=3D system_reggroup)=20=0A= + {=0A= + return ( (regnum >=3D LM32_EA_REGNUM)=0A= + && (regnum <=3D LM32_BA_REGNUM)=0A= + );=0A= + }=20=0A= + return default_register_reggroup_p (gdbarch, regnum, group);=0A= + }=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =0A= +=20=0A= + /* Return a name that corresponds to the given register number */=0A= +=20=0A= + static const char *=0A= + lm32_register_name (struct gdbarch *gdbarch, int reg_nr)=0A= + {=0A= + static char *register_names[] =3D=20=0A= + {=0A= + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",=0A= + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",=20=0A= + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",=20=0A= + "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",=0A= + "PC", "EID", "EBA", "DEBA", "IE"=0A= + };=0A= +=20=20=20=0A= + if ((reg_nr < 0) || (reg_nr >=3D sizeof (register_names) / sizeof (regi= ster_names[0])))=0A= + return NULL;=0A= + else=0A= + return register_names[reg_nr];=0A= + }=0A= +=20=0A= + /* Return type of register */=0A= +=20=0A= + static struct type *=0A= + lm32_register_type (struct gdbarch *gdbarch, int reg_nr)=0A= + {=0A= + return builtin_type_int32;=0A= + }=0A= +=20=0A= + /* Return non-zero if a register can't be written */=0A= +=20=0A= + static int=0A= + lm32_cannot_store_register (struct gdbarch *gdbarch, int regno)=0A= + {=0A= + return (regno =3D=3D LM32_R0_REGNUM);=0A= + }=0A= +=20=0A= + /* Parse a functions prologue */=0A= +=20=0A= + static CORE_ADDR=0A= + lm32_parse_prologue (CORE_ADDR pc)=0A= + {=0A= + CORE_ADDR prologue_pc;=0A= + unsigned long instruction;=0A= + int done;=0A= + int op;=0A= + int i;=0A= + int literal;=0A= +=20=0A= + /* Keep reading though instructions, until we come accross an instructi= on=20=0A= + that isn't likely to be part of the prologue */=0A= + prologue_pc =3D pc;=0A= + done =3D 0;=20=0A= + while (!done)=20=0A= + {=20=20=20=20=20=20=20=20=20=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=0A= + /* Read an instruction */=20=20=20=0A= + instruction =3D read_memory_integer (prologue_pc, 4);=0A= + prologue_pc +=3D 4;=20=20=20=20=20=20=20=20=20=20=20=0A= +=20=0A= + if ( (LM32_OPCODE(instruction) =3D=3D OP_SW)=20=0A= + && (LM32_REG0(instruction) =3D=3D LM32_SP_REGNUM))=0A= + {=0A= + /* Any stack displaced store is likely part of the prologue */= =0A= + pc =3D prologue_pc;=0A= + }=0A= + else if ( (LM32_OPCODE(instruction) =3D=3D OP_ADDI)=20=0A= + && (LM32_REG1(instruction) =3D=3D LM32_SP_REGNUM))=0A= + {=0A= + /* An add to the SP is likely to be part of the prologue */=0A= + pc =3D prologue_pc;=0A= + }=0A= + else if ( /* add fp,fp,sp */=0A= + ( (LM32_OPCODE(instruction) =3D=3D OP_ADD)=20=0A= + && (LM32_REG2(instruction) =3D=3D LM32_FP_REGNUM)=20= =0A= + && (LM32_REG0(instruction) =3D=3D LM32_FP_REGNUM)=0A= + && (LM32_REG1(instruction) =3D=3D LM32_SP_REGNUM)=0A= + )=0A= + /* mv fp,imm */=0A= + || ( (LM32_OPCODE(instruction) =3D=3D OP_ADDI)=20=0A= + && (LM32_REG1(instruction) =3D=3D LM32_FP_REGNUM)=20= =0A= + && (LM32_REG0(instruction) =3D=3D LM32_R0_REGNUM)=0A= + )=0A= + )=0A= + {=0A= + /* Likely to be in the prologue for functions that require=20= =0A= + a frame pointer. */=0A= + pc =3D prologue_pc;=0A= + }=0A= + else=0A= + done =3D 1;=20=20=20=20=20=20=20=20=20=20=20=20=0A= + }=20=0A= +=20=0A= + return pc;=0A= + }=0A= +=20=0A= + /* Return PC of first non prologue instruction, for the function at the= =20=0A= + specified address. */=0A= +=20=0A= + static CORE_ADDR=0A= + lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)=0A= + {=0A= + CORE_ADDR func_addr, func_end;=0A= + struct symtab_and_line sal;=0A= +=20=0A= + /* If we have line debugging information, then the end of the=20=0A= + prologue should the first assembly instruction of the first source l= ine */=0A= + if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))=0A= + {=0A= + sal =3D find_pc_line (func_addr, 0);=0A= + if (sal.end && sal.end < func_end)=20=0A= + return sal.end;=20=20=20=20=20=20=20=20=0A= + }=0A= +=20=20=20=0A= + return lm32_parse_prologue (pc);=0A= + }=0A= +=20=0A= + /* Create a breakpoint instruction */=0A= +=20=0A= + static const unsigned char *=0A= + lm32_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *= lenptr)=0A= + {=0A= + static const unsigned char breakpoint[4] =3D {OP_RAISE << 2, 0, 0, 2};= =0A= + *lenptr =3D sizeof (breakpoint);=0A= + return breakpoint;=0A= + }=0A= +=20=0A= + /* Setup registers and stack for faking a call to a function in the infer= ior */=0A= +=20=0A= + static CORE_ADDR=0A= + lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,=0A= + struct regcache *regcache, CORE_ADDR bp_addr,=0A= + int nargs, struct value **args, CORE_ADDR sp,=0A= + int struct_return, CORE_ADDR struct_addr)=0A= + {=0A= + int first_arg_reg =3D LM32_R1_REGNUM;=0A= + int num_arg_regs =3D 8;=20=20=0A= + int i;=0A= +=20=20=20=0A= + /* Set the return address */=0A= + regcache_cooked_write_signed (regcache, LM32_RA_REGNUM, bp_addr);=0A= +=20=20=20=20=20=0A= + /* If we're returning a large struct, a pointer to the address to=0A= + store it at is passed as a first hidden parameter */=0A= + if (struct_return)=0A= + {=0A= + regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_add= r);=20=0A= + first_arg_reg++;=0A= + num_arg_regs--;=0A= + sp -=3D 4;=0A= + }=20=20=20=20=20=20=20=0A= +=20=20=20=20=20=0A= + /* Setup parameters */=0A= + for (i =3D 0; i < nargs; i++)=0A= + {=0A= + struct value *arg =3D args[i];=0A= + struct type *arg_type =3D check_typedef (value_type (arg));=0A= + char *contents;=0A= + int len;=0A= + int j;=0A= + int reg;=0A= + ULONGEST val;=0A= +=20=20=20=20=20=20=20=0A= + /* Promote small integer types to int */=0A= + switch (TYPE_CODE (arg_type))=0A= + {=0A= + case TYPE_CODE_INT:=0A= + case TYPE_CODE_BOOL:=0A= + case TYPE_CODE_CHAR:=0A= + case TYPE_CODE_RANGE:=0A= + case TYPE_CODE_ENUM:=0A= + if (TYPE_LENGTH (arg_type) < 4)=0A= + {=0A= + arg_type =3D builtin_type_int32;=0A= + arg =3D value_cast (arg_type, arg);=0A= + }=0A= + break;=0A= + }=20=20=0A= +=20=0A= + /* FIXME: Handle structures */=20=20=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=0A= + contents =3D (char *) value_contents (arg);=20=20=20=20=20=20=20=20= =0A= + len =3D TYPE_LENGTH (arg_type);=0A= + val =3D extract_unsigned_integer (contents, len);=0A= +=20=20=20=20=20=20=20=0A= + /* First num_arg_regs parameters go in registers, rest go on stack = */=0A= + if (i < num_arg_regs)=20=20=20=20=0A= + {=0A= + regcache_cooked_write_unsigned (regcache, first_arg_reg + i, va= l);=0A= + }=0A= + else=20=0A= + {=0A= + write_memory (sp, (void *)&val, len);=0A= + sp -=3D 4;=0A= + }=20=20=20=20=20=20=20=20=0A= + }=0A= +=20=20=20=20=20=0A= + /* Update stack pointer */=0A= + regcache_cooked_write_signed (regcache, LM32_SP_REGNUM, sp);=0A= +=20=20=20=20=20=20=20=20=20=0A= + /* Return adjusted stack pointer. */=0A= + return sp;=20=20=20=0A= + }=0A= +=20=0A= + /* Extract return value after calling a function in the inferior */=0A= +=20=0A= + static void=0A= + lm32_extract_return_value (struct type *type, struct regcache *regcache,= =20=0A= + gdb_byte *valbuf)=0A= + {=0A= + int offset;=0A= + ULONGEST l;=0A= + CORE_ADDR return_buffer;=0A= +=20=20=20=20=20=20=20=0A= + if ( TYPE_CODE(type) !=3D TYPE_CODE_STRUCT=0A= + && TYPE_CODE(type) !=3D TYPE_CODE_UNION=0A= + && TYPE_CODE(type) !=3D TYPE_CODE_ARRAY=0A= + && TYPE_LENGTH (type) <=3D 4=0A= + )=0A= + {=0A= + /* Return value is returned in a single register */=0A= + regcache_cooked_read_unsigned (regcache, LM32_R1_REGNUM, &l);=0A= + store_unsigned_integer (valbuf, TYPE_LENGTH (type), l);=0A= + }=0A= + else if ( (TYPE_CODE(type) =3D=3D TYPE_CODE_INT)=0A= + && (TYPE_LENGTH (type) =3D=3D 8)=0A= + )=0A= + {=0A= + /* 64-bit values are returned in a register pair */=0A= + regcache_cooked_read_unsigned (regcache, LM32_R1_REGNUM, &l);=0A= + memcpy (valbuf, &l, 4);=0A= + regcache_cooked_read_unsigned (regcache, LM32_R2_REGNUM, &l);=0A= + memcpy (valbuf + 4, &l, 4);=0A= + }=0A= + else=0A= + {=0A= + /* Aggregate types greater than a single register are returned in m= emory:=20=0A= + FIXME: Unless they are only 2 regs?. */=0A= + regcache_cooked_read_unsigned (regcache, LM32_R1_REGNUM, &l);=0A= + return_buffer =3D l;=0A= + read_memory (return_buffer, valbuf, TYPE_LENGTH (type));=0A= + }=20=20=20=20=0A= + }=0A= +=20=0A= + /* Write into appropriate registers a function return value of type=0A= + TYPE, given in virtual format. */=0A= + static void=0A= + lm32_store_return_value (struct type *type, struct regcache *regcache,=0A= + const gdb_byte *valbuf)=0A= + {=0A= + ULONGEST val;=0A= + int len =3D TYPE_LENGTH (type);=0A= +=20=0A= + if (len <=3D 4)=0A= + {=0A= + val =3D extract_unsigned_integer (valbuf, len);=0A= + regcache_cooked_write_unsigned (regcache, LM32_R1_REGNUM, val);=0A= + }=0A= + else if (len <=3D 8)=0A= + {=0A= + val =3D extract_unsigned_integer (valbuf, 4);=0A= + regcache_cooked_write_unsigned (regcache, LM32_R1_REGNUM, val);=0A= + val =3D extract_unsigned_integer ((char *)valbuf + 4, len - 4);=0A= + regcache_cooked_write_unsigned (regcache, LM32_R2_REGNUM, val);=0A= + }=0A= + else=0A= + error (_("lm32_store_return_value: type length too large."));=0A= + }=0A= +=20=0A= + /* Determine whether a functions return value is in a register or memory = */=0A= + static enum return_value_convention=0A= + lm32_return_value (struct gdbarch *gdbarch, struct type *func_type,=0A= + struct type *valtype, struct regcache *regcache,=20=0A= + gdb_byte *readbuf, const gdb_byte *writebuf)=0A= + {=0A= + enum type_code code =3D TYPE_CODE (valtype);=0A= +=20=0A= + if ((code =3D=3D TYPE_CODE_STRUCT=0A= + || code =3D=3D TYPE_CODE_UNION=0A= + || code =3D=3D TYPE_CODE_ARRAY=0A= + || TYPE_LENGTH (valtype) > 8))=0A= + return RETURN_VALUE_STRUCT_CONVENTION;=0A= +=20=0A= + if (readbuf)=0A= + lm32_extract_return_value (valtype, regcache, readbuf);=0A= + if (writebuf)=0A= + lm32_store_return_value (valtype, regcache, writebuf);=0A= +=20=0A= + return RETURN_VALUE_REGISTER_CONVENTION;=0A= + }=0A= +=20=0A= + static CORE_ADDR=0A= + lm32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)= =0A= + {=0A= + return frame_unwind_register_unsigned (next_frame, LM32_PC_REGNUM);=0A= + }=0A= +=20=0A= + static CORE_ADDR=0A= + lm32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)= =0A= + {=0A= + return frame_unwind_register_unsigned (next_frame, LM32_SP_REGNUM);=0A= + }=0A= +=20=0A= + static struct frame_id=0A= + lm32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)=0A= + {=0A= + CORE_ADDR sp =3D lm32_unwind_sp (gdbarch, this_frame);=0A= + return frame_id_build (sp, get_frame_pc (this_frame));=0A= + }=0A= +=20=0A= + struct lm32_unwind_cache *=0A= + lm32_frame_unwind_cache (struct frame_info *this_frame,=20=0A= + void **this_prologue_cache)=0A= + {=0A= + CORE_ADDR start_pc;=0A= + CORE_ADDR prologue_pc;=0A= + CORE_ADDR current_pc;=0A= + ULONGEST prev_sp;=0A= + ULONGEST this_base;=0A= + struct lm32_unwind_cache *info;=0A= + int done;=0A= + int prefixed;=0A= + unsigned long instruction;=0A= + int op;=0A= + int offsets[32];=0A= + int i;=0A= + long immediate;=0A= + int ra_on_stack;=0A= +=20=0A= + if ((*this_prologue_cache))=0A= + return (*this_prologue_cache);=0A= +=20=0A= + info =3D FRAME_OBSTACK_ZALLOC (struct lm32_unwind_cache);=0A= + (*this_prologue_cache) =3D info;=0A= + info->saved_regs =3D trad_frame_alloc_saved_regs (this_frame);=0A= +=20=0A= + info->size =3D 0;=0A= + info->uses_fp =3D 0;=0A= +=20=20=20=0A= + start_pc =3D get_frame_func (this_frame);=0A= + current_pc =3D get_frame_pc (this_frame);=0A= +=20=0A= + /* Keep reading through instructions, until we come accross an instruct= ion=20=0A= + that isn't likely to be part of the prologue */=0A= + prologue_pc =3D start_pc;=0A= + ra_on_stack =3D 0;=0A= + done =3D 0;=0A= +=20=20=20=0A= + while (!done && (current_pc > prologue_pc))=20=0A= + {=20=20=20=20=20=20=20=20=20=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=0A= + /* Read an instruction */=20=20=20=0A= + instruction =3D read_memory_integer (prologue_pc, 4);=0A= +=20=0A= + if ( (LM32_OPCODE(instruction) =3D=3D OP_SW)=20=0A= + && (LM32_REG0(instruction) =3D=3D LM32_SP_REGNUM))=20=20=20=20= =20=20=0A= + {=0A= + /* Any stack displaced store is likely part of the prologue.=20= =20=0A= + Record that the register is being saved, and the offset=20= =0A= + into the stack. */=0A= + info->saved_regs[LM32_REG1(instruction)].addr =3D LM32_IMM16(in= struction);=0A= + /* Check to see if the return address register is=20=0A= + being stored on the stack. */=0A= + if ( (LM32_REG1(instruction) =3D=3D LM32_RA_REGNUM)=20=0A= + && (current_pc > prologue_pc))=0A= + ra_on_stack =3D 1;=0A= + }=0A= + else if ( (LM32_OPCODE(instruction) =3D=3D OP_ADDI)=20=0A= + && (LM32_REG1(instruction) =3D=3D LM32_SP_REGNUM))=20=20= =20=20=20=0A= + {=0A= + /* An add to the SP is likely to be part of the prologue.=20=20= =0A= + Adjust stack size by whatever the instruction adds to the sp= . */=0A= + info->size -=3D LM32_IMM16(instruction);=0A= + }=0A= + else if ( /* add fp,fp,sp */=0A= + ( (LM32_OPCODE(instruction) =3D=3D OP_ADD)=20=0A= + && (LM32_REG2(instruction) =3D=3D LM32_FP_REGNUM)=20= =0A= + && (LM32_REG0(instruction) =3D=3D LM32_FP_REGNUM)=0A= + && (LM32_REG1(instruction) =3D=3D LM32_SP_REGNUM)=0A= + )=0A= + /* mv fp,imm */=0A= + || ( (LM32_OPCODE(instruction) =3D=3D OP_ADDI)=20=0A= + && (LM32_REG1(instruction) =3D=3D LM32_FP_REGNUM)=20= =0A= + && (LM32_REG0(instruction) =3D=3D LM32_R0_REGNUM)=0A= + )=0A= + )=0A= + {=0A= + /* Used in functions with a frame pointer. */=20=20=20=20=20= =20=20=20=20=20=0A= + info->uses_fp =3D 1;=0A= + }=0A= + else=0A= + {=0A= + /* Any other instruction is likely not to be part of the prolog= ue */=0A= + done =3D 1;=20=20=20=20=20=20=20=20=20=20=20=20=0A= + }=0A= +=20=0A= + prologue_pc +=3D 4;=20=20=20=20=20=20=20=20=20=20=20=0A= +=20=20=20=20=20=20=20=20=20=0A= + }=20=0A= +=20=20=20=20=20=0A= + /* Compute the frame's base, and the previous frame's SP. */=0A= + this_base =3D get_frame_register_unsigned (this_frame, LM32_SP_REGNUM);= =20=20=20=0A= + prev_sp =3D this_base + info->size;=0A= + info->base =3D this_base;=0A= + info->prev_sp =3D prev_sp;=0A= +=20=0A= + /* Convert callee save offsets into addresses */=0A= + for (i =3D 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i= ++)=0A= + {=0A= + if (trad_frame_addr_p (info->saved_regs, i))=0A= + info->saved_regs[i].addr =3D this_base + info->saved_regs[i].addr= ;=0A= + }=0A= +=20=0A= + /* The call instruction moves the caller's PC in the callee's RA regist= er.=0A= + Since this is an unwind, do the reverse. Copy the location of RA re= gister=0A= + into PC (the address / regnum) so that a request for PC will be=0A= + converted into a request for the RA register. */=0A= + info->saved_regs[LM32_PC_REGNUM] =3D info->saved_regs[LM32_RA_REGNUM];= =0A= +=20=20=20=20=20=0A= + /* The previous frame's SP needed to be computed. Save the computed va= lue. */=0A= + trad_frame_set_value (info->saved_regs, LM32_SP_REGNUM, info->prev_sp);= =0A= +=20=0A= + return info;=0A= + }=20=20=0A= +=20=0A= + /* Given a GDB frame, determine the address of the calling function's=0A= + frame. This will be used to create a new GDB frame struct. */=0A= +=20=0A= + static void=0A= + lm32_frame_this_id (struct frame_info *this_frame,=0A= + void **this_prologue_cache,=0A= + struct frame_id *this_id)=0A= + {=0A= + struct lm32_unwind_cache *info;=0A= + CORE_ADDR base;=0A= + CORE_ADDR func;=0A= + struct frame_id id;=0A= +=20=0A= + info =3D lm32_frame_unwind_cache (this_frame, this_prologue_cache);=0A= +=20=20=20=0A= + /* The FUNC is easy. */=0A= + func =3D get_frame_func (this_frame);=0A= +=20=20=20=20=20=0A= + /* Hopefully the prologue analysis either correctly determined the=0A= + frame's base (which is the SP from the previous frame), or set=0A= + that base to "NULL". */=0A= + base =3D info->base;=20=0A= + if (base =3D=3D 0)=0A= + return;=0A= +=20=20=20=20=20=0A= + id =3D frame_id_build (base, func);=0A= + (*this_id) =3D id;=20=20=0A= + }=0A= +=20=0A= + static struct value *=0A= + lm32_frame_prev_register (struct frame_info *this_frame,=0A= + void **this_prologue_cache,=0A= + int regnum)=0A= + {=0A= + struct lm32_unwind_cache *info;=0A= + info =3D lm32_frame_unwind_cache (this_frame, this_prologue_cache);=0A= + return trad_frame_get_prev_register (this_frame, info->saved_regs, regn= um);=0A= + }=0A= +=20=0A= + static const struct frame_unwind lm32_frame_unwind =3D {=0A= + NORMAL_FRAME,=0A= + lm32_frame_this_id,=0A= + lm32_frame_prev_register,=0A= + NULL,=0A= + default_frame_sniffer=0A= + };=0A= +=20=0A= + static CORE_ADDR=0A= + lm32_frame_base_address (struct frame_info *this_frame, void **this_cache= )=0A= + {=0A= + struct lm32_unwind_cache *info=0A= + =3D lm32_frame_unwind_cache (this_frame, this_cache);=0A= +=20=0A= + return info->base;=0A= + }=0A= +=20=0A= + static const struct frame_base lm32_frame_base =3D {=0A= + &lm32_frame_unwind,=0A= + lm32_frame_base_address,=0A= + lm32_frame_base_address,=0A= + lm32_frame_base_address=0A= + };=0A= +=20=0A= + static CORE_ADDR=0A= + lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)=0A= + {=0A= + /* Align to the size of an instruction (so that they can safely be=0A= + pushed onto the stack. */=0A= + return sp & ~3;=0A= + }=0A= +=20=0A= + static struct gdbarch *=0A= + lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches= )=0A= + {=0A= + struct gdbarch *gdbarch;=0A= + struct gdbarch_tdep *tdep;=0A= +=20=0A= + /* If there is already a candidate, use it. */=0A= + arches =3D gdbarch_list_lookup_by_info (arches, &info);=0A= + if (arches !=3D NULL)=0A= + return arches->gdbarch;=0A= +=20=20=20=0A= + /* None found, create a new architecture from the information provided.= */=0A= + tdep =3D XMALLOC (struct gdbarch_tdep);=0A= + gdbarch =3D gdbarch_alloc (&info, tdep);=0A= +=20=0A= + /* Type sizes */=0A= + set_gdbarch_short_bit (gdbarch, 16);=0A= + set_gdbarch_int_bit (gdbarch, 32);=0A= + set_gdbarch_long_bit (gdbarch, 32);=0A= + set_gdbarch_long_long_bit (gdbarch, 64);=0A= + set_gdbarch_float_bit (gdbarch, 32);=0A= + set_gdbarch_double_bit (gdbarch, 64);=0A= + set_gdbarch_long_double_bit (gdbarch, 64);=0A= + set_gdbarch_ptr_bit (gdbarch, 32);=0A= +=20=20=20=0A= + /* Register info */=0A= + set_gdbarch_num_regs (gdbarch, LM32_NUM_REGS);=0A= + set_gdbarch_sp_regnum (gdbarch, LM32_SP_REGNUM);=0A= + set_gdbarch_pc_regnum (gdbarch, LM32_PC_REGNUM);=20=20=0A= + set_gdbarch_register_name (gdbarch, lm32_register_name);=0A= + set_gdbarch_register_type (gdbarch, lm32_register_type);=0A= + set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register)= ;=0A= +=20=0A= + /* Frame info */=0A= + set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue);=0A= + set_gdbarch_inner_than (gdbarch, core_addr_lessthan);=0A= + set_gdbarch_decr_pc_after_break (gdbarch, 0);=0A= + set_gdbarch_frame_args_skip (gdbarch, 0);=0A= +=20=20=20=0A= + /* Frame unwinding */=20=20=0A= + set_gdbarch_frame_align (gdbarch, lm32_frame_align);=0A= + frame_base_set_default (gdbarch, &lm32_frame_base);=0A= + set_gdbarch_unwind_pc (gdbarch, lm32_unwind_pc);=0A= + set_gdbarch_unwind_sp (gdbarch, lm32_unwind_sp);=0A= + set_gdbarch_dummy_id (gdbarch, lm32_dummy_id);=0A= + frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind);=0A= +=20=20=20=0A= + /* Breakpoints */=0A= + set_gdbarch_breakpoint_from_pc (gdbarch, lm32_breakpoint_from_pc);=0A= + set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);=0A= + set_gdbarch_software_single_step (gdbarch, lm32_software_single_step);= =0A= +=20=20=20=0A= + /* Calling functions in the inferior */=0A= + set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call);=0A= + set_gdbarch_return_value (gdbarch, lm32_return_value);=0A= +=20=0A= + /* Instruction disassembler */=0A= + set_gdbarch_print_insn (gdbarch, print_insn_lm32);=0A= +=20=0A= + lm32_add_reggroups (gdbarch);=0A= + set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p);=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=0A= + return gdbarch;=0A= + }=0A= +=20=0A= + void=20=0A= + _initialize_lm32_tdep (void)=0A= + {=0A= + register_gdbarch_init (bfd_arch_lm32, lm32_gdbarch_init);=0A= + gdbarch_register_osabi (bfd_arch_lm32, 0, GDB_OSABI_LINUX, lm32_linux_i= nit_abi);=0A= + gdbarch_register_osabi_sniffer (bfd_arch_lm32,=0A= + bfd_target_elf_flavour,=0A= + lm32_linux_elf_osabi_sniffer);=0A= + }=0A= Index: gdb/lm32-linux-tdep.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: gdb/lm32-linux-tdep.h=0A= diff -N gdb/lm32-linux-tdep.h=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- gdb/lm32-linux-tdep.h 20 Dec 2008 22:02:23 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,68 ----=0A= + /* Target-dependent code for GNU/Linux running on the LM32.=0A= +=20=0A= + Copyright (C) 2008 Free Software Foundation, Inc.=0A= +=20=0A= + This file is part of GDB.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify= =0A= + it under the terms of the GNU General Public License as published by= =0A= + the Free Software Foundation; either version 2 of the License, or=0A= + (at your option) any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program; if not, write to the Free Software=0A= + Foundation, Inc., 51 Franklin Street, Fifth Floor,=0A= + Boston, MA 02110-1301, USA. */=0A= +=20=0A= + #ifndef LINUX_TDEP_LM32_H=0A= + #define LINUX_TDEP_LM32_H=0A= +=20=0A= + enum lm32_linux_regs=0A= + {=0A= + LM32_R0_REGNUM =3D 0,=0A= + LM32_R1_REGNUM,=20=20=20=20=20=0A= + LM32_R2_REGNUM,=20=20=20=20=20=0A= + LM32_R3_REGNUM,=20=20=20=20=20=0A= + LM32_R4_REGNUM,=20=20=20=20=20=0A= + LM32_R5_REGNUM,=20=20=20=20=20=0A= + LM32_R6_REGNUM,=20=20=20=20=20=0A= + LM32_R7_REGNUM,=20=20=20=20=20=0A= + LM32_R8_REGNUM,=20=20=20=20=20=0A= + LM32_R9_REGNUM,=20=20=20=20=20=0A= + LM32_R10_REGNUM,=20=20=20=20=0A= + LM32_R11_REGNUM,=20=20=20=20=0A= + LM32_R12_REGNUM,=20=20=20=20=0A= + LM32_R13_REGNUM,=20=20=20=20=0A= + LM32_R14_REGNUM,=20=20=20=20=0A= + LM32_R15_REGNUM,=20=20=20=20=0A= + LM32_R16_REGNUM,=20=20=20=20=0A= + LM32_R17_REGNUM,=20=20=20=20=0A= + LM32_R18_REGNUM,=20=20=20=20=0A= + LM32_R19_REGNUM,=20=20=20=20=0A= + LM32_R20_REGNUM,=20=20=20=20=0A= + LM32_R21_REGNUM,=20=20=20=20=0A= + LM32_R22_REGNUM,=20=20=20=20=0A= + LM32_R23_REGNUM,=20=20=20=20=0A= + LM32_R24_REGNUM,=20=20=20=20=0A= + LM32_R25_REGNUM,=20=20=20=20=0A= + LM32_GP_REGNUM,=20=20=20=20=20=0A= + LM32_FP_REGNUM,=20=20=20=20=20=0A= + LM32_SP_REGNUM,=20=20=20=20=20=0A= + LM32_RA_REGNUM,=20=20=20=20=20=0A= + LM32_EA_REGNUM, /* 30 =3D 0x1e */=20=20=20=20=0A= + LM32_BA_REGNUM,=0A= + LM32_PC_REGNUM,=0A= + LM32_NUM_REGS=20=20=20=20=20=20=0A= + };=0A= +=20=0A= + /* Fetch the executable load address for the PIC/FDPIC ABI.=0A= + Return 0 if successful, -1 if not. */=0A= + int lm32_load_address(struct gdbarch *gdbarch,=0A= + CORE_ADDR *load_addr);=0A= +=20=0A= + #endif=0A= Index: gdb/lm32-tdep.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: gdb/lm32-tdep.c=0A= diff -N gdb/lm32-tdep.c=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- gdb/lm32-tdep.c 20 Dec 2008 22:02:23 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,677 ----=0A= + /* Target-dependent code for Lattice Mico32 processor, for GDB.=0A= + Contributed by Jon Beniston =0A= +=20=0A= + Copyright (C) 2008 Free Software Foundation, Inc.=0A= +=20=0A= + This file is part of GDB.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify= =0A= + it under the terms of the GNU General Public License as published by= =0A= + the Free Software Foundation; either version 3 of the License, or=0A= + (at your option) any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program. If not, see . = */=0A= +=20=0A= + #include "defs.h"=0A= + #include "frame.h"=0A= + #include "frame-unwind.h"=0A= + #include "frame-base.h"=0A= + #include "inferior.h"=0A= + #include "dis-asm.h"=20=20=20=0A= + #include "symfile.h"=0A= + #include "remote.h"=0A= + #include "gdbcore.h"=0A= + #include "gdb/sim-lm32.h"=0A= + #include "gdb/callback.h"=0A= + #include "gdb/remote-sim.h"=0A= + #include "sim-regno.h"=0A= + #include "arch-utils.h"=0A= + #include "regcache.h"=0A= + #include "trad-frame.h"=0A= + #include "reggroups.h"=0A= + #include "opcodes/lm32-desc.h"=0A= +=20=0A= + #include =0A= + #include =0A= +=20=0A= + /* Macros to extract fields from an instruction */=0A= + #define LM32_OPCODE(insn) ((insn >> 26) & 0x3f)=0A= + #define LM32_REG0(insn) ((insn >> 21) & 0x1f)=0A= + #define LM32_REG1(insn) ((insn >> 16) & 0x1f)=0A= + #define LM32_REG2(insn) ((insn >> 11) & 0x1f)=0A= + #define LM32_UIMM16(insn) (insn & 0xffff)=0A= + #define LM32_IMM16(insn) ((((long)insn & 0xffff) << 16) >> 16)=0A= + #define LM32_IMM26(insn) ((((long)insn & 0x3ffffff) << 6) >> 6)=0A= +=20=0A= + struct gdbarch_tdep=0A= + {=0A= + /* gdbarch target dependent data here. Currently unused for LM32. */=0A= + };=0A= +=20=0A= + struct lm32_unwind_cache=0A= + {=0A= + /* The previous frame's inner most stack address. Used as this=0A= + frame ID's stack_addr. */=0A= + CORE_ADDR prev_sp;=0A= + /* The frame's base. Used when constructing a frame ID. */=0A= + CORE_ADDR base;=0A= + /* Size of frame */=0A= + int size;=0A= + /* Whether the function uses fp as a frame pointer */=0A= + int uses_fp;=0A= + /* Table indicating the location of each and every register. */=0A= + struct trad_frame_saved_reg *saved_regs;=0A= + };=0A= +=20=0A= + /* Add the available register groups */=0A= +=20=0A= + static void=0A= + lm32_add_reggroups (struct gdbarch *gdbarch)=0A= + {=0A= + reggroup_add (gdbarch, general_reggroup);=0A= + reggroup_add (gdbarch, all_reggroup);=0A= + reggroup_add (gdbarch, system_reggroup);=20=20=20=20=0A= + }=0A= +=20=0A= + /* Return whether a given register is in a given group */=0A= +=20=0A= + static int=20=0A= + lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,=0A= + struct reggroup *group)=0A= + {=0A= + if (group =3D=3D general_reggroup)=20=0A= + {=0A= + return ((regnum >=3D SIM_LM32_R0_REGNUM) && (regnum <=3D SIM_LM3= 2_RA_REGNUM))=0A= + || (regnum =3D=3D SIM_LM32_PC_REGNUM);=0A= + }=0A= + else if (group =3D=3D system_reggroup)=20=0A= + {=0A= + return ( (regnum >=3D SIM_LM32_EA_REGNUM)=0A= + && (regnum <=3D SIM_LM32_BA_REGNUM)=0A= + )=0A= + || ( (regnum >=3D SIM_LM32_EID_REGNUM)=0A= + && (regnum <=3D SIM_LM32_IE_REGNUM)=20=0A= + )=20=20=20=20=0A= + ;=0A= + }=20=0A= + return default_register_reggroup_p (gdbarch, regnum, group);=0A= + }=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =0A= +=20=0A= + /* Return a name that corresponds to the given register number */=0A= +=20=0A= + static const char *=0A= + lm32_register_name (struct gdbarch *gdbarch, int reg_nr)=0A= + {=0A= + static char *register_names[] =3D=20=0A= + {=0A= + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",=0A= + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",=20=0A= + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",=20=0A= + "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",=0A= + "PC", "EID", "EBA", "DEBA", "IE"=0A= + };=0A= +=20=20=20=0A= + if ((reg_nr < 0) || (reg_nr >=3D sizeof (register_names) / sizeof (regi= ster_names[0])))=0A= + return NULL;=0A= + else=0A= + return register_names[reg_nr];=0A= + }=0A= +=20=0A= + /* Return type of register */=0A= +=20=0A= + static struct type *=0A= + lm32_register_type (struct gdbarch *gdbarch, int reg_nr)=0A= + {=0A= + return builtin_type_int32;=0A= + }=0A= +=20=0A= + /* Return non-zero if a register can't be written */=0A= +=20=0A= + static int=0A= + lm32_cannot_store_register (struct gdbarch *gdbarch, int regno)=0A= + {=0A= + return (regno =3D=3D SIM_LM32_R0_REGNUM) || (regno =3D=3D SIM_LM32_EID_= REGNUM);=0A= + }=0A= +=20=0A= + /* Parse a functions prologue */=0A= +=20=0A= + static CORE_ADDR=0A= + lm32_parse_prologue (CORE_ADDR pc)=0A= + {=0A= + CORE_ADDR prologue_pc;=0A= + unsigned long instruction;=0A= + int done;=0A= + int op;=0A= + int i;=0A= + int literal;=0A= +=20=0A= + /* Keep reading though instructions, until we come accross an instructi= on=20=0A= + that isn't likely to be part of the prologue */=0A= + prologue_pc =3D pc;=0A= + done =3D 0;=20=0A= + while (!done)=20=0A= + {=20=20=20=20=20=20=20=20=20=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=0A= + /* Read an instruction */=20=20=20=0A= + instruction =3D read_memory_integer (prologue_pc, 4);=0A= + prologue_pc +=3D 4;=20=20=20=20=20=20=20=20=20=20=20=0A= +=20=0A= + if ( (LM32_OPCODE(instruction) =3D=3D OP_SW)=20=0A= + && (LM32_REG0(instruction) =3D=3D SIM_LM32_SP_REGNUM))=0A= + {=0A= + /* Any stack displaced store is likely part of the prologue */= =0A= + pc =3D prologue_pc;=0A= + }=0A= + else if ( (LM32_OPCODE(instruction) =3D=3D OP_ADDI)=20=0A= + && (LM32_REG1(instruction) =3D=3D SIM_LM32_SP_REGNUM))=0A= + {=0A= + /* An add to the SP is likely to be part of the prologue */=0A= + pc =3D prologue_pc;=0A= + }=0A= + else if ( /* add fp,fp,sp */=0A= + ( (LM32_OPCODE(instruction) =3D=3D OP_ADD)=20=0A= + && (LM32_REG2(instruction) =3D=3D SIM_LM32_FP_REGNUM)= =20=0A= + && (LM32_REG0(instruction) =3D=3D SIM_LM32_FP_REGNUM)= =0A= + && (LM32_REG1(instruction) =3D=3D SIM_LM32_SP_REGNUM)= =0A= + )=0A= + /* mv fp,imm */=0A= + || ( (LM32_OPCODE(instruction) =3D=3D OP_ADDI)=20=0A= + && (LM32_REG1(instruction) =3D=3D SIM_LM32_FP_REGNUM)= =20=0A= + && (LM32_REG0(instruction) =3D=3D SIM_LM32_R0_REGNUM)= =0A= + )=0A= + )=0A= + {=0A= + /* Likely to be in the prologue for functions that require=20= =0A= + a frame pointer. */=0A= + pc =3D prologue_pc;=0A= + }=0A= + else=0A= + done =3D 1;=20=20=20=20=20=20=20=20=20=20=20=20=0A= + }=20=0A= +=20=0A= + return pc;=0A= + }=0A= +=20=0A= + /* Return PC of first non prologue instruction, for the function at the= =20=0A= + specified address. */=0A= +=20=0A= + static CORE_ADDR=0A= + lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)=0A= + {=0A= + CORE_ADDR func_addr, func_end;=0A= + struct symtab_and_line sal;=0A= +=20=0A= + /* If we have line debugging information, then the end of the=20=0A= + prologue should the first assembly instruction of the first source l= ine */=0A= + if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))=0A= + {=0A= + sal =3D find_pc_line (func_addr, 0);=0A= + if (sal.end && sal.end < func_end)=20=0A= + return sal.end;=20=20=20=20=20=20=20=20=0A= + }=0A= +=20=20=20=0A= + return lm32_parse_prologue (pc);=0A= + }=0A= +=20=0A= + /* Create a breakpoint instruction */=0A= +=20=0A= + static const unsigned char *=0A= + lm32_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *= lenptr)=0A= + {=0A= + static const unsigned char breakpoint[4] =3D {OP_RAISE << 2, 0, 0, 2};= =0A= + *lenptr =3D sizeof (breakpoint);=0A= + return breakpoint;=0A= + }=0A= +=20=0A= + /* Setup registers and stack for faking a call to a function in the infer= ior */=0A= +=20=0A= + static CORE_ADDR=0A= + lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,=0A= + struct regcache *regcache, CORE_ADDR bp_addr,=0A= + int nargs, struct value **args, CORE_ADDR sp,=0A= + int struct_return, CORE_ADDR struct_addr)=0A= + {=0A= + int first_arg_reg =3D SIM_LM32_R1_REGNUM;=0A= + int num_arg_regs =3D 8;=20=20=0A= + int i;=0A= +=20=20=20=0A= + /* Set the return address */=0A= + regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr);= =0A= +=20=20=20=20=20=0A= + /* If we're returning a large struct, a pointer to the address to=0A= + store it at is passed as a first hidden parameter */=0A= + if (struct_return)=0A= + {=0A= + regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_add= r);=20=0A= + first_arg_reg++;=0A= + num_arg_regs--;=0A= + sp -=3D 4;=0A= + }=20=20=20=20=20=20=20=0A= +=20=20=20=20=20=0A= + /* Setup parameters */=0A= + for (i =3D 0; i < nargs; i++)=0A= + {=0A= + struct value *arg =3D args[i];=0A= + struct type *arg_type =3D check_typedef (value_type (arg));=0A= + char *contents;=0A= + int len;=0A= + int j;=0A= + int reg;=0A= + ULONGEST val;=0A= +=20=20=20=20=20=20=20=0A= + /* Promote small integer types to int */=0A= + switch (TYPE_CODE (arg_type))=0A= + {=0A= + case TYPE_CODE_INT:=0A= + case TYPE_CODE_BOOL:=0A= + case TYPE_CODE_CHAR:=0A= + case TYPE_CODE_RANGE:=0A= + case TYPE_CODE_ENUM:=0A= + if (TYPE_LENGTH (arg_type) < 4)=0A= + {=0A= + arg_type =3D builtin_type_int32;=0A= + arg =3D value_cast (arg_type, arg);=0A= + }=0A= + break;=0A= + }=20=20=0A= +=20=0A= + /* FIXME: Handle structures */=20=20=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=0A= + contents =3D (char *) value_contents (arg);=20=20=20=20=20=20=20=20= =0A= + len =3D TYPE_LENGTH (arg_type);=0A= + val =3D extract_unsigned_integer (contents, len);=0A= +=20=20=20=20=20=20=20=0A= + /* First num_arg_regs parameters go in registers, rest go on stack = */=0A= + if (i < num_arg_regs)=20=20=20=20=0A= + {=0A= + regcache_cooked_write_unsigned (regcache, first_arg_reg + i, va= l);=0A= + }=0A= + else=20=0A= + {=0A= + write_memory (sp, (void *)&val, len);=0A= + sp -=3D 4;=0A= + }=20=20=20=20=20=20=20=20=0A= + }=0A= +=20=20=20=20=20=0A= + /* Update stack pointer */=0A= + regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp);=0A= +=20=20=20=20=20=20=20=20=20=0A= + /* Return adjusted stack pointer. */=0A= + return sp;=20=20=20=0A= + }=0A= +=20=0A= + /* Extract return value after calling a function in the inferior */=0A= +=20=0A= + static void=0A= + lm32_extract_return_value (struct type *type, struct regcache *regcache,= =20=0A= + gdb_byte *valbuf)=0A= + {=0A= + int offset;=0A= + ULONGEST l;=0A= + CORE_ADDR return_buffer;=0A= +=20=20=20=20=20=20=20=0A= + if ( TYPE_CODE(type) !=3D TYPE_CODE_STRUCT=0A= + && TYPE_CODE(type) !=3D TYPE_CODE_UNION=0A= + && TYPE_CODE(type) !=3D TYPE_CODE_ARRAY=0A= + && TYPE_LENGTH (type) <=3D 4=0A= + )=0A= + {=0A= + /* Return value is returned in a single register */=0A= + regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);= =0A= + store_unsigned_integer (valbuf, TYPE_LENGTH (type), l);=0A= + }=0A= + else if ( (TYPE_CODE(type) =3D=3D TYPE_CODE_INT)=0A= + && (TYPE_LENGTH (type) =3D=3D 8)=0A= + )=0A= + {=0A= + /* 64-bit values are returned in a register pair */=0A= + regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);= =0A= + memcpy (valbuf, &l, 4);=0A= + regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l);= =0A= + memcpy (valbuf + 4, &l, 4);=0A= + }=0A= + else=0A= + {=0A= + /* Aggregate types greater than a single register are returned in m= emory:=20=0A= + FIXME: Unless they are only 2 regs?. */=0A= + regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);= =0A= + return_buffer =3D l;=0A= + read_memory (return_buffer, valbuf, TYPE_LENGTH (type));=0A= + }=20=20=20=20=0A= + }=0A= +=20=0A= + /* Write into appropriate registers a function return value of type=0A= + TYPE, given in virtual format. */=0A= + static void=0A= + lm32_store_return_value (struct type *type, struct regcache *regcache,=0A= + const gdb_byte *valbuf)=0A= + {=0A= + ULONGEST val;=0A= + int len =3D TYPE_LENGTH (type);=0A= +=20=0A= + if (len <=3D 4)=0A= + {=0A= + val =3D extract_unsigned_integer (valbuf, len);=0A= + regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);= =0A= + }=0A= + else if (len <=3D 8)=0A= + {=0A= + val =3D extract_unsigned_integer (valbuf, 4);=0A= + regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);= =0A= + val =3D extract_unsigned_integer ((char *)valbuf + 4, len - 4);=0A= + regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val);= =0A= + }=0A= + else=0A= + error (_("lm32_store_return_value: type length too large."));=0A= + }=0A= +=20=0A= + /* Determine whether a functions return value is in a register or memory = */=0A= + static enum return_value_convention=0A= + lm32_return_value (struct gdbarch *gdbarch, struct type *func_type,=0A= + struct type *valtype, struct regcache *regcache,=20=0A= + gdb_byte *readbuf, const gdb_byte *writebuf)=0A= + {=0A= + enum type_code code =3D TYPE_CODE (valtype);=0A= +=20=0A= + if ((code =3D=3D TYPE_CODE_STRUCT=0A= + || code =3D=3D TYPE_CODE_UNION=0A= + || code =3D=3D TYPE_CODE_ARRAY=0A= + || TYPE_LENGTH (valtype) > 8))=0A= + return RETURN_VALUE_STRUCT_CONVENTION;=0A= +=20=0A= + if (readbuf)=0A= + lm32_extract_return_value (valtype, regcache, readbuf);=0A= + if (writebuf)=0A= + lm32_store_return_value (valtype, regcache, writebuf);=0A= +=20=0A= + return RETURN_VALUE_REGISTER_CONVENTION;=0A= + }=0A= +=20=0A= + static CORE_ADDR=0A= + lm32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)= =0A= + {=0A= + return frame_unwind_register_unsigned (next_frame, SIM_LM32_PC_REGNUM);= =0A= + }=0A= +=20=0A= + static CORE_ADDR=0A= + lm32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)= =0A= + {=0A= + return frame_unwind_register_unsigned (next_frame, SIM_LM32_SP_REGNUM);= =0A= + }=0A= +=20=0A= + static struct frame_id=0A= + lm32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)=0A= + {=0A= + CORE_ADDR sp =3D lm32_unwind_sp (gdbarch, this_frame);=0A= + return frame_id_build (sp, get_frame_pc (this_frame));=0A= + }=0A= +=20=0A= + /* Put here the code to store, into fi->saved_regs, the addresses of=0A= + the saved registers of frame described by FRAME_INFO. This=0A= + includes special registers such as pc and fp saved in special ways=0A= + in the stack frame. sp is even more special: the address we return=0A= + for it IS the sp for the next frame. */=0A= +=20=0A= + struct lm32_unwind_cache *=0A= + lm32_frame_unwind_cache (struct frame_info *this_frame,=20=0A= + void **this_prologue_cache)=0A= + {=0A= + CORE_ADDR start_pc;=0A= + CORE_ADDR prologue_pc;=0A= + CORE_ADDR current_pc;=0A= + ULONGEST prev_sp;=0A= + ULONGEST this_base;=0A= + struct lm32_unwind_cache *info;=0A= + int done;=0A= + int prefixed;=0A= + unsigned long instruction;=0A= + int op;=0A= + int offsets[32];=0A= + int i;=0A= + long immediate;=0A= + int ra_on_stack;=0A= +=20=0A= + if ((*this_prologue_cache))=0A= + return (*this_prologue_cache);=0A= +=20=0A= + info =3D FRAME_OBSTACK_ZALLOC (struct lm32_unwind_cache);=0A= + (*this_prologue_cache) =3D info;=0A= + info->saved_regs =3D trad_frame_alloc_saved_regs (this_frame);=0A= +=20=0A= + info->size =3D 0;=0A= + info->uses_fp =3D 0;=0A= +=20=20=20=0A= + start_pc =3D get_frame_func (this_frame);=0A= + current_pc =3D get_frame_pc (this_frame);=0A= +=20=0A= + /* Keep reading through instructions, until we come accross an instruct= ion=20=0A= + that isn't likely to be part of the prologue */=0A= + prologue_pc =3D start_pc;=0A= + ra_on_stack =3D 0;=0A= + done =3D 0;=0A= +=20=20=20=0A= + while (!done && (current_pc > prologue_pc))=20=0A= + {=20=20=20=20=20=20=20=20=20=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=0A= + /* Read an instruction */=20=20=20=0A= + instruction =3D read_memory_integer (prologue_pc, 4);=0A= +=20=0A= + if ( (LM32_OPCODE(instruction) =3D=3D OP_SW)=20=0A= + && (LM32_REG0(instruction) =3D=3D SIM_LM32_SP_REGNUM))=20=20=20= =20=20=20=0A= + {=0A= + /* Any stack displaced store is likely part of the prologue.=20= =20=0A= + Record that the register is being saved, and the offset=20= =0A= + into the stack. */=0A= + info->saved_regs[LM32_REG1(instruction)].addr =3D LM32_IMM16(in= struction);=0A= + /* Check to see if the return address register is=20=0A= + being stored on the stack. */=0A= + if ( (LM32_REG1(instruction) =3D=3D SIM_LM32_RA_REGNUM)=20=0A= + && (current_pc > prologue_pc))=0A= + ra_on_stack =3D 1;=0A= + }=0A= + else if ( (LM32_OPCODE(instruction) =3D=3D OP_ADDI)=20=0A= + && (LM32_REG1(instruction) =3D=3D SIM_LM32_SP_REGNUM))=20= =20=20=20=20=0A= + {=0A= + /* An add to the SP is likely to be part of the prologue.=20=20= =0A= + Adjust stack size by whatever the instruction adds to the sp= . */=0A= + info->size -=3D LM32_IMM16(instruction);=0A= + }=0A= + else if ( /* add fp,fp,sp */=0A= + ( (LM32_OPCODE(instruction) =3D=3D OP_ADD)=20=0A= + && (LM32_REG2(instruction) =3D=3D SIM_LM32_FP_REGNUM)= =20=0A= + && (LM32_REG0(instruction) =3D=3D SIM_LM32_FP_REGNUM)= =0A= + && (LM32_REG1(instruction) =3D=3D SIM_LM32_SP_REGNUM)= =0A= + )=0A= + /* mv fp,imm */=0A= + || ( (LM32_OPCODE(instruction) =3D=3D OP_ADDI)=20=0A= + && (LM32_REG1(instruction) =3D=3D SIM_LM32_FP_REGNUM)= =20=0A= + && (LM32_REG0(instruction) =3D=3D SIM_LM32_R0_REGNUM)= =0A= + )=0A= + )=0A= + {=0A= + /* Used in functions with a frame pointer. */=20=20=20=20=20= =20=20=20=20=20=0A= + info->uses_fp =3D 1;=0A= + }=0A= + else=0A= + {=0A= + /* Any other instruction is likely not to be part of the prolog= ue */=0A= + done =3D 1;=20=20=20=20=20=20=20=20=20=20=20=20=0A= + }=0A= +=20=0A= + prologue_pc +=3D 4;=20=20=20=20=20=20=20=20=20=20=20=0A= +=20=20=20=20=20=20=20=20=20=0A= + }=20=0A= +=20=20=20=20=20=0A= + /* Compute the frame's base, and the previous frame's SP. */=0A= + this_base =3D get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGN= UM);=20=20=20=0A= + prev_sp =3D this_base + info->size;=0A= + info->base =3D this_base;=0A= + info->prev_sp =3D prev_sp;=0A= +=20=0A= + /* Convert callee save offsets into addresses */=0A= + for (i =3D 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i= ++)=0A= + {=0A= + if (trad_frame_addr_p (info->saved_regs, i))=0A= + info->saved_regs[i].addr =3D this_base + info->saved_regs[i].addr= ;=0A= + }=0A= +=20=0A= + /* The call instruction moves the caller's PC in the callee's RA regist= er.=0A= + Since this is an unwind, do the reverse. Copy the location of RA re= gister=0A= + into PC (the address / regnum) so that a request for PC will be=0A= + converted into a request for the RA register. */=0A= + info->saved_regs[SIM_LM32_PC_REGNUM] =3D info->saved_regs[SIM_LM32_RA_R= EGNUM];=0A= +=20=20=20=20=20=0A= + /* The previous frame's SP needed to be computed. Save the computed va= lue. */=0A= + trad_frame_set_value (info->saved_regs, SIM_LM32_SP_REGNUM, info->prev_= sp);=0A= +=20=0A= + return info;=0A= + }=20=20=0A= +=20=0A= + /* Given a GDB frame, determine the address of the calling function's=0A= + frame. This will be used to create a new GDB frame struct. */=0A= +=20=0A= + static void=0A= + lm32_frame_this_id (struct frame_info *this_frame,=0A= + void **this_prologue_cache,=0A= + struct frame_id *this_id)=0A= + {=0A= + struct lm32_unwind_cache *info;=0A= + CORE_ADDR base;=0A= + CORE_ADDR func;=0A= + struct frame_id id;=0A= +=20=0A= + info =3D lm32_frame_unwind_cache (this_frame, this_prologue_cache);=0A= +=20=20=20=0A= + /* The FUNC is easy. */=0A= + func =3D get_frame_func (this_frame);=0A= +=20=20=20=20=20=0A= + /* Hopefully the prologue analysis either correctly determined the=0A= + frame's base (which is the SP from the previous frame), or set=0A= + that base to "NULL". */=0A= + base =3D info->base;=20=0A= +=20=20=20=0A= + if (base =3D=3D 0)=0A= + return;=0A= +=20=20=20=20=20=0A= + id =3D frame_id_build (base, func);=0A= + (*this_id) =3D id;=20=20=0A= + }=0A= +=20=0A= + static struct value *=0A= + lm32_frame_prev_register (struct frame_info *this_frame,=0A= + void **this_prologue_cache,=0A= + int regnum)=0A= + {=0A= + struct lm32_unwind_cache *info;=0A= + info =3D lm32_frame_unwind_cache (this_frame, this_prologue_cache);=0A= + return trad_frame_get_prev_register (this_frame, info->saved_regs, regn= um);=0A= + }=0A= +=20=0A= + static const struct frame_unwind lm32_frame_unwind =3D {=0A= + NORMAL_FRAME,=0A= + lm32_frame_this_id,=0A= + lm32_frame_prev_register,=0A= + NULL,=0A= + default_frame_sniffer=0A= + };=0A= +=20=0A= + static CORE_ADDR=0A= + lm32_frame_base_address (struct frame_info *this_frame, void **this_cache= )=0A= + {=0A= + struct lm32_unwind_cache *info=0A= + =3D lm32_frame_unwind_cache (this_frame, this_cache);=0A= +=20=0A= + return info->base;=0A= + }=0A= +=20=0A= + static const struct frame_base lm32_frame_base =3D {=0A= + &lm32_frame_unwind,=0A= + lm32_frame_base_address,=0A= + lm32_frame_base_address,=0A= + lm32_frame_base_address=0A= + };=0A= +=20=0A= + static CORE_ADDR=0A= + lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)=0A= + {=0A= + /* Align to the size of an instruction (so that they can safely be=0A= + pushed onto the stack. */=0A= + return sp & ~3;=0A= + }=0A= +=20=0A= + static struct gdbarch *=0A= + lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches= )=0A= + {=0A= + struct gdbarch *gdbarch;=0A= + struct gdbarch_tdep *tdep;=0A= +=20=0A= + /* If there is already a candidate, use it. */=0A= + arches =3D gdbarch_list_lookup_by_info (arches, &info);=0A= + if (arches !=3D NULL)=0A= + return arches->gdbarch;=0A= +=20=20=20=0A= + /* None found, create a new architecture from the information provided.= */=0A= + tdep =3D XMALLOC (struct gdbarch_tdep);=0A= + gdbarch =3D gdbarch_alloc (&info, tdep);=0A= +=20=20=20=20=20=20=20=0A= + /* Type sizes */=0A= + set_gdbarch_short_bit (gdbarch, 16);=0A= + set_gdbarch_int_bit (gdbarch, 32);=0A= + set_gdbarch_long_bit (gdbarch, 32);=0A= + set_gdbarch_long_long_bit (gdbarch, 64);=0A= + set_gdbarch_float_bit (gdbarch, 32);=0A= + set_gdbarch_double_bit (gdbarch, 64);=0A= + set_gdbarch_long_double_bit (gdbarch, 64);=0A= + set_gdbarch_ptr_bit (gdbarch, 32);=0A= +=20=20=20=0A= + /* Register info */=0A= + set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS);=0A= + set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM);=0A= + set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM);=20=20=0A= + set_gdbarch_register_name (gdbarch, lm32_register_name);=0A= + set_gdbarch_register_type (gdbarch, lm32_register_type);=0A= + set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register)= ;=0A= +=20=0A= + /* Frame info */=0A= + set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue);=0A= + set_gdbarch_inner_than (gdbarch, core_addr_lessthan);=0A= + set_gdbarch_decr_pc_after_break (gdbarch, 0);=0A= + set_gdbarch_frame_args_skip (gdbarch, 0);=0A= +=20=20=20=0A= + /* Frame unwinding */=20=20=0A= + set_gdbarch_frame_align (gdbarch, lm32_frame_align);=0A= + frame_base_set_default (gdbarch, &lm32_frame_base);=0A= + set_gdbarch_unwind_pc (gdbarch, lm32_unwind_pc);=0A= + set_gdbarch_unwind_sp (gdbarch, lm32_unwind_sp);=0A= + set_gdbarch_dummy_id (gdbarch, lm32_dummy_id);=0A= + frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind);=0A= +=20=20=20=0A= + /* Breakpoints */=0A= + set_gdbarch_breakpoint_from_pc (gdbarch, lm32_breakpoint_from_pc);=0A= + set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);=0A= +=20=20=20=0A= + /* Calling functions in the inferior */=0A= + set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call);=0A= + set_gdbarch_return_value (gdbarch, lm32_return_value);=0A= +=20=20=20=0A= + /* Instruction disassembler */=0A= + set_gdbarch_print_insn (gdbarch, print_insn_lm32);=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=0A= + lm32_add_reggroups (gdbarch);=0A= + set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p);=0A= +=20=20=20=20=20=20=20=20=20=20=20=20=20=0A= + return gdbarch;=0A= + }=0A= +=20=20=20=20=0A= + void=20=0A= + _initialize_lm32_tdep (void)=0A= + {=0A= + register_gdbarch_init (bfd_arch_lm32, lm32_gdbarch_init);=0A= + }=0A= +=20=0A= Index: gdb/testsuite/gdb.asm/asm-source.exp=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/gdb/testsuite/gdb.asm/asm-source.exp,v=0A= retrieving revision 1.72=0A= diff -c -p -r1.72 asm-source.exp=0A= *** gdb/testsuite/gdb.asm/asm-source.exp 6 Aug 2008 12:52:06 -0000 1.72=0A= --- gdb/testsuite/gdb.asm/asm-source.exp 20 Dec 2008 22:02:24 -0000=0A= *************** switch -glob -- [istarget] {=0A= *** 64,69 ****=0A= --- 64,72 ----=0A= "i\[3456\]86-*-*" {=0A= set asm-arch i386=0A= }=0A= + "lm32-*" {=0A= + set asm-arch lm32=0A= + }=0A= "m32r*-linux*" {=0A= set asm-arch m32r-linux=0A= }=0A= Index: include/gdb/sim-lm32.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: include/gdb/sim-lm32.h=0A= diff -N include/gdb/sim-lm32.h=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- include/gdb/sim-lm32.h 20 Dec 2008 22:02:25 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,74 ----=0A= + /* This file defines the interface between the LM32 simulator and GDB.=0A= + Contributed by Jon Beniston =0A= +=20=0A= + Copyright (C) 2008 Free Software Foundation, Inc.=0A= +=20=0A= + This file is part of GDB.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify= =0A= + it under the terms of the GNU General Public License as published by= =0A= + the Free Software Foundation; either version 3 of the License, or=0A= + (at your option) any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program. If not, see . = */=0A= +=20=0A= + #ifndef SIM_LM32_H=0A= + #define SIM_LM32_H=0A= +=20=0A= + #ifdef __cplusplus=0A= + extern "C" { // }=0A= + #endif=0A= +=20=0A= + enum sim_lm32_regs=0A= + {=0A= + SIM_LM32_R0_REGNUM,=0A= + SIM_LM32_R1_REGNUM,=20=20=20=20=20=0A= + SIM_LM32_R2_REGNUM,=20=20=20=20=20=0A= + SIM_LM32_R3_REGNUM,=20=20=20=20=20=0A= + SIM_LM32_R4_REGNUM,=20=20=20=20=20=0A= + SIM_LM32_R5_REGNUM,=20=20=20=20=20=0A= + SIM_LM32_R6_REGNUM,=20=20=20=20=20=0A= + SIM_LM32_R7_REGNUM,=20=20=20=20=20=0A= + SIM_LM32_R8_REGNUM,=20=20=20=20=20=0A= + SIM_LM32_R9_REGNUM,=20=20=20=20=20=0A= + SIM_LM32_R10_REGNUM,=20=20=20=20=0A= + SIM_LM32_R11_REGNUM,=20=20=20=20=0A= + SIM_LM32_R12_REGNUM,=20=20=20=20=0A= + SIM_LM32_R13_REGNUM,=20=20=20=20=0A= + SIM_LM32_R14_REGNUM,=20=20=20=20=0A= + SIM_LM32_R15_REGNUM,=20=20=20=20=0A= + SIM_LM32_R16_REGNUM,=20=20=20=20=0A= + SIM_LM32_R17_REGNUM,=20=20=20=20=0A= + SIM_LM32_R18_REGNUM,=20=20=20=20=0A= + SIM_LM32_R19_REGNUM,=20=20=20=20=0A= + SIM_LM32_R20_REGNUM,=20=20=20=20=0A= + SIM_LM32_R21_REGNUM,=20=20=20=20=0A= + SIM_LM32_R22_REGNUM,=20=20=20=20=0A= + SIM_LM32_R23_REGNUM,=20=20=20=20=0A= + SIM_LM32_R24_REGNUM,=20=20=20=20=0A= + SIM_LM32_R25_REGNUM,=20=20=20=20=0A= + SIM_LM32_GP_REGNUM,=20=20=20=20=20=0A= + SIM_LM32_FP_REGNUM,=20=20=20=20=20=0A= + SIM_LM32_SP_REGNUM,=20=20=20=20=20=0A= + SIM_LM32_RA_REGNUM,=20=20=20=20=20=0A= + SIM_LM32_BA_REGNUM,=20=20=20=20=20=0A= + SIM_LM32_EA_REGNUM,=20=20=20=20=20=0A= + SIM_LM32_PC_REGNUM,=0A= + SIM_LM32_EID_REGNUM,=0A= + SIM_LM32_EBA_REGNUM,=20=20=0A= + SIM_LM32_DEBA_REGNUM,=20=0A= + SIM_LM32_IE_REGNUM,=20=20=0A= + SIM_LM32_NUM_REGS=20=20=20=20=20=20=0A= + };=0A= +=20=0A= + #ifdef __cplusplus=0A= + }=0A= + #endif=0A= +=20=0A= + #endif=0A= Index: sim/MAINTAINERS=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/sim/MAINTAINERS,v=0A= retrieving revision 1.22=0A= diff -c -p -r1.22 MAINTAINERS=0A= *** sim/MAINTAINERS 8 Apr 2008 07:15:39 -0000 1.22=0A= --- sim/MAINTAINERS 20 Dec 2008 22:02:33 -0000=0A= *************** cr16 M R Swami Reddy =0A= igen (igen simulators)=0A= ppc Andrew Cagney =0A= + lm32 Jon Beniston =0A= m68hc11 Stephane Carrez =0A= mips Thiemo Seufer =0A= sh (global maintainers)=0A= Index: sim/configure.ac=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/sim/configure.ac,v=0A= retrieving revision 1.14=0A= diff -c -p -r1.14 configure.ac=0A= *** sim/configure.ac 8 Apr 2008 09:15:56 -0000 1.14=0A= --- sim/configure.ac 20 Dec 2008 22:02:35 -0000=0A= *************** if test "${enable_sim}" !=3D no; then=0A= *** 74,79 ****=0A= --- 74,83 ----=0A= AC_CONFIG_SUBDIRS(iq2000)=0A= testsuite=3Dyes=0A= ;;=0A= + lm32-*-*)=0A= + AC_CONFIG_SUBDIRS(lm32)=0A= + testsuite=3Dyes=0A= + ;;=0A= m32c-*-*)=0A= AC_CONFIG_SUBDIRS(m32c)=0A= ;;=0A= Index: sim/common/gennltvals.sh=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/sim/common/gennltvals.sh,v=0A= retrieving revision 1.4=0A= diff -c -p -r1.4 gennltvals.sh=0A= *** sim/common/gennltvals.sh 8 Apr 2008 08:44:51 -0000 1.4=0A= --- sim/common/gennltvals.sh 20 Dec 2008 22:02:35 -0000=0A= *************** dir=3Dlibgloss/v850/sys target=3Dv850=0A= *** 73,75 ****=0A= --- 73,78 ----=0A= $shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \=0A= "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}"=0A= =20=20=0A= + dir=3Dlibgloss target=3Dlm32=0A= + $shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \=0A= + "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}"=0A= Index: sim/common/nltvals.def=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/sim/common/nltvals.def,v=0A= retrieving revision 1.4=0A= diff -c -p -r1.4 nltvals.def=0A= *** sim/common/nltvals.def 8 Apr 2008 08:44:51 -0000 1.4=0A= --- sim/common/nltvals.def 20 Dec 2008 22:02:35 -0000=0A= ***************=0A= *** 454,456 ****=0A= --- 454,483 ----=0A= /* end cr16 sys target macros */=0A= #endif=0A= #endif=0A= + #ifdef NL_TARGET_lm32=0A= + #ifdef sys_defs=0A= + /* from syscall.h */=0A= + /* begin lm32 sys target macros */=0A= + { "SYS_argv", 13 },=0A= + { "SYS_argvlen", 12 },=0A= + { "SYS_chdir", 14 },=0A= + { "SYS_chmod", 16 },=0A= + { "SYS_close", 3 },=0A= + { "SYS_exit", 1 },=0A= + { "SYS_fstat", 10 },=0A= + { "SYS_getpid", 8 },=0A= + { "SYS_gettimeofday", 19 },=0A= + { "SYS_kill", 9 },=0A= + { "SYS_link", 21 },=0A= + { "SYS_lseek", 6 },=0A= + { "SYS_open", 2 },=0A= + { "SYS_read", 4 },=0A= + { "SYS_stat", 15 },=0A= + { "SYS_time", 18 },=0A= + { "SYS_times", 20 },=0A= + { "SYS_unlink", 7 },=0A= + { "SYS_utime", 17 },=0A= + { "SYS_write", 5 },=0A= + /* end lm32 sys target macros */=0A= + #endif=0A= + #endif=0A= Index: sim/lm32/Makefile.in=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/Makefile.in=0A= diff -N sim/lm32/Makefile.in=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/Makefile.in 20 Dec 2008 22:02:35 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,90 ----=0A= + # Makefile for Lattice Mico32 simulator.=0A= + # Contributed by Jon Beniston =0A= +=20=0A= + ## COMMON_PRE_CONFIG_FRAG=0A= +=20=0A= + # List of object files, less common parts.=0A= + SIM_OBJS =3D \=0A= + $(SIM_NEW_COMMON_OBJS) \=0A= + sim-cpu.o \=0A= + sim-hload.o \=0A= + sim-hrw.o \=0A= + sim-model.o \=0A= + sim-reg.o \=0A= + sim-signal.o \=0A= + cgen-utils.o cgen-trace.o cgen-scache.o \=0A= + cgen-run.o sim-reason.o sim-engine.o sim-stop.o \=0A= + sim-if.o arch.o \=0A= + cpu.o decode.o sem.o model.o mloop.o \=0A= + lm32.o traps.o user.o=20=0A= +=20=20=20=20=20=20=20=20=20=0A= + # List of extra dependencies.=0A= + # Generally this consists of simulator specific files included by sim-mai= n.h.=0A= + SIM_EXTRA_DEPS =3D $(CGEN_INCLUDE_DEPS) $(srcdir)/../../opcodes/lm32-desc= .h=0A= +=20=0A= + # List of flags to always pass to $(CC).=0A= + #SIM_EXTRA_CFLAGS =3D=0A= +=20=0A= + # List of main object files for `run'.=0A= + SIM_RUN_OBJS =3D nrun.o=0A= +=20=0A= + SIM_EXTRA_CLEAN =3D lm32-clean=0A= +=20=0A= + # This selects the lm32 newlib/libgloss syscall definitions.=0A= + NL_TARGET =3D -DNL_TARGET_lm32=0A= +=20=0A= + ## COMMON_POST_CONFIG_FRAG=0A= +=20=0A= + arch =3D lm32=20=0A= +=20=0A= + arch.o: arch.c $(SIM_MAIN_DEPS)=0A= +=20=0A= + sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h=0A= +=20=0A= + LM32BF_INCLUDE_DEPS =3D \=0A= + $(CGEN_MAIN_CPU_DEPS) \=0A= + cpu.h decode.h eng.h=0A= +=20=0A= + lm32.o: lm32.c $(LM32BF_INCLUDE_DEPS)=0A= +=20=0A= + # FIXME: Use of `mono' is wip.=0A= + mloop.c eng.h: stamp-mloop=0A= + stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile=0A= + $(SHELL) $(srccom)/genmloop.sh \=0A= + -mono -fast -pbb -switch sem-switch.c \=0A= + -cpu lm32bf -infile $(srcdir)/mloop.in=0A= + $(SHELL) $(srcroot)/move-if-change eng.hin eng.h=0A= + $(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c=0A= + touch stamp-mloop=0A= + mloop.o: mloop.c sem-switch.c=20=0A= +=20=0A= + cpu.o: cpu.c $(LM32BF_INCLUDE_DEPS)=0A= + decode.o: decode.c $(LM32BF_INCLUDE_DEPS)=0A= + sem.o: sem.c $(LM32BF_INCLUDE_DEPS)=0A= + model.o: model.c $(LM32BF_INCLUDE_DEPS)=0A= +=20=0A= + lm32-clean:=0A= + rm -f mloop.c eng.h stamp-mloop=0A= + rm -f stamp-arch stamp-cpu=20=0A= + rm -f tmp-*=0A= +=20=0A= + # cgen support, enable with --enable-cgen-maint=0A= + CGEN_MAINT =3D ; @true=0A= + # The following line is commented in or out depending upon --enable-cgen-= maint.=0A= + @CGEN_MAINT@CGEN_MAINT =3D=0A= +=20=0A= + stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/lm32.cpu=0A= + $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=3Dall \=0A= + archfile=3D$(CGEN_CPU_DIR)/lm32.cpu \=0A= + FLAGS=3D"with-scache with-profile=3Dfn"=0A= + touch stamp-arch=0A= + arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch=0A= +=20=0A= + stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU= _DIR)/lm32.cpu=0A= + $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \=0A= + cpu=3Dlm32bf mach=3Dlm32 SUFFIX=3D \=0A= + archfile=3D$(CGEN_CPU_DIR)/lm32.cpu \=0A= + FLAGS=3D"with-scache with-profile=3Dfn" \=0A= + EXTRAFILES=3D"$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"=0A= + touch stamp-cpu=0A= + cpu.h sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-c= pu=0A= Index: sim/lm32/arch.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/arch.c=0A= diff -N sim/lm32/arch.c=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/arch.c 20 Dec 2008 22:02:35 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,35 ----=0A= + /* Simulator support for lm32.=0A= +=20=0A= + THIS FILE IS MACHINE GENERATED WITH CGEN.=0A= +=20=0A= + Copyright 1996-2005 Free Software Foundation, Inc.=0A= +=20=0A= + This file is part of the GNU simulators.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 2, or (at your option)=0A= + any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License along= =0A= + with this program; if not, write to the Free Software Foundation, Inc.,= =0A= + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.=0A= +=20=0A= + */=0A= +=20=0A= + #include "sim-main.h"=0A= + #include "bfd.h"=0A= +=20=0A= + const MACH *sim_machs[] =3D=0A= + {=0A= + #ifdef HAVE_CPU_LM32BF=0A= + & lm32_mach,=0A= + #endif=0A= + 0=0A= + };=0A= +=20=0A= Index: sim/lm32/arch.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/arch.h=0A= diff -N sim/lm32/arch.h=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/arch.h 20 Dec 2008 22:02:35 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,44 ----=0A= + /* Simulator header for lm32.=0A= +=20=0A= + THIS FILE IS MACHINE GENERATED WITH CGEN.=0A= +=20=0A= + Copyright 1996-2005 Free Software Foundation, Inc.=0A= +=20=0A= + This file is part of the GNU simulators.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 2, or (at your option)=0A= + any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License along= =0A= + with this program; if not, write to the Free Software Foundation, Inc.,= =0A= + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.=0A= +=20=0A= + */=0A= +=20=0A= + #ifndef LM32_ARCH_H=0A= + #define LM32_ARCH_H=0A= +=20=0A= + #define TARGET_BIG_ENDIAN 1=0A= +=20=0A= + /* Enum declaration for model types. */=0A= + typedef enum model_type {=0A= + MODEL_LM32, MODEL_MAX=0A= + } MODEL_TYPE;=0A= +=20=0A= + #define MAX_MODELS ((int) MODEL_MAX)=0A= +=20=0A= + /* Enum declaration for unit types. */=0A= + typedef enum unit_type {=0A= + UNIT_NONE, UNIT_LM32_U_EXEC, UNIT_MAX=0A= + } UNIT_TYPE;=0A= +=20=0A= + #define MAX_UNITS (1)=0A= +=20=0A= + #endif /* LM32_ARCH_H */=0A= Index: sim/lm32/config.in=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/config.in=0A= diff -N sim/lm32/config.in=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/config.in 20 Dec 2008 22:02:35 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,116 ----=0A= + /* config.in. Generated from configure.ac by autoheader. */=0A= +=20=0A= + /* Define if building universal (internal helper macro) */=0A= + #undef AC_APPLE_UNIVERSAL_BUILD=0A= +=20=0A= + /* Define to 1 if translation of program messages to the user's native=0A= + language is requested. */=0A= + #undef ENABLE_NLS=0A= +=20=0A= + /* Define to 1 if you have the header file. */=0A= + #undef HAVE_DLFCN_H=0A= +=20=0A= + /* Define to 1 if you have the header file. */=0A= + #undef HAVE_ERRNO_H=0A= +=20=0A= + /* Define to 1 if you have the header file. */=0A= + #undef HAVE_FCNTL_H=0A= +=20=0A= + /* Define to 1 if you have the header file. */=0A= + #undef HAVE_FPU_CONTROL_H=0A= +=20=0A= + /* Define to 1 if you have the `getrusage' function. */=0A= + #undef HAVE_GETRUSAGE=0A= +=20=0A= + /* Define to 1 if you have the header file. */=0A= + #undef HAVE_INTTYPES_H=0A= +=20=0A= + /* Define to 1 if you have the `nsl' library (-lnsl). */=0A= + #undef HAVE_LIBNSL=0A= +=20=0A= + /* Define to 1 if you have the `socket' library (-lsocket). */=0A= + #undef HAVE_LIBSOCKET=0A= +=20=0A= + /* Define to 1 if you have the header file. */=0A= + #undef HAVE_MEMORY_H=0A= +=20=0A= + /* Define to 1 if you have the `sigaction' function. */=0A= + #undef HAVE_SIGACTION=0A= +=20=0A= + /* Define to 1 if you have the header file. */=0A= + #undef HAVE_STDINT_H=0A= +=20=0A= + /* Define to 1 if you have the header file. */=0A= + #undef HAVE_STDLIB_H=0A= +=20=0A= + /* Define to 1 if you have the header file. */=0A= + #undef HAVE_STRINGS_H=0A= +=20=0A= + /* Define to 1 if you have the header file. */=0A= + #undef HAVE_STRING_H=0A= +=20=0A= + /* Define to 1 if you have the header file. */=0A= + #undef HAVE_SYS_RESOURCE_H=0A= +=20=0A= + /* Define to 1 if you have the header file. */=0A= + #undef HAVE_SYS_STAT_H=0A= +=20=0A= + /* Define to 1 if you have the header file. */=0A= + #undef HAVE_SYS_TIME_H=0A= +=20=0A= + /* Define to 1 if you have the header file. */=0A= + #undef HAVE_SYS_TYPES_H=0A= +=20=0A= + /* Define to 1 if you have the `time' function. */=0A= + #undef HAVE_TIME=0A= +=20=0A= + /* Define to 1 if you have the header file. */=0A= + #undef HAVE_TIME_H=0A= +=20=0A= + /* Define to 1 if you have the header file. */=0A= + #undef HAVE_UNISTD_H=0A= +=20=0A= + /* Define to 1 if you have the header file. */=0A= + #undef HAVE_ZLIB_H=0A= +=20=0A= + /* Define to 1 if you have the `__setfpucw' function. */=0A= + #undef HAVE___SETFPUCW=0A= +=20=0A= + /* Define to the address where bug reports for this package should be sen= t. */=0A= + #undef PACKAGE_BUGREPORT=0A= +=20=0A= + /* Define to the full name of this package. */=0A= + #undef PACKAGE_NAME=0A= +=20=0A= + /* Define to the full name and version of this package. */=0A= + #undef PACKAGE_STRING=0A= +=20=0A= + /* Define to the one symbol short name of this package. */=0A= + #undef PACKAGE_TARNAME=0A= +=20=0A= + /* Define to the version of this package. */=0A= + #undef PACKAGE_VERSION=0A= +=20=0A= + /* Additional package description */=0A= + #undef PKGVERSION=0A= +=20=0A= + /* Bug reporting address */=0A= + #undef REPORT_BUGS_TO=0A= +=20=0A= + /* Define as the return type of signal handlers (`int' or `void'). */=0A= + #undef RETSIGTYPE=0A= +=20=0A= + /* Define to 1 if you have the ANSI C header files. */=0A= + #undef STDC_HEADERS=0A= +=20=0A= + /* Define WORDS_BIGENDIAN to 1 if your processor stores words with the mo= st=0A= + significant byte first (like Motorola and SPARC, unlike Intel). */=0A= + #if defined AC_APPLE_UNIVERSAL_BUILD=0A= + # if defined __BIG_ENDIAN__=0A= + # define WORDS_BIGENDIAN 1=0A= + # endif=0A= + #else=0A= + # ifndef WORDS_BIGENDIAN=0A= + # undef WORDS_BIGENDIAN=0A= + # endif=0A= + #endif=0A= Index: sim/lm32/configure.ac=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/configure.ac=0A= diff -N sim/lm32/configure.ac=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/configure.ac 20 Dec 2008 22:02:35 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,21 ----=0A= + dnl Process this file with autoconf to produce a configure script.=0A= + AC_PREREQ(2.59)dnl=0A= + AC_INIT(Makefile.in)=0A= + AC_CONFIG_HEADER(config.h:config.in)=0A= +=20=0A= + sinclude(../common/aclocal.m4)=0A= +=20=0A= + # Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around=0A= + # it by inlining the macro's contents.=0A= + sinclude(../common/common.m4)=0A= +=20=0A= + SIM_AC_OPTION_ENDIAN(BIG_ENDIAN)=0A= + SIM_AC_OPTION_ALIGNMENT(STRICT_ALIGNMENT,STRICT_ALIGNMENT)=0A= + SIM_AC_OPTION_HOSTENDIAN=0A= + SIM_AC_OPTION_SCACHE(16384)=0A= + SIM_AC_OPTION_DEFAULT_MODEL(lm32)=0A= + SIM_AC_OPTION_ENVIRONMENT=0A= + SIM_AC_OPTION_CGEN_MAINT=0A= + SIM_AC_OPTION_HARDWARE(yes,,lm32cpu lm32timer lm32uart)=0A= +=20=0A= + SIM_AC_OUTPUT=0A= Index: sim/lm32/cpu.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/cpu.c=0A= diff -N sim/lm32/cpu.c=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/cpu.c 20 Dec 2008 22:02:35 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,85 ----=0A= + /* Misc. support for CPU family lm32bf.=0A= +=20=0A= + THIS FILE IS MACHINE GENERATED WITH CGEN.=0A= +=20=0A= + Copyright 1996-2005 Free Software Foundation, Inc.=0A= +=20=0A= + This file is part of the GNU simulators.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 2, or (at your option)=0A= + any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License along= =0A= + with this program; if not, write to the Free Software Foundation, Inc.,= =0A= + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.=0A= +=20=0A= + */=0A= +=20=0A= + #define WANT_CPU lm32bf=0A= + #define WANT_CPU_LM32BF=0A= +=20=0A= + #include "sim-main.h"=0A= + #include "cgen-ops.h"=0A= +=20=0A= + /* Get the value of h-pc. */=0A= +=20=0A= + USI=0A= + lm32bf_h_pc_get (SIM_CPU *current_cpu)=0A= + {=0A= + return CPU (h_pc);=0A= + }=0A= +=20=0A= + /* Set a value for h-pc. */=0A= +=20=0A= + void=0A= + lm32bf_h_pc_set (SIM_CPU *current_cpu, USI newval)=0A= + {=0A= + CPU (h_pc) =3D newval;=0A= + }=0A= +=20=0A= + /* Get the value of h-gr. */=0A= +=20=0A= + SI=0A= + lm32bf_h_gr_get (SIM_CPU *current_cpu, UINT regno)=0A= + {=0A= + return CPU (h_gr[regno]);=0A= + }=0A= +=20=0A= + /* Set a value for h-gr. */=0A= +=20=0A= + void=0A= + lm32bf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)=0A= + {=0A= + CPU (h_gr[regno]) =3D newval;=0A= + }=0A= +=20=0A= + /* Get the value of h-csr. */=0A= +=20=0A= + SI=0A= + lm32bf_h_csr_get (SIM_CPU *current_cpu, UINT regno)=0A= + {=0A= + return CPU (h_csr[regno]);=0A= + }=0A= +=20=0A= + /* Set a value for h-csr. */=0A= +=20=0A= + void=0A= + lm32bf_h_csr_set (SIM_CPU *current_cpu, UINT regno, SI newval)=0A= + {=0A= + CPU (h_csr[regno]) =3D newval;=0A= + }=0A= +=20=0A= + /* Record trace results for INSN. */=0A= +=20=0A= + void=0A= + lm32bf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,=0A= + int *indices, TRACE_RECORD *tr)=0A= + {=0A= + }=0A= Index: sim/lm32/cpu.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/cpu.h=0A= diff -N sim/lm32/cpu.h=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/cpu.h 20 Dec 2008 22:02:35 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,349 ----=0A= + /* CPU family header for lm32bf.=0A= +=20=0A= + THIS FILE IS MACHINE GENERATED WITH CGEN.=0A= +=20=0A= + Copyright 1996-2005 Free Software Foundation, Inc.=0A= +=20=0A= + This file is part of the GNU simulators.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 2, or (at your option)=0A= + any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License along= =0A= + with this program; if not, write to the Free Software Foundation, Inc.,= =0A= + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.=0A= +=20=0A= + */=0A= +=20=0A= + #ifndef CPU_LM32BF_H=0A= + #define CPU_LM32BF_H=0A= +=20=0A= + /* Maximum number of instructions that are fetched at a time.=0A= + This is for LIW type instructions sets (e.g. m32r). */=0A= + #define MAX_LIW_INSNS 1=0A= +=20=0A= + /* Maximum number of instructions that can be executed in parallel. */= =0A= + #define MAX_PARALLEL_INSNS 1=0A= +=20=0A= + /* CPU state information. */=0A= + typedef struct {=0A= + /* Hardware elements. */=0A= + struct {=0A= + /* Program counter */=0A= + USI h_pc;=0A= + #define GET_H_PC() CPU (h_pc)=0A= + #define SET_H_PC(x) (CPU (h_pc) =3D (x))=0A= + /* General purpose registers */=0A= + SI h_gr[32];=0A= + #define GET_H_GR(a1) CPU (h_gr)[a1]=0A= + #define SET_H_GR(a1, x) (CPU (h_gr)[a1] =3D (x))=0A= + /* Control and status registers */=0A= + SI h_csr[32];=0A= + #define GET_H_CSR(a1) CPU (h_csr)[a1]=0A= + #define SET_H_CSR(a1, x) (CPU (h_csr)[a1] =3D (x))=0A= + } hardware;=0A= + #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)=0A= + } LM32BF_CPU_DATA;=0A= +=20=0A= + /* Cover fns for register access. */=0A= + USI lm32bf_h_pc_get (SIM_CPU *);=0A= + void lm32bf_h_pc_set (SIM_CPU *, USI);=0A= + SI lm32bf_h_gr_get (SIM_CPU *, UINT);=0A= + void lm32bf_h_gr_set (SIM_CPU *, UINT, SI);=0A= + SI lm32bf_h_csr_get (SIM_CPU *, UINT);=0A= + void lm32bf_h_csr_set (SIM_CPU *, UINT, SI);=0A= +=20=0A= + /* These must be hand-written. */=0A= + extern CPUREG_FETCH_FN lm32bf_fetch_register;=0A= + extern CPUREG_STORE_FN lm32bf_store_register;=0A= +=20=0A= + typedef struct {=0A= + int empty;=0A= + } MODEL_LM32_DATA;=0A= +=20=0A= + /* Instruction argument buffer. */=0A= +=20=0A= + union sem_fields {=0A= + struct { /* no operands */=0A= + int empty;=0A= + } fmt_empty;=0A= + struct { /* */=0A= + IADDR i_call;=0A= + } sfmt_bi;=0A= + struct { /* */=0A= + UINT f_csr;=0A= + UINT f_r1;=0A= + } sfmt_wcsr;=0A= + struct { /* */=0A= + UINT f_csr;=0A= + UINT f_r2;=0A= + } sfmt_rcsr;=0A= + struct { /* */=0A= + IADDR i_branch;=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + } sfmt_be;=0A= + struct { /* */=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + UINT f_uimm;=0A= + } sfmt_andi;=0A= + struct { /* */=0A= + INT f_imm;=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + } sfmt_addi;=0A= + struct { /* */=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + UINT f_r2;=0A= + UINT f_user;=0A= + } sfmt_user;=0A= + #if WITH_SCACHE_PBB=0A= + /* Writeback handler. */=0A= + struct {=0A= + /* Pointer to argbuf entry for insn whose results need writing back. = */=0A= + const struct argbuf *abuf;=0A= + } write;=0A= + /* x-before handler */=0A= + struct {=0A= + /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/=0A= + int first_p;=0A= + } before;=0A= + /* x-after handler */=0A= + struct {=0A= + int empty;=0A= + } after;=0A= + /* This entry is used to terminate each pbb. */=0A= + struct {=0A= + /* Number of insns in pbb. */=0A= + int insn_count;=0A= + /* Next pbb to execute. */=0A= + SCACHE *next;=0A= + SCACHE *branch_target;=0A= + } chain;=0A= + #endif=0A= + };=0A= +=20=0A= + /* The ARGBUF struct. */=0A= + struct argbuf {=0A= + /* These are the baseclass definitions. */=0A= + IADDR addr;=0A= + const IDESC *idesc;=0A= + char trace_p;=0A= + char profile_p;=0A= + /* ??? Temporary hack for skip insns. */=0A= + char skip_count;=0A= + char unused;=0A= + /* cpu specific data follows */=0A= + union sem semantic;=0A= + int written;=0A= + union sem_fields fields;=0A= + };=0A= +=20=0A= + /* A cached insn.=0A= +=20=0A= + ??? SCACHE used to contain more than just argbuf. We could delete the= =0A= + type entirely and always just use ARGBUF, but for future concerns and = as=0A= + a level of abstraction it is left in. */=0A= +=20=0A= + struct scache {=0A= + struct argbuf argbuf;=0A= + };=0A= +=20=0A= + /* Macros to simplify extraction, reading and semantic code.=0A= + These define and assign the local vars that contain the insn's fields.= */=0A= +=20=0A= + #define EXTRACT_IFMT_EMPTY_VARS \=0A= + unsigned int length;=0A= + #define EXTRACT_IFMT_EMPTY_CODE \=0A= + length =3D 0; \=0A= +=20=0A= + #define EXTRACT_IFMT_ADD_VARS \=0A= + UINT f_opcode; \=0A= + UINT f_r0; \=0A= + UINT f_r1; \=0A= + UINT f_r2; \=0A= + UINT f_resv0; \=0A= + unsigned int length;=0A= + #define EXTRACT_IFMT_ADD_CODE \=0A= + length =3D 4; \=0A= + f_opcode =3D EXTRACT_LSB0_UINT (insn, 32, 31, 6); \=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5); \=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5); \=0A= + f_r2 =3D EXTRACT_LSB0_UINT (insn, 32, 15, 5); \=0A= + f_resv0 =3D EXTRACT_LSB0_UINT (insn, 32, 10, 11); \=0A= +=20=0A= + #define EXTRACT_IFMT_ADDI_VARS \=0A= + UINT f_opcode; \=0A= + UINT f_r0; \=0A= + UINT f_r1; \=0A= + INT f_imm; \=0A= + unsigned int length;=0A= + #define EXTRACT_IFMT_ADDI_CODE \=0A= + length =3D 4; \=0A= + f_opcode =3D EXTRACT_LSB0_UINT (insn, 32, 31, 6); \=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5); \=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5); \=0A= + f_imm =3D EXTRACT_LSB0_INT (insn, 32, 15, 16); \=0A= +=20=0A= + #define EXTRACT_IFMT_ANDI_VARS \=0A= + UINT f_opcode; \=0A= + UINT f_r0; \=0A= + UINT f_r1; \=0A= + UINT f_uimm; \=0A= + unsigned int length;=0A= + #define EXTRACT_IFMT_ANDI_CODE \=0A= + length =3D 4; \=0A= + f_opcode =3D EXTRACT_LSB0_UINT (insn, 32, 31, 6); \=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5); \=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5); \=0A= + f_uimm =3D EXTRACT_LSB0_UINT (insn, 32, 15, 16); \=0A= +=20=0A= + #define EXTRACT_IFMT_ANDHII_VARS \=0A= + UINT f_opcode; \=0A= + UINT f_r0; \=0A= + UINT f_r1; \=0A= + UINT f_uimm; \=0A= + unsigned int length;=0A= + #define EXTRACT_IFMT_ANDHII_CODE \=0A= + length =3D 4; \=0A= + f_opcode =3D EXTRACT_LSB0_UINT (insn, 32, 31, 6); \=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5); \=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5); \=0A= + f_uimm =3D EXTRACT_LSB0_UINT (insn, 32, 15, 16); \=0A= +=20=0A= + #define EXTRACT_IFMT_B_VARS \=0A= + UINT f_opcode; \=0A= + UINT f_r0; \=0A= + UINT f_r1; \=0A= + UINT f_r2; \=0A= + UINT f_resv0; \=0A= + unsigned int length;=0A= + #define EXTRACT_IFMT_B_CODE \=0A= + length =3D 4; \=0A= + f_opcode =3D EXTRACT_LSB0_UINT (insn, 32, 31, 6); \=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5); \=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5); \=0A= + f_r2 =3D EXTRACT_LSB0_UINT (insn, 32, 15, 5); \=0A= + f_resv0 =3D EXTRACT_LSB0_UINT (insn, 32, 10, 11); \=0A= +=20=0A= + #define EXTRACT_IFMT_BI_VARS \=0A= + UINT f_opcode; \=0A= + SI f_call; \=0A= + unsigned int length;=0A= + #define EXTRACT_IFMT_BI_CODE \=0A= + length =3D 4; \=0A= + f_opcode =3D EXTRACT_LSB0_UINT (insn, 32, 31, 6); \=0A= + f_call =3D ((pc) + (((int) (((EXTRACT_LSB0_INT (insn, 32, 25, 26)) << (= 6))) >> (4)))); \=0A= +=20=0A= + #define EXTRACT_IFMT_BE_VARS \=0A= + UINT f_opcode; \=0A= + UINT f_r0; \=0A= + UINT f_r1; \=0A= + SI f_branch; \=0A= + unsigned int length;=0A= + #define EXTRACT_IFMT_BE_CODE \=0A= + length =3D 4; \=0A= + f_opcode =3D EXTRACT_LSB0_UINT (insn, 32, 31, 6); \=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5); \=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5); \=0A= + f_branch =3D ((pc) + (((int) (((EXTRACT_LSB0_INT (insn, 32, 15, 16)) <<= (16))) >> (14)))); \=0A= +=20=0A= + #define EXTRACT_IFMT_ORI_VARS \=0A= + UINT f_opcode; \=0A= + UINT f_r0; \=0A= + UINT f_r1; \=0A= + UINT f_uimm; \=0A= + unsigned int length;=0A= + #define EXTRACT_IFMT_ORI_CODE \=0A= + length =3D 4; \=0A= + f_opcode =3D EXTRACT_LSB0_UINT (insn, 32, 31, 6); \=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5); \=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5); \=0A= + f_uimm =3D EXTRACT_LSB0_UINT (insn, 32, 15, 16); \=0A= +=20=0A= + #define EXTRACT_IFMT_RCSR_VARS \=0A= + UINT f_opcode; \=0A= + UINT f_csr; \=0A= + UINT f_r1; \=0A= + UINT f_r2; \=0A= + UINT f_resv0; \=0A= + unsigned int length;=0A= + #define EXTRACT_IFMT_RCSR_CODE \=0A= + length =3D 4; \=0A= + f_opcode =3D EXTRACT_LSB0_UINT (insn, 32, 31, 6); \=0A= + f_csr =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5); \=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5); \=0A= + f_r2 =3D EXTRACT_LSB0_UINT (insn, 32, 15, 5); \=0A= + f_resv0 =3D EXTRACT_LSB0_UINT (insn, 32, 10, 11); \=0A= +=20=0A= + #define EXTRACT_IFMT_SEXTB_VARS \=0A= + UINT f_opcode; \=0A= + UINT f_r0; \=0A= + UINT f_r1; \=0A= + UINT f_r2; \=0A= + UINT f_resv0; \=0A= + unsigned int length;=0A= + #define EXTRACT_IFMT_SEXTB_CODE \=0A= + length =3D 4; \=0A= + f_opcode =3D EXTRACT_LSB0_UINT (insn, 32, 31, 6); \=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5); \=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5); \=0A= + f_r2 =3D EXTRACT_LSB0_UINT (insn, 32, 15, 5); \=0A= + f_resv0 =3D EXTRACT_LSB0_UINT (insn, 32, 10, 11); \=0A= +=20=0A= + #define EXTRACT_IFMT_USER_VARS \=0A= + UINT f_opcode; \=0A= + UINT f_r0; \=0A= + UINT f_r1; \=0A= + UINT f_r2; \=0A= + UINT f_user; \=0A= + unsigned int length;=0A= + #define EXTRACT_IFMT_USER_CODE \=0A= + length =3D 4; \=0A= + f_opcode =3D EXTRACT_LSB0_UINT (insn, 32, 31, 6); \=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5); \=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5); \=0A= + f_r2 =3D EXTRACT_LSB0_UINT (insn, 32, 15, 5); \=0A= + f_user =3D EXTRACT_LSB0_UINT (insn, 32, 10, 11); \=0A= +=20=0A= + #define EXTRACT_IFMT_WCSR_VARS \=0A= + UINT f_opcode; \=0A= + UINT f_csr; \=0A= + UINT f_r1; \=0A= + UINT f_r2; \=0A= + UINT f_resv0; \=0A= + unsigned int length;=0A= + #define EXTRACT_IFMT_WCSR_CODE \=0A= + length =3D 4; \=0A= + f_opcode =3D EXTRACT_LSB0_UINT (insn, 32, 31, 6); \=0A= + f_csr =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5); \=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5); \=0A= + f_r2 =3D EXTRACT_LSB0_UINT (insn, 32, 15, 5); \=0A= + f_resv0 =3D EXTRACT_LSB0_UINT (insn, 32, 10, 11); \=0A= +=20=0A= + #define EXTRACT_IFMT_BREAK_VARS \=0A= + UINT f_opcode; \=0A= + UINT f_exception; \=0A= + unsigned int length;=0A= + #define EXTRACT_IFMT_BREAK_CODE \=0A= + length =3D 4; \=0A= + f_opcode =3D EXTRACT_LSB0_UINT (insn, 32, 31, 6); \=0A= + f_exception =3D EXTRACT_LSB0_UINT (insn, 32, 25, 26); \=0A= +=20=0A= + /* Collection of various things for the trace handler to use. */=0A= +=20=0A= + typedef struct trace_record {=0A= + IADDR pc;=0A= + /* FIXME:wip */=0A= + } TRACE_RECORD;=0A= +=20=0A= + #endif /* CPU_LM32BF_H */=0A= Index: sim/lm32/cpuall.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/cpuall.h=0A= diff -N sim/lm32/cpuall.h=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/cpuall.h 20 Dec 2008 22:02:35 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,66 ----=0A= + /* Simulator CPU header for lm32.=0A= +=20=0A= + THIS FILE IS MACHINE GENERATED WITH CGEN.=0A= +=20=0A= + Copyright 1996-2005 Free Software Foundation, Inc.=0A= +=20=0A= + This file is part of the GNU simulators.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 2, or (at your option)=0A= + any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License along= =0A= + with this program; if not, write to the Free Software Foundation, Inc.,= =0A= + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.=0A= +=20=0A= + */=0A= +=20=0A= + #ifndef LM32_CPUALL_H=0A= + #define LM32_CPUALL_H=0A= +=20=0A= + /* Include files for each cpu family. */=0A= +=20=0A= + #ifdef WANT_CPU_LM32BF=0A= + #include "eng.h"=0A= + #include "cgen-engine.h"=0A= + #include "cpu.h"=0A= + #include "decode.h"=0A= + #endif=0A= +=20=0A= + extern const MACH lm32_mach;=0A= +=20=0A= + #ifndef WANT_CPU=0A= + /* The ARGBUF struct. */=0A= + struct argbuf {=0A= + /* These are the baseclass definitions. */=0A= + IADDR addr;=0A= + const IDESC *idesc;=0A= + char trace_p;=0A= + char profile_p;=0A= + /* ??? Temporary hack for skip insns. */=0A= + char skip_count;=0A= + char unused;=0A= + /* cpu specific data follows */=0A= + };=0A= + #endif=0A= +=20=0A= + #ifndef WANT_CPU=0A= + /* A cached insn.=0A= +=20=0A= + ??? SCACHE used to contain more than just argbuf. We could delete the= =0A= + type entirely and always just use ARGBUF, but for future concerns and = as=0A= + a level of abstraction it is left in. */=0A= +=20=0A= + struct scache {=0A= + struct argbuf argbuf;=0A= + };=0A= + #endif=0A= +=20=0A= + #endif /* LM32_CPUALL_H */=0A= Index: sim/lm32/decode.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/decode.c=0A= diff -N sim/lm32/decode.c=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/decode.c 20 Dec 2008 22:02:36 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,955 ----=0A= + /* Simulator instruction decoder for lm32bf.=0A= +=20=0A= + THIS FILE IS MACHINE GENERATED WITH CGEN.=0A= +=20=0A= + Copyright 1996-2005 Free Software Foundation, Inc.=0A= +=20=0A= + This file is part of the GNU simulators.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 2, or (at your option)=0A= + any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License along= =0A= + with this program; if not, write to the Free Software Foundation, Inc.,= =0A= + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.=0A= +=20=0A= + */=0A= +=20=0A= + #define WANT_CPU lm32bf=0A= + #define WANT_CPU_LM32BF=0A= +=20=0A= + #include "sim-main.h"=0A= + #include "sim-assert.h"=0A= +=20=0A= + /* The instruction descriptor array.=0A= + This is computed at runtime. Space for it is not malloc'd to save a= =0A= + teensy bit of cpu in the decoder. Moving it to malloc space is trivia= l=0A= + but won't be done until necessary (we don't currently support the runt= ime=0A= + addition of instructions nor an SMP machine with different cpus). */= =0A= + static IDESC lm32bf_insn_data[LM32BF_INSN__MAX];=0A= +=20=0A= + /* Commas between elements are contained in the macros.=0A= + Some of these are conditionally compiled out. */=0A= +=20=0A= + static const struct insn_sem lm32bf_insn_sem[] =3D=0A= + {=0A= + { VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY },= =0A= + { VIRTUAL_INSN_X_AFTER, LM32BF_INSN_X_AFTER, LM32BF_SFMT_EMPTY },=0A= + { VIRTUAL_INSN_X_BEFORE, LM32BF_INSN_X_BEFORE, LM32BF_SFMT_EMPTY },=0A= + { VIRTUAL_INSN_X_CTI_CHAIN, LM32BF_INSN_X_CTI_CHAIN, LM32BF_SFMT_EMPTY = },=0A= + { VIRTUAL_INSN_X_CHAIN, LM32BF_INSN_X_CHAIN, LM32BF_SFMT_EMPTY },=0A= + { VIRTUAL_INSN_X_BEGIN, LM32BF_INSN_X_BEGIN, LM32BF_SFMT_EMPTY },=0A= + { LM32_INSN_ADD, LM32BF_INSN_ADD, LM32BF_SFMT_ADD },=0A= + { LM32_INSN_ADDI, LM32BF_INSN_ADDI, LM32BF_SFMT_ADDI },=0A= + { LM32_INSN_AND, LM32BF_INSN_AND, LM32BF_SFMT_ADD },=0A= + { LM32_INSN_ANDI, LM32BF_INSN_ANDI, LM32BF_SFMT_ANDI },=0A= + { LM32_INSN_ANDHII, LM32BF_INSN_ANDHII, LM32BF_SFMT_ANDHII },=0A= + { LM32_INSN_B, LM32BF_INSN_B, LM32BF_SFMT_B },=0A= + { LM32_INSN_BI, LM32BF_INSN_BI, LM32BF_SFMT_BI },=0A= + { LM32_INSN_BE, LM32BF_INSN_BE, LM32BF_SFMT_BE },=0A= + { LM32_INSN_BG, LM32BF_INSN_BG, LM32BF_SFMT_BE },=0A= + { LM32_INSN_BGE, LM32BF_INSN_BGE, LM32BF_SFMT_BE },=0A= + { LM32_INSN_BGEU, LM32BF_INSN_BGEU, LM32BF_SFMT_BE },=0A= + { LM32_INSN_BGU, LM32BF_INSN_BGU, LM32BF_SFMT_BE },=0A= + { LM32_INSN_BNE, LM32BF_INSN_BNE, LM32BF_SFMT_BE },=0A= + { LM32_INSN_CALL, LM32BF_INSN_CALL, LM32BF_SFMT_CALL },=0A= + { LM32_INSN_CALLI, LM32BF_INSN_CALLI, LM32BF_SFMT_CALLI },=0A= + { LM32_INSN_CMPE, LM32BF_INSN_CMPE, LM32BF_SFMT_ADD },=0A= + { LM32_INSN_CMPEI, LM32BF_INSN_CMPEI, LM32BF_SFMT_ADDI },=0A= + { LM32_INSN_CMPG, LM32BF_INSN_CMPG, LM32BF_SFMT_ADD },=0A= + { LM32_INSN_CMPGI, LM32BF_INSN_CMPGI, LM32BF_SFMT_ADDI },=0A= + { LM32_INSN_CMPGE, LM32BF_INSN_CMPGE, LM32BF_SFMT_ADD },=0A= + { LM32_INSN_CMPGEI, LM32BF_INSN_CMPGEI, LM32BF_SFMT_ADDI },=0A= + { LM32_INSN_CMPGEU, LM32BF_INSN_CMPGEU, LM32BF_SFMT_ADD },=0A= + { LM32_INSN_CMPGEUI, LM32BF_INSN_CMPGEUI, LM32BF_SFMT_ANDI },=0A= + { LM32_INSN_CMPGU, LM32BF_INSN_CMPGU, LM32BF_SFMT_ADD },=0A= + { LM32_INSN_CMPGUI, LM32BF_INSN_CMPGUI, LM32BF_SFMT_ANDI },=0A= + { LM32_INSN_CMPNE, LM32BF_INSN_CMPNE, LM32BF_SFMT_ADD },=0A= + { LM32_INSN_CMPNEI, LM32BF_INSN_CMPNEI, LM32BF_SFMT_ADDI },=0A= + { LM32_INSN_DIVU, LM32BF_INSN_DIVU, LM32BF_SFMT_DIVU },=0A= + { LM32_INSN_LB, LM32BF_INSN_LB, LM32BF_SFMT_LB },=0A= + { LM32_INSN_LBU, LM32BF_INSN_LBU, LM32BF_SFMT_LB },=0A= + { LM32_INSN_LH, LM32BF_INSN_LH, LM32BF_SFMT_LH },=0A= + { LM32_INSN_LHU, LM32BF_INSN_LHU, LM32BF_SFMT_LH },=0A= + { LM32_INSN_LW, LM32BF_INSN_LW, LM32BF_SFMT_LW },=0A= + { LM32_INSN_MODU, LM32BF_INSN_MODU, LM32BF_SFMT_DIVU },=0A= + { LM32_INSN_MUL, LM32BF_INSN_MUL, LM32BF_SFMT_ADD },=0A= + { LM32_INSN_MULI, LM32BF_INSN_MULI, LM32BF_SFMT_ADDI },=0A= + { LM32_INSN_NOR, LM32BF_INSN_NOR, LM32BF_SFMT_ADD },=0A= + { LM32_INSN_NORI, LM32BF_INSN_NORI, LM32BF_SFMT_ANDI },=0A= + { LM32_INSN_OR, LM32BF_INSN_OR, LM32BF_SFMT_ADD },=0A= + { LM32_INSN_ORI, LM32BF_INSN_ORI, LM32BF_SFMT_ORI },=0A= + { LM32_INSN_ORHII, LM32BF_INSN_ORHII, LM32BF_SFMT_ANDHII },=0A= + { LM32_INSN_RCSR, LM32BF_INSN_RCSR, LM32BF_SFMT_RCSR },=0A= + { LM32_INSN_SB, LM32BF_INSN_SB, LM32BF_SFMT_SB },=0A= + { LM32_INSN_SEXTB, LM32BF_INSN_SEXTB, LM32BF_SFMT_SEXTB },=0A= + { LM32_INSN_SEXTH, LM32BF_INSN_SEXTH, LM32BF_SFMT_SEXTB },=0A= + { LM32_INSN_SH, LM32BF_INSN_SH, LM32BF_SFMT_SH },=0A= + { LM32_INSN_SL, LM32BF_INSN_SL, LM32BF_SFMT_SL },=0A= + { LM32_INSN_SLI, LM32BF_INSN_SLI, LM32BF_SFMT_ADDI },=0A= + { LM32_INSN_SR, LM32BF_INSN_SR, LM32BF_SFMT_SL },=0A= + { LM32_INSN_SRI, LM32BF_INSN_SRI, LM32BF_SFMT_ADDI },=0A= + { LM32_INSN_SRU, LM32BF_INSN_SRU, LM32BF_SFMT_SL },=0A= + { LM32_INSN_SRUI, LM32BF_INSN_SRUI, LM32BF_SFMT_ADDI },=0A= + { LM32_INSN_SUB, LM32BF_INSN_SUB, LM32BF_SFMT_ADD },=0A= + { LM32_INSN_SW, LM32BF_INSN_SW, LM32BF_SFMT_SW },=0A= + { LM32_INSN_USER, LM32BF_INSN_USER, LM32BF_SFMT_USER },=0A= + { LM32_INSN_WCSR, LM32BF_INSN_WCSR, LM32BF_SFMT_WCSR },=0A= + { LM32_INSN_XOR, LM32BF_INSN_XOR, LM32BF_SFMT_ADD },=0A= + { LM32_INSN_XORI, LM32BF_INSN_XORI, LM32BF_SFMT_ANDI },=0A= + { LM32_INSN_XNOR, LM32BF_INSN_XNOR, LM32BF_SFMT_ADD },=0A= + { LM32_INSN_XNORI, LM32BF_INSN_XNORI, LM32BF_SFMT_ANDI },=0A= + { LM32_INSN_BREAK, LM32BF_INSN_BREAK, LM32BF_SFMT_BREAK },=0A= + { LM32_INSN_SCALL, LM32BF_INSN_SCALL, LM32BF_SFMT_BREAK },=0A= + };=0A= +=20=0A= + static const struct insn_sem lm32bf_insn_sem_invalid =3D {=0A= + VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY=0A= + };=0A= +=20=0A= + /* Initialize an IDESC from the compile-time computable parts. */=0A= +=20=0A= + static INLINE void=0A= + init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)=0A= + {=0A= + const CGEN_INSN *insn_table =3D CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu)= )->init_entries;=0A= +=20=0A= + id->num =3D t->index;=0A= + id->sfmt =3D t->sfmt;=0A= + if ((int) t->type <=3D 0)=0A= + id->idata =3D & cgen_virtual_insn_table[- (int) t->type];=0A= + else=0A= + id->idata =3D & insn_table[t->type];=0A= + id->attrs =3D CGEN_INSN_ATTRS (id->idata);=0A= + /* Oh my god, a magic number. */=0A= + id->length =3D CGEN_INSN_BITSIZE (id->idata) / 8;=0A= +=20=0A= + #if WITH_PROFILE_MODEL_P=0A= + id->timing =3D & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];=0A= + {=0A= + SIM_DESC sd =3D CPU_STATE (cpu);=0A= + SIM_ASSERT (t->index =3D=3D id->timing->num);=0A= + }=0A= + #endif=0A= +=20=0A= + /* Semantic pointers are initialized elsewhere. */=0A= + }=0A= +=20=0A= + /* Initialize the instruction descriptor table. */=0A= +=20=0A= + void=0A= + lm32bf_init_idesc_table (SIM_CPU *cpu)=0A= + {=0A= + IDESC *id,*tabend;=0A= + const struct insn_sem *t,*tend;=0A= + int tabsize =3D LM32BF_INSN__MAX;=0A= + IDESC *table =3D lm32bf_insn_data;=0A= +=20=0A= + memset (table, 0, tabsize * sizeof (IDESC));=0A= +=20=0A= + /* First set all entries to the `invalid insn'. */=0A= + t =3D & lm32bf_insn_sem_invalid;=0A= + for (id =3D table, tabend =3D table + tabsize; id < tabend; ++id)=0A= + init_idesc (cpu, id, t);=0A= +=20=0A= + /* Now fill in the values for the chosen cpu. */=0A= + for (t =3D lm32bf_insn_sem, tend =3D t + sizeof (lm32bf_insn_sem) / siz= eof (*t);=0A= + t !=3D tend; ++t)=0A= + {=0A= + init_idesc (cpu, & table[t->index], t);=0A= + }=0A= +=20=0A= + /* Link the IDESC table into the cpu. */=0A= + CPU_IDESC (cpu) =3D table;=0A= + }=0A= +=20=0A= + /* Given an instruction, return a pointer to its IDESC entry. */=0A= +=20=0A= + const IDESC *=0A= + lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,=0A= + CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,=0A= + ARGBUF *abuf)=0A= + {=0A= + /* Result of decoder. */=0A= + LM32BF_INSN_TYPE itype;=0A= +=20=0A= + {=0A= + CGEN_INSN_INT insn =3D base_insn;=0A= +=20=0A= + {=0A= + unsigned int val =3D (((insn >> 26) & (63 << 0)));=0A= + switch (val)=0A= + {=0A= + case 0 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x0)=0A= + { itype =3D LM32BF_INSN_SRUI; goto extract_sfmt_addi; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 1 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x4000000)=0A= + { itype =3D LM32BF_INSN_NORI; goto extract_sfmt_andi; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 2 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x8000000)=0A= + { itype =3D LM32BF_INSN_MULI; goto extract_sfmt_addi; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 3 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0xc000000)=0A= + { itype =3D LM32BF_INSN_SH; goto extract_sfmt_sh; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 4 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x10000000)=0A= + { itype =3D LM32BF_INSN_LB; goto extract_sfmt_lb; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 5 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x14000000)=0A= + { itype =3D LM32BF_INSN_SRI; goto extract_sfmt_addi; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 6 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x18000000)=0A= + { itype =3D LM32BF_INSN_XORI; goto extract_sfmt_andi; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 7 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x1c000000)=0A= + { itype =3D LM32BF_INSN_LH; goto extract_sfmt_lh; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 8 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x20000000)=0A= + { itype =3D LM32BF_INSN_ANDI; goto extract_sfmt_andi; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 9 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x24000000)=0A= + { itype =3D LM32BF_INSN_XNORI; goto extract_sfmt_andi; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 10 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x28000000)=0A= + { itype =3D LM32BF_INSN_LW; goto extract_sfmt_lw; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 11 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x2c000000)=0A= + { itype =3D LM32BF_INSN_LHU; goto extract_sfmt_lh; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 12 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x30000000)=0A= + { itype =3D LM32BF_INSN_SB; goto extract_sfmt_sb; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 13 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x34000000)=0A= + { itype =3D LM32BF_INSN_ADDI; goto extract_sfmt_addi; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 14 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x38000000)=0A= + { itype =3D LM32BF_INSN_ORI; goto extract_sfmt_ori; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 15 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x3c000000)=0A= + { itype =3D LM32BF_INSN_SLI; goto extract_sfmt_addi; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 16 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x40000000)=0A= + { itype =3D LM32BF_INSN_LBU; goto extract_sfmt_lb; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 17 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x44000000)=0A= + { itype =3D LM32BF_INSN_BE; goto extract_sfmt_be; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 18 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x48000000)=0A= + { itype =3D LM32BF_INSN_BG; goto extract_sfmt_be; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 19 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x4c000000)=0A= + { itype =3D LM32BF_INSN_BGE; goto extract_sfmt_be; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 20 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x50000000)=0A= + { itype =3D LM32BF_INSN_BGEU; goto extract_sfmt_be; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 21 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x54000000)=0A= + { itype =3D LM32BF_INSN_BGU; goto extract_sfmt_be; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 22 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x58000000)=0A= + { itype =3D LM32BF_INSN_SW; goto extract_sfmt_sw; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 23 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x5c000000)=0A= + { itype =3D LM32BF_INSN_BNE; goto extract_sfmt_be; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 24 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x60000000)=0A= + { itype =3D LM32BF_INSN_ANDHII; goto extract_sfmt_andhii; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 25 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x64000000)=0A= + { itype =3D LM32BF_INSN_CMPEI; goto extract_sfmt_addi; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 26 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x68000000)=0A= + { itype =3D LM32BF_INSN_CMPGI; goto extract_sfmt_addi; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 27 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x6c000000)=0A= + { itype =3D LM32BF_INSN_CMPGEI; goto extract_sfmt_addi; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 28 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x70000000)=0A= + { itype =3D LM32BF_INSN_CMPGEUI; goto extract_sfmt_andi; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 29 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x74000000)=0A= + { itype =3D LM32BF_INSN_CMPGUI; goto extract_sfmt_andi; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 30 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x78000000)=0A= + { itype =3D LM32BF_INSN_ORHII; goto extract_sfmt_andhii; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 31 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0x7c000000)=0A= + { itype =3D LM32BF_INSN_CMPNEI; goto extract_sfmt_addi; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 32 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0x80000000)=0A= + { itype =3D LM32BF_INSN_SRU; goto extract_sfmt_sl; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 33 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0x84000000)=0A= + { itype =3D LM32BF_INSN_NOR; goto extract_sfmt_add; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 34 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0x88000000)=0A= + { itype =3D LM32BF_INSN_MUL; goto extract_sfmt_add; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 35 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0x8c000000)=0A= + { itype =3D LM32BF_INSN_DIVU; goto extract_sfmt_divu; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 36 :=0A= + if ((entire_insn & 0xfc1f07ff) =3D=3D 0x90000000)=0A= + { itype =3D LM32BF_INSN_RCSR; goto extract_sfmt_rcsr; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 37 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0x94000000)=0A= + { itype =3D LM32BF_INSN_SR; goto extract_sfmt_sl; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 38 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0x98000000)=0A= + { itype =3D LM32BF_INSN_XOR; goto extract_sfmt_add; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 40 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0xa0000000)=0A= + { itype =3D LM32BF_INSN_AND; goto extract_sfmt_add; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 41 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0xa4000000)=0A= + { itype =3D LM32BF_INSN_XNOR; goto extract_sfmt_add; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 43 :=0A= + {=0A= + unsigned int val =3D (((insn >> 1) & (1 << 1)) | ((insn >> 0) &= (1 << 0)));=0A= + switch (val)=0A= + {=0A= + case 0 :=0A= + if ((entire_insn & 0xffffffff) =3D=3D 0xac000002)=0A= + { itype =3D LM32BF_INSN_BREAK; goto extract_sfmt_break; }= =0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 3 :=0A= + if ((entire_insn & 0xffffffff) =3D=3D 0xac000007)=0A= + { itype =3D LM32BF_INSN_SCALL; goto extract_sfmt_break; }= =0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + default : itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_em= pty;=0A= + }=0A= + }=0A= + case 44 :=0A= + if ((entire_insn & 0xfc1f07ff) =3D=3D 0xb0000000)=0A= + { itype =3D LM32BF_INSN_SEXTB; goto extract_sfmt_sextb; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 45 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0xb4000000)=0A= + { itype =3D LM32BF_INSN_ADD; goto extract_sfmt_add; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 46 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0xb8000000)=0A= + { itype =3D LM32BF_INSN_OR; goto extract_sfmt_add; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 47 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0xbc000000)=0A= + { itype =3D LM32BF_INSN_SL; goto extract_sfmt_sl; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 48 :=0A= + if ((entire_insn & 0xfc1fffff) =3D=3D 0xc0000000)=0A= + { itype =3D LM32BF_INSN_B; goto extract_sfmt_b; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 49 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0xc4000000)=0A= + { itype =3D LM32BF_INSN_MODU; goto extract_sfmt_divu; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 50 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0xc8000000)=0A= + { itype =3D LM32BF_INSN_SUB; goto extract_sfmt_add; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 51 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0xcc000000)=0A= + { itype =3D LM32BF_INSN_USER; goto extract_sfmt_user; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 52 :=0A= + if ((entire_insn & 0xfc00ffff) =3D=3D 0xd0000000)=0A= + { itype =3D LM32BF_INSN_WCSR; goto extract_sfmt_wcsr; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 54 :=0A= + if ((entire_insn & 0xfc1fffff) =3D=3D 0xd8000000)=0A= + { itype =3D LM32BF_INSN_CALL; goto extract_sfmt_call; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 55 :=0A= + if ((entire_insn & 0xfc1f07ff) =3D=3D 0xdc000000)=0A= + { itype =3D LM32BF_INSN_SEXTH; goto extract_sfmt_sextb; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 56 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0xe0000000)=0A= + { itype =3D LM32BF_INSN_BI; goto extract_sfmt_bi; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 57 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0xe4000000)=0A= + { itype =3D LM32BF_INSN_CMPE; goto extract_sfmt_add; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 58 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0xe8000000)=0A= + { itype =3D LM32BF_INSN_CMPG; goto extract_sfmt_add; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 59 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0xec000000)=0A= + { itype =3D LM32BF_INSN_CMPGE; goto extract_sfmt_add; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 60 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0xf0000000)=0A= + { itype =3D LM32BF_INSN_CMPGEU; goto extract_sfmt_add; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 61 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0xf4000000)=0A= + { itype =3D LM32BF_INSN_CMPGU; goto extract_sfmt_add; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 62 :=0A= + if ((entire_insn & 0xfc000000) =3D=3D 0xf8000000)=0A= + { itype =3D LM32BF_INSN_CALLI; goto extract_sfmt_calli; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + case 63 :=0A= + if ((entire_insn & 0xfc0007ff) =3D=3D 0xfc000000)=0A= + { itype =3D LM32BF_INSN_CMPNE; goto extract_sfmt_add; }=0A= + itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;=0A= + default : itype =3D LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;= =0A= + }=0A= + }=0A= + }=0A= +=20=0A= + /* The instruction has been decoded, now extract the fields. */=0A= +=20=0A= + extract_sfmt_empty:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= +=20=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char= *) 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_add:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + UINT f_r2;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5);=0A= + f_r2 =3D EXTRACT_LSB0_UINT (insn, 32, 15, 5);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_r0) =3D f_r0;=0A= + FLD (f_r1) =3D f_r1;=0A= + FLD (f_r2) =3D f_r2;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r0 0= x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, (char *) 0= ));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_addi:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + INT f_imm;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5);=0A= + f_imm =3D EXTRACT_LSB0_INT (insn, 32, 15, 16);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_imm) =3D f_imm;=0A= + FLD (f_r0) =3D f_r0;=0A= + FLD (f_r1) =3D f_r1;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_imm= 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *= ) 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_andi:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + UINT f_uimm;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5);=0A= + f_uimm =3D EXTRACT_LSB0_UINT (insn, 32, 15, 16);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_r0) =3D f_r0;=0A= + FLD (f_uimm) =3D f_uimm;=0A= + FLD (f_r1) =3D f_r1;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andi", "f_r0 = 0x%x", 'x', f_r0, "f_uimm 0x%x", 'x', f_uimm, "f_r1 0x%x", 'x', f_r1, (char= *) 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_andhii:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + UINT f_uimm;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5);=0A= + f_uimm =3D EXTRACT_LSB0_UINT (insn, 32, 15, 16);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_uimm) =3D f_uimm;=0A= + FLD (f_r0) =3D f_r0;=0A= + FLD (f_r1) =3D f_r1;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andhii", "f_u= imm 0x%x", 'x', f_uimm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (ch= ar *) 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_b:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + UINT f_r0;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_r0) =3D f_r0;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_b", "f_r0 0x%= x", 'x', f_r0, (char *) 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_bi:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_bi.f=0A= + SI f_call;=0A= +=20=0A= + f_call =3D ((pc) + (((int) (((EXTRACT_LSB0_INT (insn, 32, 25, 26)) <<= (6))) >> (4))));=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (i_call) =3D f_call;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bi", "call 0x= %x", 'x', f_call, (char *) 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_be:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + SI f_branch;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5);=0A= + f_branch =3D ((pc) + (((int) (((EXTRACT_LSB0_INT (insn, 32, 15, 16)) = << (16))) >> (14))));=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_r0) =3D f_r0;=0A= + FLD (f_r1) =3D f_r1;=0A= + FLD (i_branch) =3D f_branch;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_be", "f_r0 0x= %x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, "branch 0x%x", 'x', f_branch, (char= *) 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_call:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + UINT f_r0;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_r0) =3D f_r0;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_call", "f_r0 = 0x%x", 'x', f_r0, (char *) 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_calli:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_bi.f=0A= + SI f_call;=0A= +=20=0A= + f_call =3D ((pc) + (((int) (((EXTRACT_LSB0_INT (insn, 32, 25, 26)) <<= (6))) >> (4))));=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (i_call) =3D f_call;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_calli", "call= 0x%x", 'x', f_call, (char *) 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_divu:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + UINT f_r2;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5);=0A= + f_r2 =3D EXTRACT_LSB0_UINT (insn, 32, 15, 5);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_r0) =3D f_r0;=0A= + FLD (f_r1) =3D f_r1;=0A= + FLD (f_r2) =3D f_r2;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divu", "f_r0 = 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, (char *) = 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_lb:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + INT f_imm;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5);=0A= + f_imm =3D EXTRACT_LSB0_INT (insn, 32, 15, 16);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_imm) =3D f_imm;=0A= + FLD (f_r0) =3D f_r0;=0A= + FLD (f_r1) =3D f_r1;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lb", "f_imm 0= x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) = 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_lh:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + INT f_imm;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5);=0A= + f_imm =3D EXTRACT_LSB0_INT (insn, 32, 15, 16);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_imm) =3D f_imm;=0A= + FLD (f_r0) =3D f_r0;=0A= + FLD (f_r1) =3D f_r1;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lh", "f_imm 0= x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) = 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_lw:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + INT f_imm;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5);=0A= + f_imm =3D EXTRACT_LSB0_INT (insn, 32, 15, 16);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_imm) =3D f_imm;=0A= + FLD (f_r0) =3D f_r0;=0A= + FLD (f_r1) =3D f_r1;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lw", "f_imm 0= x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) = 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_ori:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + UINT f_uimm;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5);=0A= + f_uimm =3D EXTRACT_LSB0_UINT (insn, 32, 15, 16);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_uimm) =3D f_uimm;=0A= + FLD (f_r0) =3D f_r0;=0A= + FLD (f_r1) =3D f_r1;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ori", "f_uimm= 0x%x", 'x', f_uimm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char = *) 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_rcsr:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_rcsr.f=0A= + UINT f_csr;=0A= + UINT f_r2;=0A= +=20=0A= + f_csr =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r2 =3D EXTRACT_LSB0_UINT (insn, 32, 15, 5);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_csr) =3D f_csr;=0A= + FLD (f_r2) =3D f_r2;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rcsr", "f_csr= 0x%x", 'x', f_csr, "f_r2 0x%x", 'x', f_r2, (char *) 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_sb:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + INT f_imm;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5);=0A= + f_imm =3D EXTRACT_LSB0_INT (insn, 32, 15, 16);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_imm) =3D f_imm;=0A= + FLD (f_r0) =3D f_r0;=0A= + FLD (f_r1) =3D f_r1;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sb", "f_imm 0= x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) = 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_sextb:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + UINT f_r0;=0A= + UINT f_r2;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r2 =3D EXTRACT_LSB0_UINT (insn, 32, 15, 5);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_r0) =3D f_r0;=0A= + FLD (f_r2) =3D f_r2;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sextb", "f_r0= 0x%x", 'x', f_r0, "f_r2 0x%x", 'x', f_r2, (char *) 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_sh:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + INT f_imm;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5);=0A= + f_imm =3D EXTRACT_LSB0_INT (insn, 32, 15, 16);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_imm) =3D f_imm;=0A= + FLD (f_r0) =3D f_r0;=0A= + FLD (f_r1) =3D f_r1;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sh", "f_imm 0= x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) = 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_sl:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + UINT f_r2;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5);=0A= + f_r2 =3D EXTRACT_LSB0_UINT (insn, 32, 15, 5);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_r0) =3D f_r0;=0A= + FLD (f_r1) =3D f_r1;=0A= + FLD (f_r2) =3D f_r2;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sl", "f_r0 0x= %x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, (char *) 0)= );=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_sw:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + INT f_imm;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5);=0A= + f_imm =3D EXTRACT_LSB0_INT (insn, 32, 15, 16);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_imm) =3D f_imm;=0A= + FLD (f_r0) =3D f_r0;=0A= + FLD (f_r1) =3D f_r1;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sw", "f_imm 0= x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) = 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_user:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + UINT f_r0;=0A= + UINT f_r1;=0A= + UINT f_r2;=0A= + UINT f_user;=0A= +=20=0A= + f_r0 =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5);=0A= + f_r2 =3D EXTRACT_LSB0_UINT (insn, 32, 15, 5);=0A= + f_user =3D EXTRACT_LSB0_UINT (insn, 32, 10, 11);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_r0) =3D f_r0;=0A= + FLD (f_r1) =3D f_r1;=0A= + FLD (f_user) =3D f_user;=0A= + FLD (f_r2) =3D f_r2;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_user", "f_r0 = 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, "f_user 0x%x", 'x', f_user, "f_r2= 0x%x", 'x', f_r2, (char *) 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_wcsr:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + CGEN_INSN_INT insn =3D entire_insn;=0A= + #define FLD(f) abuf->fields.sfmt_wcsr.f=0A= + UINT f_csr;=0A= + UINT f_r1;=0A= +=20=0A= + f_csr =3D EXTRACT_LSB0_UINT (insn, 32, 25, 5);=0A= + f_r1 =3D EXTRACT_LSB0_UINT (insn, 32, 20, 5);=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + FLD (f_csr) =3D f_csr;=0A= + FLD (f_r1) =3D f_r1;=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_wcsr", "f_csr= 0x%x", 'x', f_csr, "f_r1 0x%x", 'x', f_r1, (char *) 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + extract_sfmt_break:=0A= + {=0A= + const IDESC *idesc =3D &lm32bf_insn_data[itype];=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= +=20=0A= +=20=0A= + /* Record the fields for the semantic handler. */=0A= + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_break", (char= *) 0));=0A= +=20=0A= + #undef FLD=0A= + return idesc;=0A= + }=0A= +=20=0A= + }=0A= Index: sim/lm32/decode.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/decode.h=0A= diff -N sim/lm32/decode.h=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/decode.h 20 Dec 2008 22:02:36 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,76 ----=0A= + /* Decode header for lm32bf.=0A= +=20=0A= + THIS FILE IS MACHINE GENERATED WITH CGEN.=0A= +=20=0A= + Copyright 1996-2005 Free Software Foundation, Inc.=0A= +=20=0A= + This file is part of the GNU simulators.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 2, or (at your option)=0A= + any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License along= =0A= + with this program; if not, write to the Free Software Foundation, Inc.,= =0A= + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.=0A= +=20=0A= + */=0A= +=20=0A= + #ifndef LM32BF_DECODE_H=0A= + #define LM32BF_DECODE_H=0A= +=20=0A= + extern const IDESC *lm32bf_decode (SIM_CPU *, IADDR,=0A= + CGEN_INSN_INT, CGEN_INSN_INT,=0A= + ARGBUF *);=0A= + extern void lm32bf_init_idesc_table (SIM_CPU *);=0A= + extern void lm32bf_sem_init_idesc_table (SIM_CPU *);=0A= + extern void lm32bf_semf_init_idesc_table (SIM_CPU *);=0A= +=20=0A= + /* Enum declaration for instructions in cpu family lm32bf. */=0A= + typedef enum lm32bf_insn_type {=0A= + LM32BF_INSN_X_INVALID, LM32BF_INSN_X_AFTER, LM32BF_INSN_X_BEFORE, LM32B= F_INSN_X_CTI_CHAIN=0A= + , LM32BF_INSN_X_CHAIN, LM32BF_INSN_X_BEGIN, LM32BF_INSN_ADD, LM32BF_INSN= _ADDI=0A= + , LM32BF_INSN_AND, LM32BF_INSN_ANDI, LM32BF_INSN_ANDHII, LM32BF_INSN_B= =0A= + , LM32BF_INSN_BI, LM32BF_INSN_BE, LM32BF_INSN_BG, LM32BF_INSN_BGE=0A= + , LM32BF_INSN_BGEU, LM32BF_INSN_BGU, LM32BF_INSN_BNE, LM32BF_INSN_CALL= =0A= + , LM32BF_INSN_CALLI, LM32BF_INSN_CMPE, LM32BF_INSN_CMPEI, LM32BF_INSN_CM= PG=0A= + , LM32BF_INSN_CMPGI, LM32BF_INSN_CMPGE, LM32BF_INSN_CMPGEI, LM32BF_INSN_= CMPGEU=0A= + , LM32BF_INSN_CMPGEUI, LM32BF_INSN_CMPGU, LM32BF_INSN_CMPGUI, LM32BF_INS= N_CMPNE=0A= + , LM32BF_INSN_CMPNEI, LM32BF_INSN_DIVU, LM32BF_INSN_LB, LM32BF_INSN_LBU= =0A= + , LM32BF_INSN_LH, LM32BF_INSN_LHU, LM32BF_INSN_LW, LM32BF_INSN_MODU=0A= + , LM32BF_INSN_MUL, LM32BF_INSN_MULI, LM32BF_INSN_NOR, LM32BF_INSN_NORI= =0A= + , LM32BF_INSN_OR, LM32BF_INSN_ORI, LM32BF_INSN_ORHII, LM32BF_INSN_RCSR= =0A= + , LM32BF_INSN_SB, LM32BF_INSN_SEXTB, LM32BF_INSN_SEXTH, LM32BF_INSN_SH= =0A= + , LM32BF_INSN_SL, LM32BF_INSN_SLI, LM32BF_INSN_SR, LM32BF_INSN_SRI=0A= + , LM32BF_INSN_SRU, LM32BF_INSN_SRUI, LM32BF_INSN_SUB, LM32BF_INSN_SW=0A= + , LM32BF_INSN_USER, LM32BF_INSN_WCSR, LM32BF_INSN_XOR, LM32BF_INSN_XORI= =0A= + , LM32BF_INSN_XNOR, LM32BF_INSN_XNORI, LM32BF_INSN_BREAK, LM32BF_INSN_SC= ALL=0A= + , LM32BF_INSN__MAX=0A= + } LM32BF_INSN_TYPE;=0A= +=20=0A= + /* Enum declaration for semantic formats in cpu family lm32bf. */=0A= + typedef enum lm32bf_sfmt_type {=0A= + LM32BF_SFMT_EMPTY, LM32BF_SFMT_ADD, LM32BF_SFMT_ADDI, LM32BF_SFMT_ANDI= =0A= + , LM32BF_SFMT_ANDHII, LM32BF_SFMT_B, LM32BF_SFMT_BI, LM32BF_SFMT_BE=0A= + , LM32BF_SFMT_CALL, LM32BF_SFMT_CALLI, LM32BF_SFMT_DIVU, LM32BF_SFMT_LB= =0A= + , LM32BF_SFMT_LH, LM32BF_SFMT_LW, LM32BF_SFMT_ORI, LM32BF_SFMT_RCSR=0A= + , LM32BF_SFMT_SB, LM32BF_SFMT_SEXTB, LM32BF_SFMT_SH, LM32BF_SFMT_SL=0A= + , LM32BF_SFMT_SW, LM32BF_SFMT_USER, LM32BF_SFMT_WCSR, LM32BF_SFMT_BREAK= =0A= + } LM32BF_SFMT_TYPE;=0A= +=20=0A= + /* Function unit handlers (user written). */=0A= +=20=0A= + extern int lm32bf_model_lm32_u_exec (SIM_CPU *, const IDESC *, int /*unit= _num*/, int /*referenced*/);=0A= +=20=0A= + /* Profiling before/after handlers (user written) */=0A= +=20=0A= + extern void lm32bf_model_insn_before (SIM_CPU *, int /*first_p*/);=0A= + extern void lm32bf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cyc= les*/);=0A= +=20=0A= + #endif /* LM32BF_DECODE_H */=0A= Index: sim/lm32/dv-lm32cpu.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/dv-lm32cpu.c=0A= diff -N sim/lm32/dv-lm32cpu.c=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/dv-lm32cpu.c 20 Dec 2008 22:02:36 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,239 ----=0A= + /* Lattice Mico32 CPU model.=0A= + Contributed by Jon Beniston =0A= +=20=0A= + This file is part of GDB.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify= =0A= + it under the terms of the GNU General Public License as published by= =0A= + the Free Software Foundation; either version 3 of the License, or=0A= + (at your option) any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program. If not, see . = */=0A= +=20=0A= + #include "hw-main.h"=0A= + #include "sim-main.h"=0A= +=20=0A= +=20=0A= + struct lm32cpu {=0A= + struct hw_event* event;=0A= + };=0A= +=20=0A= + /* input port ID's */=20=0A= +=20=0A= + enum {=0A= + INT0_PORT,=20=0A= + INT1_PORT,=20=0A= + INT2_PORT,=20=0A= + INT3_PORT,=0A= + INT4_PORT,=20=0A= + INT5_PORT,=20=0A= + INT6_PORT,=20=0A= + INT7_PORT,=0A= + INT8_PORT,=20=0A= + INT9_PORT,=20=0A= + INT10_PORT,=20=0A= + INT11_PORT,=0A= + INT12_PORT,=0A= + INT13_PORT,=0A= + INT14_PORT,=0A= + INT15_PORT,=0A= + INT16_PORT,=0A= + INT17_PORT,=0A= + INT18_PORT,=0A= + INT19_PORT,=0A= + INT20_PORT,=0A= + INT21_PORT,=0A= + INT22_PORT,=0A= + INT23_PORT,=0A= + INT24_PORT,=0A= + INT25_PORT,=0A= + INT26_PORT,=0A= + INT27_PORT,=0A= + INT28_PORT,=0A= + INT29_PORT,=0A= + INT30_PORT,=0A= + INT31_PORT,=0A= + };=0A= +=20=0A= + static const struct hw_port_descriptor lm32cpu_ports[] =3D {=0A= + /* interrupt inputs */=0A= + { "int0", INT0_PORT, 0, input_port, },=0A= + { "int1", INT1_PORT, 0, input_port, },=0A= + { "int2", INT2_PORT, 0, input_port, },=0A= + { "int3", INT3_PORT, 0, input_port, },=0A= + { "int4", INT4_PORT, 0, input_port, },=0A= + { "int5", INT5_PORT, 0, input_port, },=0A= + { "int6", INT6_PORT, 0, input_port, },=0A= + { "int7", INT7_PORT, 0, input_port, },=0A= + { "int8", INT8_PORT, 0, input_port, },=0A= + { "int9", INT9_PORT, 0, input_port, },=0A= + { "int10", INT10_PORT, 0, input_port, },=0A= + { "int11", INT11_PORT, 0, input_port, },=0A= + { "int12", INT12_PORT, 0, input_port, },=0A= + { "int13", INT13_PORT, 0, input_port, },=0A= + { "int14", INT14_PORT, 0, input_port, },=0A= + { "int15", INT15_PORT, 0, input_port, },=0A= + { "int16", INT16_PORT, 0, input_port, },=0A= + { "int17", INT17_PORT, 0, input_port, },=0A= + { "int18", INT18_PORT, 0, input_port, },=0A= + { "int19", INT19_PORT, 0, input_port, },=0A= + { "int20", INT20_PORT, 0, input_port, },=0A= + { "int21", INT21_PORT, 0, input_port, },=0A= + { "int22", INT22_PORT, 0, input_port, },=0A= + { "int23", INT23_PORT, 0, input_port, },=0A= + { "int24", INT24_PORT, 0, input_port, },=0A= + { "int25", INT25_PORT, 0, input_port, },=0A= + { "int26", INT26_PORT, 0, input_port, },=0A= + { "int27", INT27_PORT, 0, input_port, },=0A= + { "int28", INT28_PORT, 0, input_port, },=0A= + { "int29", INT29_PORT, 0, input_port, },=0A= + { "int30", INT30_PORT, 0, input_port, },=0A= + { "int31", INT31_PORT, 0, input_port, },=0A= + { NULL, },=0A= + };=0A= +=20=0A= +=20=0A= +=20=0A= + /*=0A= + * Finish off the partially created hw device. Attach our local=0A= + * callbacks. Wire up our port names etc=20=0A= + */=0A= + static hw_port_event_method lm32cpu_port_event;=0A= +=20=0A= +=20=0A= + static void=0A= + lm32cpu_finish (struct hw *me)=0A= + {=0A= + struct lm32cpu *controller;=0A= +=20=0A= + controller =3D HW_ZALLOC (me, struct lm32cpu);=0A= + set_hw_data (me, controller);=0A= + set_hw_ports (me, lm32cpu_ports);=0A= + set_hw_port_event (me, lm32cpu_port_event);=0A= +=20=0A= + /* Initialize the pending interrupt flags */=0A= + controller->event =3D NULL;=0A= + }=0A= +=20=0A= +=20=0A= + /* An event arrives on an interrupt port */=0A= + static unsigned int s_ui_ExtIntrs =3D 0;=0A= +=20=0A= +=20=0A= + static void=0A= + deliver_lm32cpu_interrupt (struct hw *me,=0A= + void *data)=0A= + {=0A= + static unsigned int ip, im, im_and_ip_result;=0A= + struct lm32cpu *controller =3D hw_data (me);=0A= + SIM_DESC sd =3D hw_system (me);=0A= + sim_cpu *cpu =3D STATE_CPU (sd, 0); /* NB: fix CPU 0. */=0A= + address_word cia =3D CIA_GET (cpu);=0A= + int interrupt =3D (int)data;=0A= +=20=0A= +=20=0A= + HW_TRACE ((me, "interrupt-check event"));=0A= +=20=0A= +=20=0A= + /*=0A= + * Determine if an external interrupt is active=20=0A= + * and needs to cause an exception=0A= + */=0A= + im =3D lm32bf_h_csr_get(cpu, LM32_CSR_IM);=0A= + ip =3D lm32bf_h_csr_get(cpu, LM32_CSR_IP);=0A= + im_and_ip_result =3D im & ip;=0A= +=20=0A= +=20=0A= + if ((lm32bf_h_csr_get (cpu, LM32_CSR_IE) & 1) && (im_and_ip_result !=3D= 0)){=0A= + /* Save PC in exception address register */=0A= + lm32bf_h_gr_set (cpu, 30, lm32bf_h_pc_get (cpu));=0A= + /* Restart at interrupt offset in handler exception table */=0A= + lm32bf_h_pc_set (cpu, lm32bf_h_csr_get (cpu, LM32_CSR_EBA) + LM32_EID= _INTERRUPT * 32);=0A= + /* Save interrupt enable and then clear */=0A= + lm32bf_h_csr_set (cpu, LM32_CSR_IE, 0x2);=0A= + }=0A= +=20=0A= + /* reschedule soon */=0A= + if(controller->event !=3D NULL)=0A= + hw_event_queue_deschedule(me, controller->event);=0A= + controller->event =3D NULL;=0A= +=20=0A= +=20=0A= + /* if there are external interrupts, schedule an interrupt-check again.= =0A= + * NOTE: THIS MAKES IT VERY INEFFICIENT. INSTEAD, TRIGGER THIS=0A= + * CHECk_EVENT WHEN THE USER ENABLES IE OR USER MODIFIES IM REGISTERS.= =0A= + */=0A= + if(s_ui_ExtIntrs !=3D 0)=0A= + controller->event =3D hw_event_queue_schedule (me, 1, deliver_lm32cpu= _interrupt, data);=0A= + }=0A= +=20=0A= +=20=0A= +=20=0A= + /* Handle an event on one of the CPU's ports. */=0A= + static void=0A= + lm32cpu_port_event (struct hw *me,=0A= + int my_port,=0A= + struct hw *source,=0A= + int source_port,=0A= + int level)=0A= + {=0A= + struct lm32cpu *controller =3D hw_data (me);=0A= + SIM_DESC sd =3D hw_system (me);=0A= + sim_cpu *cpu =3D STATE_CPU (sd, 0); /* NB: fix CPU 0. */=0A= + address_word cia =3D CIA_GET (cpu);=0A= +=20=0A= +=20=0A= + HW_TRACE ((me, "interrupt event on port %d, level %d", my_port, level))= ;=0A= +=20=0A= +=20=0A= +=20=0A= + /*=20=0A= + * Activate IP if the interrupt's activated; don't do anything if=0A= + * the interrupt's deactivated.=0A= + */=0A= + if(level =3D=3D 1){=0A= + /*=0A= + * save state of external interrupt=0A= + */=0A= + s_ui_ExtIntrs |=3D (1 << my_port);=0A= +=20=0A= + /* interrupt-activated so set IP */=0A= + lm32bf_h_csr_set (cpu, LM32_CSR_IP,=20=0A= + lm32bf_h_csr_get (cpu, LM32_CSR_IP) | (1 << my_po= rt));=0A= +=20=0A= + /*=20=0A= + * Since interrupt is activated, queue an immediate event=0A= + * to check if this interrupt is serviceable=0A= + */=0A= + if(controller->event !=3D NULL)=0A= + hw_event_queue_deschedule(me, controller->event);=0A= +=20=0A= +=20=0A= + /*=20=0A= + * Queue an immediate event to check if this interrupt must be servi= ced;=0A= + * this will happen after the current instruction is complete=0A= + */=0A= + controller->event =3D hw_event_queue_schedule ( me,=0A= + 0,=0A= + deliver_lm32cpu_inter= rupt,=0A= + 0);=0A= + }else{=0A= + /*=0A= + * save state of external interrupt=0A= + */=0A= + s_ui_ExtIntrs &=3D ~(1 << my_port);=0A= + }=0A= + }=0A= +=20=0A= +=20=0A= + const struct hw_descriptor dv_lm32cpu_descriptor[] =3D {=0A= + { "lm32cpu", lm32cpu_finish, },=0A= + { NULL },=0A= + };=0A= +=20=0A= Index: sim/lm32/dv-lm32timer.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/dv-lm32timer.c=0A= diff -N sim/lm32/dv-lm32timer.c=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/dv-lm32timer.c 20 Dec 2008 22:02:36 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,228 ----=0A= + /* Lattice Mico32 timer model.=0A= + Contributed by Jon Beniston =0A= +=20=20=20=20=20=0A= + This file is part of GDB.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify= =0A= + it under the terms of the GNU General Public License as published by= =0A= + the Free Software Foundation; either version 3 of the License, or=0A= + (at your option) any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program. If not, see . = */=0A= +=20=0A= + #include "sim-main.h"=0A= + #include "hw-main.h"=0A= + #include "sim-assert.h"=0A= +=20=0A= + struct lm32timer {=0A= + unsigned base; /* Base address of this timer */=0A= + unsigned limit; /* Limit address of this timer */=0A= + unsigned int status;=0A= + unsigned int control;=0A= + unsigned int period;=0A= + unsigned int snapshot;=0A= + struct hw_event* event;=20=0A= + };=0A= +=20=0A= + /* Timer registers */=0A= + #define LM32_TIMER_STATUS 0x0=0A= + #define LM32_TIMER_CONTROL 0x4=0A= + #define LM32_TIMER_PERIOD 0x8=0A= + #define LM32_TIMER_SNAPSHOT 0xc=0A= +=20=0A= + /* Timer ports */=0A= +=20=0A= + enum {=0A= + INT_PORT=0A= + };=0A= +=20=0A= + static const struct hw_port_descriptor lm32timer_ports[] =3D {=0A= + { "int", INT_PORT, 0, output_port },=0A= + {}=0A= + };=0A= +=20=0A= + static void=0A= + do_timer_event (struct hw *me, void *data)=0A= + {=0A= + struct lm32timer *timer =3D hw_data (me);=0A= +=20=20=20=0A= + /* Is timer started? */=0A= + if (timer->control & 0x4)=20=0A= + {=0A= + if (timer->snapshot)=0A= + {=0A= + /* Decrement timer */=0A= + timer->snapshot--;=0A= + }=0A= + else if (timer->control & 1)=0A= + {=0A= + /* Restart timer */=0A= + timer->snapshot =3D timer->period;=0A= + }=0A= + }=20=20=20=0A= + /* Generate interrupt when timer is at 0, and interrupt enable is 1 */= =0A= + if ((timer->snapshot =3D=3D 0) && (timer->control & 1))=0A= + {=0A= + /* Generate interrupt */=0A= + hw_port_event (me, INT_PORT, 1);=0A= + }=20=20=20=20=0A= + /* If timer is started, schedule another event to decrement the timer a= gain */=0A= + if (timer->control & 4)=20=0A= + hw_event_queue_schedule (me, 1, do_timer_event, 0);=0A= + }=0A= +=20=0A= + static unsigned=0A= + lm32timer_io_write_buffer (struct hw *me,=0A= + const void *source,=0A= + int space,=0A= + unsigned_word base,=0A= + unsigned nr_bytes)=0A= + {=0A= + struct lm32timer *timers =3D hw_data (me);=0A= + int timer_reg;=0A= + const unsigned char *source_bytes =3D source;=0A= + int value =3D 0;=0A= +=20=20=20=0A= + HW_TRACE ((me, "write to 0x%08lx length %d with 0x%x", (long) base,=0A= + (int) nr_bytes, value));=0A= +=20=0A= + if (nr_bytes =3D=3D 4)=0A= + value =3D (source_bytes[0] << 24)=0A= + | (source_bytes[1] << 16)=0A= + | (source_bytes[2] << 8)=0A= + | (source_bytes[3]);=0A= + else=20=0A= + hw_abort (me, "write with invalid number of bytes: %d", nr_bytes);=0A= +=20=20=20=0A= + timer_reg =3D base - timers->base;=0A= +=20=0A= + switch (timer_reg)=20=0A= + {=0A= + case LM32_TIMER_STATUS:=0A= + timers->status =3D value;=0A= + break;=20=20=20=20=20=20=20=20=0A= + case LM32_TIMER_CONTROL:=0A= + timers->control =3D value;=0A= + if (timers->control & 0x4)=20=0A= + {=0A= + /* Timer is started */=0A= + hw_event_queue_schedule (me, 1, do_timer_event, 0);=0A= + }=0A= + break;=20=20=20=20=20=20=20=20=0A= + case LM32_TIMER_PERIOD:=0A= + timers->period =3D value;=0A= + break;=20=20=20=20=20=20=20=20=0A= + default:=20=0A= + hw_abort (me, "invalid register address: 0x%x.", timer_reg);=20= =20=0A= + }=0A= +=20=0A= + return nr_bytes;=0A= + }=20=20=20=20=20=0A= +=20=0A= + static unsigned=0A= + lm32timer_io_read_buffer (struct hw *me,=0A= + void *dest,=0A= + int space,=0A= + unsigned_word base,=0A= + unsigned nr_bytes)=0A= + {=09=09=09=0A= + struct lm32timer *timers =3D hw_data (me);=0A= + int timer_reg;=0A= + int value;=0A= + unsigned char *dest_bytes =3D dest;=0A= +=20=0A= + HW_TRACE ((me, "read 0x%08lx length %d", (long) base, (int) nr_bytes));= =0A= +=20=0A= + timer_reg =3D base - timers->base;=0A= +=20=0A= + switch (timer_reg)=20=0A= + {=0A= + case LM32_TIMER_STATUS:=0A= + value =3D timers->status;=0A= + break;=20=20=20=20=20=20=20=20=0A= + case LM32_TIMER_CONTROL:=0A= + value =3D timers->control;=0A= + break;=20=20=20=20=20=20=20=20=0A= + case LM32_TIMER_PERIOD:=0A= + value =3D timers->period;=0A= + break;=20=20=20=20=20=20=20=20=0A= + case LM32_TIMER_SNAPSHOT:=0A= + value =3D timers->snapshot;=0A= + break;=20=20=20=20=20=20=20=0A= + default:=20=0A= + hw_abort (me, "invalid register address: 0x%x.", timer_reg);=20= =20=0A= + }=0A= +=20=20=0A= + if (nr_bytes =3D=3D 4)=0A= + {=0A= + dest_bytes[0] =3D value >> 24;=0A= + dest_bytes[1] =3D value >> 16;=0A= + dest_bytes[2] =3D value >> 8;=0A= + dest_bytes[3] =3D value;=0A= + }=0A= + else=20=0A= + hw_abort (me, "read of unsupported number of bytes: %d", nr_bytes);= =0A= +=20=20=20=20=20=0A= + return nr_bytes;=0A= + }=20=20=20=20=20=0A= +=20=0A= + static void=0A= + attach_lm32timer_regs (struct hw *me, struct lm32timer *timers)=0A= + {=0A= + unsigned_word attach_address;=0A= + int attach_space;=0A= + unsigned attach_size;=0A= + reg_property_spec reg;=0A= +=20=0A= + if (hw_find_property (me, "reg") =3D=3D NULL)=20=0A= + hw_abort (me, "Missing \"reg\" property");=0A= + if (!hw_find_reg_array_property (me, "reg", 0, ®))=0A= + hw_abort (me, "\"reg\" property must contain three addr/size entries"= );=0A= + hw_unit_address_to_attach_address (hw_parent (me),=0A= + ®.address,=0A= + &attach_space,=0A= + &attach_address,=0A= + me);=0A= + timers->base =3D attach_address;=0A= + hw_unit_size_to_attach_size (hw_parent (me),=0A= + ®.size,=0A= + &attach_size, me);=0A= + timers->limit =3D attach_address + (attach_size - 1);=0A= + hw_attach_address (hw_parent (me),=0A= + 0,=0A= + attach_space, attach_address, attach_size,=0A= + me);=20=0A= + }=0A= +=20=0A= + static void=0A= + lm32timer_finish (struct hw *me)=0A= + {=0A= + struct lm32timer *timers;=0A= + int i;=0A= +=20=0A= + timers =3D HW_ZALLOC (me, struct lm32timer);=0A= + set_hw_data (me, timers);=0A= + set_hw_io_read_buffer (me, lm32timer_io_read_buffer);=0A= + set_hw_io_write_buffer (me, lm32timer_io_write_buffer);=0A= + set_hw_ports (me, lm32timer_ports);=0A= +=20=0A= + /* Attach ourself to our parent bus */=0A= + attach_lm32timer_regs (me, timers);=0A= +=20=0A= + /* Initialize the timers */=0A= + timers->status =3D 0;=0A= + timers->control =3D 0;=0A= + timers->period =3D 0;=0A= + timers->snapshot =3D 0;=0A= + }=0A= +=20=0A= + const struct hw_descriptor dv_lm32timer_descriptor[] =3D {=0A= + { "lm32timer", lm32timer_finish, },=0A= + { NULL },=0A= + };=0A= Index: sim/lm32/dv-lm32uart.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/dv-lm32uart.c=0A= diff -N sim/lm32/dv-lm32uart.c=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/dv-lm32uart.c 20 Dec 2008 22:02:36 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,321 ----=0A= + /* Lattice Mico32 UART model.=0A= + Contributed by Jon Beniston =0A= +=20=20=20=20=20=0A= + This file is part of GDB.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify= =0A= + it under the terms of the GNU General Public License as published by= =0A= + the Free Software Foundation; either version 3 of the License, or=0A= + (at your option) any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program. If not, see . = */=0A= +=20=0A= + #include "sim-main.h"=0A= + #include "hw-main.h"=0A= + #include "sim-assert.h"=0A= +=20=0A= + #include =0A= + #include =0A= +=20=0A= + struct lm32uart {=0A= + unsigned base; /* Base address of this UART */=0A= + unsigned limit; /* Limit address of this UART */=0A= + unsigned char rbr;=0A= + unsigned char thr;=0A= + unsigned char ier;=0A= + unsigned char iir;=0A= + unsigned char lcr;=0A= + unsigned char mcr;=0A= + unsigned char lsr;=0A= + unsigned char msr;=0A= + unsigned char div;=20=20=0A= + struct hw_event* event;=20=0A= + };=0A= +=20=0A= + /* UART registers */=0A= +=20=0A= + #define LM32_UART_RBR 0x0=0A= + #define LM32_UART_THR 0x0=0A= + #define LM32_UART_IER 0x4=0A= + #define LM32_UART_IIR 0x8=0A= + #define LM32_UART_LCR 0xc=0A= + #define LM32_UART_MCR 0x10=0A= + #define LM32_UART_LSR 0x14=0A= + #define LM32_UART_MSR 0x18=0A= + #define LM32_UART_DIV 0x1c=0A= +=20=0A= + #define LM32_UART_IER_RX_INT 0x1=0A= + #define LM32_UART_IER_TX_INT 0x2=0A= +=20=0A= + #define MICOUART_IIR_TXRDY 0x2=0A= + #define MICOUART_IIR_RXRDY 0x4=0A= +=20=0A= + #define LM32_UART_LSR_RX_RDY 0x01=0A= + #define LM32_UART_LSR_TX_RDY 0x20=0A= +=20=0A= + #define LM32_UART_LCR_WLS_MASK 0x3=0A= + #define LM32_UART_LCR_WLS_5 0x0=0A= + #define LM32_UART_LCR_WLS_6 0x1=0A= + #define LM32_UART_LCR_WLS_7 0x2=0A= + #define LM32_UART_LCR_WLS_8 0x3=0A= +=20=0A= + /* UART ports */=0A= +=20=0A= + enum {=0A= + INT_PORT=0A= + };=0A= +=20=0A= + static const struct hw_port_descriptor lm32uart_ports[] =3D {=0A= + { "int", INT_PORT, 0, output_port },=0A= + {}=0A= + };=0A= +=20=0A= + static void=0A= + do_uart_tx_event (struct hw *me, void *data)=0A= + {=0A= + struct lm32uart *uart =3D hw_data (me);=0A= + char c;=0A= +=20=20=20=0A= + /* Generate interrupt when transmission is complete */=0A= + if (uart->ier & LM32_UART_IER_TX_INT) {=0A= + /* Generate interrupt */=0A= + hw_port_event (me, INT_PORT, 1);=0A= + }=0A= +=20=0A= + /* Indicate which interrupt has occured */=20=20=0A= + uart->iir =3D MICOUART_IIR_TXRDY;=0A= +=20=0A= + /* Indicate THR is empty */=0A= + uart->lsr |=3D LM32_UART_LSR_TX_RDY;=0A= +=20=0A= + /* Output the character in the THR */=0A= + c =3D (char)uart->thr;=0A= +=20=0A= + /* WLS field in LCR register specifies the number of bits to output */= =0A= + switch (uart->lcr & LM32_UART_LCR_WLS_MASK)=20=0A= + {=0A= + case LM32_UART_LCR_WLS_5:=0A= + c &=3D 0x1f;=0A= + break;=0A= + case LM32_UART_LCR_WLS_6:=0A= + c &=3D 0x3f;=0A= + break;=0A= + case LM32_UART_LCR_WLS_7:=20=0A= + c &=3D 0x7f;=0A= + break;=0A= + }=0A= + printf ("%c", c);=0A= + }=0A= +=20=0A= + static unsigned=0A= + lm32uart_io_write_buffer (struct hw *me,=0A= + const void *source,=0A= + int space,=0A= + unsigned_word base,=0A= + unsigned nr_bytes)=0A= + {=0A= + struct lm32uart *uart =3D hw_data (me);=0A= + int uart_reg;=0A= + const unsigned char *source_bytes =3D source;=0A= + int value =3D 0;=0A= +=20=20=20=0A= + HW_TRACE ((me, "write to 0x%08lx length %d with 0x%x", (long) base,=0A= + (int) nr_bytes, value));=0A= +=20=0A= + if (nr_bytes =3D=3D 4)=0A= + value =3D (source_bytes[0] << 24)=0A= + | (source_bytes[1] << 16)=0A= + | (source_bytes[2] << 8)=0A= + | (source_bytes[3]);=0A= + else=20=0A= + hw_abort (me, "write of unsupported number of bytes: %d.", nr_bytes);= =0A= +=20=20=20=0A= + uart_reg =3D base - uart->base;=0A= +=20=0A= + switch (uart_reg)=20=0A= + {=0A= + case LM32_UART_THR:=0A= + /* Buffer the character to output */=0A= + uart->thr =3D value;=0A= +=20=0A= + /* Indicate the THR is full */=0A= + uart->lsr &=3D ~LM32_UART_LSR_TX_RDY;=0A= +=20=0A= + /* deassert interrupt when IER is loaded */=0A= + uart->iir &=3D ~MICOUART_IIR_TXRDY;=0A= +=20=0A= + /* schedule an event to output the character */=0A= + hw_event_queue_schedule (me, 1, do_uart_tx_event, 0);=0A= +=20=0A= + break;=0A= + case LM32_UART_IER:=0A= + uart->ier =3D value;=0A= + if((value & LM32_UART_IER_TX_INT) && (uart->lsr & LM32_UART_LSR_TX_RDY))= {=0A= + /* hw_event_queue_schedule (me, 1, do_uart_tx_event, 0); */= =0A= + uart->lsr |=3D LM32_UART_LSR_TX_RDY;=0A= + uart->iir |=3D MICOUART_IIR_TXRDY;=0A= + hw_port_event (me, INT_PORT, 1);=0A= + }else if((value & LM32_UART_IER_TX_INT) =3D=3D 0){=0A= + hw_port_event (me, INT_PORT, 0);=0A= + }=0A= + break;=0A= + case LM32_UART_IIR:=0A= + uart->iir =3D value;=0A= + break;=20=20=0A= + case LM32_UART_LCR:=0A= + uart->lcr =3D value;=0A= + break;=0A= + case LM32_UART_MCR:=0A= + uart->mcr =3D value;=0A= + break;=0A= + case LM32_UART_LSR:=0A= + uart->lsr =3D value;=0A= + break;=0A= + case LM32_UART_MSR:=0A= + uart->msr =3D value;=0A= + break;=0A= + case LM32_UART_DIV:=0A= + uart->div =3D value;=0A= + break;=20=20=20=20=20=20=20=20=0A= + default:=20=0A= + hw_abort (me, "write to invalid register address: 0x%x.", uart_re= g);=20=20=0A= + }=0A= +=20=0A= + return nr_bytes;=0A= + }=20=20=20=20=20=0A= +=20=0A= + static unsigned=0A= + lm32uart_io_read_buffer (struct hw *me,=0A= + void *dest,=0A= + int space,=0A= + unsigned_word base,=0A= + unsigned nr_bytes)=0A= + {=09=09=09=0A= + struct lm32uart *uart =3D hw_data (me);=0A= + int uart_reg;=0A= + int value;=0A= + unsigned char *dest_bytes =3D dest;=0A= + fd_set fd;=0A= + struct timeval tv;=0A= +=20=0A= + HW_TRACE ((me, "read 0x%08lx length %d", (long) base, (int) nr_bytes));= =0A= +=20=0A= + uart_reg =3D base - uart->base;=0A= +=20=0A= + switch (uart_reg)=20=0A= + {=0A= + case LM32_UART_RBR:=0A= + value =3D getchar ();=0A= + uart->lsr &=3D ~LM32_UART_LSR_RX_RDY;=0A= + break;=0A= + case LM32_UART_IER:=0A= + value =3D uart->ier;=0A= + break;=20=0A= + case LM32_UART_IIR:=0A= + value =3D uart->iir;=0A= + break;=20=20=0A= + case LM32_UART_LCR:=0A= + value =3D uart->lcr;=0A= + break;=0A= + case LM32_UART_MCR:=0A= + value =3D uart->mcr;=0A= + break;=0A= + case LM32_UART_LSR:=0A= + /* Check to see if any data waiting in stdin */=0A= + FD_ZERO (&fd);=0A= + FD_SET (fileno (stdin), &fd);=0A= + tv.tv_sec =3D 0;=0A= + tv.tv_usec =3D 1;=0A= + if (select (fileno (stdin) + 1, &fd, NULL, NULL, &tv))=20=0A= + uart->lsr |=3D LM32_UART_LSR_RX_RDY;=0A= + value =3D uart->lsr;=0A= + break;=0A= + case LM32_UART_MSR:=0A= + value =3D uart->msr;=0A= + break;=0A= + case LM32_UART_DIV:=0A= + value =3D uart->div;=0A= + break;=20=20=20=20=20=20=20=20=0A= + default:=20=0A= + hw_abort (me, "read from invalid register address: 0x%x.", uart_r= eg);=20=20=0A= + }=0A= +=20=0A= + if (nr_bytes =3D=3D 4)=0A= + {=0A= + dest_bytes[0] =3D value >> 24;=0A= + dest_bytes[1] =3D value >> 16;=0A= + dest_bytes[2] =3D value >> 8;=0A= + dest_bytes[3] =3D value;=0A= + }=0A= + else=20=0A= + hw_abort (me, "read of unsupported number of bytes: %d", nr_bytes);= =0A= +=20=20=20=20=20=0A= + return nr_bytes;=0A= + }=20=20=20=20=20=0A= +=20=0A= + static void=0A= + attach_lm32uart_regs (struct hw *me, struct lm32uart *uart)=0A= + {=0A= + unsigned_word attach_address;=0A= + int attach_space;=0A= + unsigned attach_size;=0A= + reg_property_spec reg;=0A= +=20=0A= + if (hw_find_property (me, "reg") =3D=3D NULL)=20=0A= + hw_abort (me, "Missing \"reg\" property");=0A= + if (!hw_find_reg_array_property (me, "reg", 0, ®))=0A= + hw_abort (me, "\"reg\" property must contain three addr/size entries"= );=0A= + hw_unit_address_to_attach_address (hw_parent (me),=0A= + ®.address,=0A= + &attach_space,=0A= + &attach_address,=0A= + me);=0A= + uart->base =3D attach_address;=0A= + hw_unit_size_to_attach_size (hw_parent (me),=0A= + ®.size,=0A= + &attach_size, me);=0A= + uart->limit =3D attach_address + (attach_size - 1);=0A= + hw_attach_address (hw_parent (me),=0A= + 0,=0A= + attach_space, attach_address, attach_size,=0A= + me);=20=0A= + }=0A= +=20=0A= + static void=0A= + lm32uart_finish (struct hw *me)=0A= + {=0A= + struct lm32uart *uart;=0A= + int i;=0A= +=20=0A= + uart =3D HW_ZALLOC (me, struct lm32uart);=0A= + set_hw_data (me, uart);=0A= + set_hw_io_read_buffer (me, lm32uart_io_read_buffer);=0A= + set_hw_io_write_buffer (me, lm32uart_io_write_buffer);=0A= + set_hw_ports (me, lm32uart_ports);=0A= +=20=0A= + /* Attach ourself to our parent bus */=0A= + attach_lm32uart_regs (me, uart);=0A= +=20=0A= + /* Initialize the UART */=0A= + uart->rbr =3D 0;=0A= + uart->thr =3D 0;=0A= + uart->ier =3D 0;=0A= + uart->iir =3D 0;=0A= + uart->lcr =3D 0;=0A= + uart->mcr =3D 0;=0A= + uart->lsr =3D LM32_UART_LSR_TX_RDY;=0A= + uart->msr =3D 0;=0A= + uart->div =3D 0; /* By setting to zero, characters are output immediat= ely */=0A= + }=0A= +=20=0A= + const struct hw_descriptor dv_lm32uart_descriptor[] =3D {=0A= + { "lm32uart", lm32uart_finish, },=0A= + { NULL },=0A= + };=0A= +=20=0A= Index: sim/lm32/lm32-sim.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/lm32-sim.h=0A= diff -N sim/lm32/lm32-sim.h=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/lm32-sim.h 20 Dec 2008 22:02:36 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,55 ----=0A= + /* Contributed by Jon Beniston =0A= +=20=0A= + This file is part of GDB.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify= =0A= + it under the terms of the GNU General Public License as published by= =0A= + the Free Software Foundation; either version 3 of the License, or=0A= + (at your option) any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program. If not, see . = */=0A= +=20=0A= + #ifndef LM32_SIM_H=0A= + #define LM32_SIM_H=0A= +=20=0A= + #include "gdb/sim-lm32.h"=0A= +=20=0A= + /* CSRs */=0A= + #define LM32_CSR_IE 0=0A= + #define LM32_CSR_IM 1=0A= + #define LM32_CSR_IP 2=0A= + #define LM32_CSR_ICC 3=0A= + #define LM32_CSR_DCC 4=0A= + #define LM32_CSR_CC 5=0A= + #define LM32_CSR_CFG 6=0A= + #define LM32_CSR_EBA 7=0A= + #define LM32_CSR_DC 8=0A= + #define LM32_CSR_DEBA 9=0A= + #define LM32_CSR_JTX 0xe=0A= + #define LM32_CSR_JRX 0xf=0A= + #define LM32_CSR_BP0 0x10=0A= + #define LM32_CSR_BP1 0x11=0A= + #define LM32_CSR_BP2 0x12=0A= + #define LM32_CSR_BP3 0x13=0A= + #define LM32_CSR_WP0 0x18=0A= + #define LM32_CSR_WP1 0x19=0A= + #define LM32_CSR_WP2 0x1a=0A= + #define LM32_CSR_WP3 0x1b=0A= +=20=0A= + /* Exception IDs */=0A= + #define LM32_EID_RESET 0=0A= + #define LM32_EID_BREAKPOINT 1=0A= + #define LM32_EID_INSTRUCTION_BUS_ERROR 2=0A= + #define LM32_EID_WATCHPOINT 3=0A= + #define LM32_EID_DATA_BUS_ERROR 4=0A= + #define LM32_EID_DIVIDE_BY_ZERO 5=0A= + #define LM32_EID_INTERRUPT 6=0A= + #define LM32_EID_SYSTEM_CALL 7=0A= +=20=0A= + #endif /* LM32_SIM_H */=0A= Index: sim/lm32/lm32.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/lm32.c=0A= diff -N sim/lm32/lm32.c=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/lm32.c 20 Dec 2008 22:02:36 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,96 ----=0A= + /* Lattice Mico32 simulator support code.=0A= + Contributed by Jon Beniston =0A= +=20=0A= + This file is part of GDB.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify= =0A= + it under the terms of the GNU General Public License as published by= =0A= + the Free Software Foundation; either version 3 of the License, or=0A= + (at your option) any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program. If not, see . = */=0A= +=20=0A= + #define WANT_CPU lm32bf=0A= + #define WANT_CPU_LM32BF=0A= +=20=0A= + #include "sim-main.h"=0A= + #include "cgen-mem.h"=0A= + #include "cgen-ops.h"=0A= +=20=0A= + /* The contents of BUF are in target byte order. */=0A= +=20=0A= + int=0A= + lm32bf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, = int len)=0A= + {=0A= + if (rn < 32)=0A= + SETTSI (buf, lm32bf_h_gr_get (current_cpu, rn));=0A= + else=0A= + switch (rn)=0A= + {=0A= + case SIM_LM32_PC_REGNUM :=0A= + SETTSI (buf, lm32bf_h_pc_get (current_cpu));=0A= + break;=0A= + default :=0A= + return 0;=0A= + }=0A= +=20=0A= + return -1; /*FIXME*/=0A= + }=0A= +=20=0A= + /* The contents of BUF are in target byte order. */=0A= +=20=0A= + int=0A= + lm32bf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, = int len)=0A= + {=0A= + if (rn < 32)=0A= + lm32bf_h_gr_set (current_cpu, rn, GETTSI (buf));=0A= + else=0A= + switch (rn)=0A= + {=0A= + case SIM_LM32_PC_REGNUM :=0A= + lm32bf_h_pc_set (current_cpu, GETTSI (buf));=0A= + break;=0A= + default :=0A= + return 0;=0A= + }=0A= +=20=0A= + return -1; /*FIXME*/=0A= + }=0A= +=20=0A= +=20=0A= +=20=0A= + #if WITH_PROFILE_MODEL_P=0A= +=20=0A= + /* Initialize cycle counting for an insn.=0A= + FIRST_P is non-zero if this is the first insn in a set of parallel=0A= + insns. */=0A= +=20=0A= + void=0A= + lm32bf_model_insn_before (SIM_CPU *cpu, int first_p)=0A= + {=0A= + }=0A= +=20=0A= + /* Record the cycles computed for an insn.=0A= + LAST_P is non-zero if this is the last insn in a set of parallel insns= ,=0A= + and we update the total cycle count.=0A= + CYCLES is the cycle count of the insn. */=0A= +=20=0A= + void=0A= + lm32bf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)=0A= + {=0A= + }=0A= +=20=0A= + int=0A= + lm32bf_model_lm32_u_exec (SIM_CPU *cpu, const IDESC *idesc,=0A= + int unit_num, int referenced)=0A= + {=0A= + return idesc->timing->units[unit_num].done;=0A= + }=0A= +=20=0A= + #endif /* WITH_PROFILE_MODEL_P */=0A= Index: sim/lm32/mloop.in=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/mloop.in=0A= diff -N sim/lm32/mloop.in=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/mloop.in 20 Dec 2008 22:02:36 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,203 ----=0A= + # Simulator main loop for lm32. -*- C -*-=0A= + # Contributed by Jon Beniston =0A= + #=0A= + # This file is part of the GNU Simulators.=0A= + #=0A= + # This program is free software; you can redistribute it and/or modify=0A= + # it under the terms of the GNU General Public License as published by=0A= + # the Free Software Foundation; either version 2, or (at your option)=0A= + # any later version.=0A= + #=0A= + # This program is distributed in the hope that it will be useful,=0A= + # but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + # GNU General Public License for more details.=0A= + #=0A= + # You should have received a copy of the GNU General Public License along= =0A= + # with this program; if not, write to the Free Software Foundation, Inc.,= =0A= + # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.=0A= +=20=0A= + # Syntax:=0A= + # /bin/sh mainloop.in command=0A= + #=0A= + # Command is one of:=0A= + #=0A= + # init=0A= + # support=0A= + # extract-{simple,scache,pbb}=0A= + # {full,fast}-exec-{simple,scache,pbb}=0A= + #=0A= +=20=0A= + case "x$1" in=0A= +=20=0A= + xsupport)=0A= +=20=0A= + cat <argbuf.semantic.sem_fast) (current_cpu, sc);=0A= + #else=0A= + vpc =3D (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);= =0A= + #endif=0A= + #else=0A= + abort ();=0A= + #endif /* WITH_SEM_SWITCH_FAST */=0A= + }=0A= + else=0A= + {=0A= + #if ! WITH_SEM_SWITCH_FULL=0A= + ARGBUF *abuf =3D &sc->argbuf;=0A= + const IDESC *idesc =3D abuf->idesc;=0A= + const CGEN_INSN *idata =3D idesc->idata;=0A= + #if WITH_SCACHE_PBB=0A= + int virtual_p =3D CGEN_INSN_ATTR_VALUE (idata, CGEN_INSN_VIRTUAL);= =0A= + #else=0A= + int virtual_p =3D 0;=0A= + #endif=0A= + if (! virtual_p)=0A= + {=0A= + /* FIXME: call x-before */=0A= + if (ARGBUF_PROFILE_P (abuf))=0A= + PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);=0A= + /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */=0A= + if (PROFILE_MODEL_P (current_cpu)=0A= + && ARGBUF_PROFILE_P (abuf))=0A= + @cpu@_model_insn_before (current_cpu, 1 /*first_p*/);=0A= + TRACE_INSN_INIT (current_cpu, abuf, 1);=0A= + TRACE_INSN (current_cpu, idata,=0A= + (const struct argbuf *) abuf, abuf->addr);=0A= + }=0A= + #if WITH_SCACHE=0A= + vpc =3D (*sc->argbuf.semantic.sem_full) (current_cpu, sc);=0A= + #else=0A= + vpc =3D (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);=0A= + #endif=0A= + if (! virtual_p)=0A= + {=0A= + /* FIXME: call x-after */=0A= + if (PROFILE_MODEL_P (current_cpu)=0A= + && ARGBUF_PROFILE_P (abuf))=0A= + {=0A= + int cycles;=0A= +=20=0A= + cycles =3D (*idesc->timing->model_fn) (current_cpu, sc);=0A= + @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);=0A= + }=0A= + TRACE_INSN_FINI (current_cpu, abuf, 1);=0A= + }=0A= + #else=0A= + abort ();=0A= + #endif /* WITH_SEM_SWITCH_FULL */=0A= + }=0A= +=20=0A= + return vpc;=0A= + }=0A= +=20=0A= + EOF=0A= +=20=0A= + ;;=0A= +=20=0A= + xinit)=0A= +=20=0A= + # Nothing needed.=0A= +=20=0A= + ;;=0A= +=20=0A= + xextract-simple | xextract-scache)=0A= +=20=0A= + cat < 0)=0A= + {=0A= + USI insn =3D GETIMEMUSI (current_cpu, pc);=0A= +=20=20=20=20=20=20=20=0A= + idesc =3D extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);=0A= + ++sc;=0A= + --max_insns;=0A= + ++icount;=0A= + pc +=3D idesc->length;=0A= +=20=0A= + if (IDESC_CTI_P (idesc))=0A= + {=0A= + SET_CTI_VPC (sc - 1);=0A= + break;=0A= + }=0A= + }=0A= +=20=0A= + Finish:=0A= + SET_INSN_COUNT (icount);=0A= + }=0A= + EOF=0A= +=20=0A= + ;;=0A= +=20=0A= + xfull-exec-* | xfast-exec-*)=0A= +=20=0A= + # Inputs: current_cpu, vpc, FAST_P=0A= + # Outputs: vpc=0A= +=20=0A= + cat <&2=0A= + exit 1=0A= + ;;=0A= +=20=0A= + esac=0A= Index: sim/lm32/model.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/model.c=0A= diff -N sim/lm32/model.c=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/model.c 20 Dec 2008 22:02:37 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,1176 ----=0A= + /* Simulator model support for lm32bf.=0A= +=20=0A= + THIS FILE IS MACHINE GENERATED WITH CGEN.=0A= +=20=0A= + Copyright 1996-2005 Free Software Foundation, Inc.=0A= +=20=0A= + This file is part of the GNU simulators.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 2, or (at your option)=0A= + any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License along= =0A= + with this program; if not, write to the Free Software Foundation, Inc.,= =0A= + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.=0A= +=20=0A= + */=0A= +=20=0A= + #define WANT_CPU lm32bf=0A= + #define WANT_CPU_LM32BF=0A= +=20=0A= + #include "sim-main.h"=0A= +=20=0A= + /* The profiling data is recorded here, but is accessed via the profiling= =0A= + mechanism. After all, this is information for profiling. */=0A= +=20=0A= + #if WITH_PROFILE_MODEL_P=0A= +=20=0A= + /* Model handlers for each insn. */=0A= +=20=0A= + static int=0A= + model_lm32_add (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_addi (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_and (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_andi (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_andhii (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_b (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_bi (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_bi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_be (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_bg (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_bge (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_bgeu (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_bgu (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_bne (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_call (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_calli (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_bi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_cmpe (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_cmpei (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_cmpg (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_cmpgi (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_cmpge (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_cmpgei (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_cmpgeu (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_cmpgeui (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_cmpgu (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_cmpgui (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_cmpne (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_cmpnei (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_divu (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_lb (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_lbu (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_lh (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_lhu (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_lw (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_modu (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_mul (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_muli (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_nor (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_nori (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_or (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_ori (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_orhii (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_rcsr (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_rcsr.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_sb (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_sextb (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_sexth (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_sh (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_sl (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_sli (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_sr (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_sri (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_sru (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_srui (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_sub (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_sw (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_user (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_wcsr (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_wcsr.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_xor (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_xori (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_xnor (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_xnori (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_break (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + static int=0A= + model_lm32_scall (SIM_CPU *current_cpu, void *sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= + const IDESC * UNUSED idesc =3D abuf->idesc;=0A= + int cycles =3D 0;=0A= + {=0A= + int referenced =3D 0;=0A= + int UNUSED insn_referenced =3D abuf->written;=0A= + cycles +=3D lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenc= ed);=0A= + }=0A= + return cycles;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* We assume UNIT_NONE =3D=3D 0 because the tables don't always terminate= =0A= + entries with it. */=0A= +=20=0A= + /* Model timing data for `lm32'. */=0A= +=20=0A= + static const INSN_TIMING lm32_timing[] =3D {=0A= + { LM32BF_INSN_X_INVALID, 0, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },=0A= + { LM32BF_INSN_X_AFTER, 0, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },=0A= + { LM32BF_INSN_X_BEFORE, 0, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },=0A= + { LM32BF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },= =0A= + { LM32BF_INSN_X_CHAIN, 0, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },=0A= + { LM32BF_INSN_X_BEGIN, 0, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },=0A= + { LM32BF_INSN_ADD, model_lm32_add, { { (int) UNIT_LM32_U_EXEC, 1, 1 } }= },=0A= + { LM32BF_INSN_ADDI, model_lm32_addi, { { (int) UNIT_LM32_U_EXEC, 1, 1 }= } },=0A= + { LM32BF_INSN_AND, model_lm32_and, { { (int) UNIT_LM32_U_EXEC, 1, 1 } }= },=0A= + { LM32BF_INSN_ANDI, model_lm32_andi, { { (int) UNIT_LM32_U_EXEC, 1, 1 }= } },=0A= + { LM32BF_INSN_ANDHII, model_lm32_andhii, { { (int) UNIT_LM32_U_EXEC, 1,= 1 } } },=0A= + { LM32BF_INSN_B, model_lm32_b, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },= =0A= + { LM32BF_INSN_BI, model_lm32_bi, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } }= ,=0A= + { LM32BF_INSN_BE, model_lm32_be, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } }= ,=0A= + { LM32BF_INSN_BG, model_lm32_bg, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } }= ,=0A= + { LM32BF_INSN_BGE, model_lm32_bge, { { (int) UNIT_LM32_U_EXEC, 1, 1 } }= },=0A= + { LM32BF_INSN_BGEU, model_lm32_bgeu, { { (int) UNIT_LM32_U_EXEC, 1, 1 }= } },=0A= + { LM32BF_INSN_BGU, model_lm32_bgu, { { (int) UNIT_LM32_U_EXEC, 1, 1 } }= },=0A= + { LM32BF_INSN_BNE, model_lm32_bne, { { (int) UNIT_LM32_U_EXEC, 1, 1 } }= },=0A= + { LM32BF_INSN_CALL, model_lm32_call, { { (int) UNIT_LM32_U_EXEC, 1, 1 }= } },=0A= + { LM32BF_INSN_CALLI, model_lm32_calli, { { (int) UNIT_LM32_U_EXEC, 1, 1= } } },=0A= + { LM32BF_INSN_CMPE, model_lm32_cmpe, { { (int) UNIT_LM32_U_EXEC, 1, 1 }= } },=0A= + { LM32BF_INSN_CMPEI, model_lm32_cmpei, { { (int) UNIT_LM32_U_EXEC, 1, 1= } } },=0A= + { LM32BF_INSN_CMPG, model_lm32_cmpg, { { (int) UNIT_LM32_U_EXEC, 1, 1 }= } },=0A= + { LM32BF_INSN_CMPGI, model_lm32_cmpgi, { { (int) UNIT_LM32_U_EXEC, 1, 1= } } },=0A= + { LM32BF_INSN_CMPGE, model_lm32_cmpge, { { (int) UNIT_LM32_U_EXEC, 1, 1= } } },=0A= + { LM32BF_INSN_CMPGEI, model_lm32_cmpgei, { { (int) UNIT_LM32_U_EXEC, 1,= 1 } } },=0A= + { LM32BF_INSN_CMPGEU, model_lm32_cmpgeu, { { (int) UNIT_LM32_U_EXEC, 1,= 1 } } },=0A= + { LM32BF_INSN_CMPGEUI, model_lm32_cmpgeui, { { (int) UNIT_LM32_U_EXEC, = 1, 1 } } },=0A= + { LM32BF_INSN_CMPGU, model_lm32_cmpgu, { { (int) UNIT_LM32_U_EXEC, 1, 1= } } },=0A= + { LM32BF_INSN_CMPGUI, model_lm32_cmpgui, { { (int) UNIT_LM32_U_EXEC, 1,= 1 } } },=0A= + { LM32BF_INSN_CMPNE, model_lm32_cmpne, { { (int) UNIT_LM32_U_EXEC, 1, 1= } } },=0A= + { LM32BF_INSN_CMPNEI, model_lm32_cmpnei, { { (int) UNIT_LM32_U_EXEC, 1,= 1 } } },=0A= + { LM32BF_INSN_DIVU, model_lm32_divu, { { (int) UNIT_LM32_U_EXEC, 1, 1 }= } },=0A= + { LM32BF_INSN_LB, model_lm32_lb, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } }= ,=0A= + { LM32BF_INSN_LBU, model_lm32_lbu, { { (int) UNIT_LM32_U_EXEC, 1, 1 } }= },=0A= + { LM32BF_INSN_LH, model_lm32_lh, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } }= ,=0A= + { LM32BF_INSN_LHU, model_lm32_lhu, { { (int) UNIT_LM32_U_EXEC, 1, 1 } }= },=0A= + { LM32BF_INSN_LW, model_lm32_lw, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } }= ,=0A= + { LM32BF_INSN_MODU, model_lm32_modu, { { (int) UNIT_LM32_U_EXEC, 1, 1 }= } },=0A= + { LM32BF_INSN_MUL, model_lm32_mul, { { (int) UNIT_LM32_U_EXEC, 1, 1 } }= },=0A= + { LM32BF_INSN_MULI, model_lm32_muli, { { (int) UNIT_LM32_U_EXEC, 1, 1 }= } },=0A= + { LM32BF_INSN_NOR, model_lm32_nor, { { (int) UNIT_LM32_U_EXEC, 1, 1 } }= },=0A= + { LM32BF_INSN_NORI, model_lm32_nori, { { (int) UNIT_LM32_U_EXEC, 1, 1 }= } },=0A= + { LM32BF_INSN_OR, model_lm32_or, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } }= ,=0A= + { LM32BF_INSN_ORI, model_lm32_ori, { { (int) UNIT_LM32_U_EXEC, 1, 1 } }= },=0A= + { LM32BF_INSN_ORHII, model_lm32_orhii, { { (int) UNIT_LM32_U_EXEC, 1, 1= } } },=0A= + { LM32BF_INSN_RCSR, model_lm32_rcsr, { { (int) UNIT_LM32_U_EXEC, 1, 1 }= } },=0A= + { LM32BF_INSN_SB, model_lm32_sb, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } }= ,=0A= + { LM32BF_INSN_SEXTB, model_lm32_sextb, { { (int) UNIT_LM32_U_EXEC, 1, 1= } } },=0A= + { LM32BF_INSN_SEXTH, model_lm32_sexth, { { (int) UNIT_LM32_U_EXEC, 1, 1= } } },=0A= + { LM32BF_INSN_SH, model_lm32_sh, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } }= ,=0A= + { LM32BF_INSN_SL, model_lm32_sl, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } }= ,=0A= + { LM32BF_INSN_SLI, model_lm32_sli, { { (int) UNIT_LM32_U_EXEC, 1, 1 } }= },=0A= + { LM32BF_INSN_SR, model_lm32_sr, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } }= ,=0A= + { LM32BF_INSN_SRI, model_lm32_sri, { { (int) UNIT_LM32_U_EXEC, 1, 1 } }= },=0A= + { LM32BF_INSN_SRU, model_lm32_sru, { { (int) UNIT_LM32_U_EXEC, 1, 1 } }= },=0A= + { LM32BF_INSN_SRUI, model_lm32_srui, { { (int) UNIT_LM32_U_EXEC, 1, 1 }= } },=0A= + { LM32BF_INSN_SUB, model_lm32_sub, { { (int) UNIT_LM32_U_EXEC, 1, 1 } }= },=0A= + { LM32BF_INSN_SW, model_lm32_sw, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } }= ,=0A= + { LM32BF_INSN_USER, model_lm32_user, { { (int) UNIT_LM32_U_EXEC, 1, 1 }= } },=0A= + { LM32BF_INSN_WCSR, model_lm32_wcsr, { { (int) UNIT_LM32_U_EXEC, 1, 1 }= } },=0A= + { LM32BF_INSN_XOR, model_lm32_xor, { { (int) UNIT_LM32_U_EXEC, 1, 1 } }= },=0A= + { LM32BF_INSN_XORI, model_lm32_xori, { { (int) UNIT_LM32_U_EXEC, 1, 1 }= } },=0A= + { LM32BF_INSN_XNOR, model_lm32_xnor, { { (int) UNIT_LM32_U_EXEC, 1, 1 }= } },=0A= + { LM32BF_INSN_XNORI, model_lm32_xnori, { { (int) UNIT_LM32_U_EXEC, 1, 1= } } },=0A= + { LM32BF_INSN_BREAK, model_lm32_break, { { (int) UNIT_LM32_U_EXEC, 1, 1= } } },=0A= + { LM32BF_INSN_SCALL, model_lm32_scall, { { (int) UNIT_LM32_U_EXEC, 1, 1= } } },=0A= + };=0A= +=20=0A= + #endif /* WITH_PROFILE_MODEL_P */=0A= +=20=0A= + static void=0A= + lm32_model_init (SIM_CPU *cpu)=0A= + {=0A= + CPU_MODEL_DATA (cpu) =3D (void *) zalloc (sizeof (MODEL_LM32_DATA));=0A= + }=0A= +=20=0A= + #if WITH_PROFILE_MODEL_P=0A= + #define TIMING_DATA(td) td=0A= + #else=0A= + #define TIMING_DATA(td) 0=0A= + #endif=0A= +=20=0A= + static const MODEL lm32_models[] =3D=0A= + {=0A= + { "lm32", & lm32_mach, MODEL_LM32, TIMING_DATA (& lm32_timing[0]), lm32= _model_init },=0A= + { 0 }=0A= + };=0A= +=20=0A= + /* The properties of this cpu's implementation. */=0A= +=20=0A= + static const MACH_IMP_PROPERTIES lm32bf_imp_properties =3D=0A= + {=0A= + sizeof (SIM_CPU),=0A= + #if WITH_SCACHE=0A= + sizeof (SCACHE)=0A= + #else=0A= + 0=0A= + #endif=0A= + };=0A= +=20=0A= +=20=0A= + static void=0A= + lm32bf_prepare_run (SIM_CPU *cpu)=0A= + {=0A= + if (CPU_IDESC (cpu) =3D=3D NULL)=0A= + lm32bf_init_idesc_table (cpu);=0A= + }=0A= +=20=0A= + static const CGEN_INSN *=0A= + lm32bf_get_idata (SIM_CPU *cpu, int inum)=0A= + {=0A= + return CPU_IDESC (cpu) [inum].idata;=0A= + }=0A= +=20=0A= + static void=0A= + lm32_init_cpu (SIM_CPU *cpu)=0A= + {=0A= + CPU_REG_FETCH (cpu) =3D lm32bf_fetch_register;=0A= + CPU_REG_STORE (cpu) =3D lm32bf_store_register;=0A= + CPU_PC_FETCH (cpu) =3D lm32bf_h_pc_get;=0A= + CPU_PC_STORE (cpu) =3D lm32bf_h_pc_set;=0A= + CPU_GET_IDATA (cpu) =3D lm32bf_get_idata;=0A= + CPU_MAX_INSNS (cpu) =3D LM32BF_INSN__MAX;=0A= + CPU_INSN_NAME (cpu) =3D cgen_insn_name;=0A= + CPU_FULL_ENGINE_FN (cpu) =3D lm32bf_engine_run_full;=0A= + #if WITH_FAST=0A= + CPU_FAST_ENGINE_FN (cpu) =3D lm32bf_engine_run_fast;=0A= + #else=0A= + CPU_FAST_ENGINE_FN (cpu) =3D lm32bf_engine_run_full;=0A= + #endif=0A= + }=0A= +=20=0A= + const MACH lm32_mach =3D=0A= + {=0A= + "lm32", "lm32", MACH_LM32,=0A= + 32, 32, & lm32_models[0], & lm32bf_imp_properties,=0A= + lm32_init_cpu,=0A= + lm32bf_prepare_run=0A= + };=0A= +=20=0A= Index: sim/lm32/sem-switch.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/sem-switch.c=0A= diff -N sim/lm32/sem-switch.c=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/sem-switch.c 20 Dec 2008 22:02:37 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,1554 ----=0A= + /* Simulator instruction semantics for lm32bf.=0A= +=20=0A= + THIS FILE IS MACHINE GENERATED WITH CGEN.=0A= +=20=0A= + Copyright 1996-2005 Free Software Foundation, Inc.=0A= +=20=0A= + This file is part of the GNU simulators.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 2, or (at your option)=0A= + any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License along= =0A= + with this program; if not, write to the Free Software Foundation, Inc.,= =0A= + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.=0A= +=20=0A= + */=0A= +=20=0A= + #ifdef DEFINE_LABELS=0A= +=20=0A= + /* The labels have the case they have because the enum of insn types=0A= + is all uppercase and in the non-stdc case the insn symbol is built= =0A= + into the enum name. */=0A= +=20=0A= + static struct {=0A= + int index;=0A= + void *label;=0A= + } labels[] =3D {=0A= + { LM32BF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },=0A= + { LM32BF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },=0A= + { LM32BF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },=0A= + { LM32BF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },=0A= + { LM32BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },=0A= + { LM32BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },=0A= + { LM32BF_INSN_ADD, && case_sem_INSN_ADD },=0A= + { LM32BF_INSN_ADDI, && case_sem_INSN_ADDI },=0A= + { LM32BF_INSN_AND, && case_sem_INSN_AND },=0A= + { LM32BF_INSN_ANDI, && case_sem_INSN_ANDI },=0A= + { LM32BF_INSN_ANDHII, && case_sem_INSN_ANDHII },=0A= + { LM32BF_INSN_B, && case_sem_INSN_B },=0A= + { LM32BF_INSN_BI, && case_sem_INSN_BI },=0A= + { LM32BF_INSN_BE, && case_sem_INSN_BE },=0A= + { LM32BF_INSN_BG, && case_sem_INSN_BG },=0A= + { LM32BF_INSN_BGE, && case_sem_INSN_BGE },=0A= + { LM32BF_INSN_BGEU, && case_sem_INSN_BGEU },=0A= + { LM32BF_INSN_BGU, && case_sem_INSN_BGU },=0A= + { LM32BF_INSN_BNE, && case_sem_INSN_BNE },=0A= + { LM32BF_INSN_CALL, && case_sem_INSN_CALL },=0A= + { LM32BF_INSN_CALLI, && case_sem_INSN_CALLI },=0A= + { LM32BF_INSN_CMPE, && case_sem_INSN_CMPE },=0A= + { LM32BF_INSN_CMPEI, && case_sem_INSN_CMPEI },=0A= + { LM32BF_INSN_CMPG, && case_sem_INSN_CMPG },=0A= + { LM32BF_INSN_CMPGI, && case_sem_INSN_CMPGI },=0A= + { LM32BF_INSN_CMPGE, && case_sem_INSN_CMPGE },=0A= + { LM32BF_INSN_CMPGEI, && case_sem_INSN_CMPGEI },=0A= + { LM32BF_INSN_CMPGEU, && case_sem_INSN_CMPGEU },=0A= + { LM32BF_INSN_CMPGEUI, && case_sem_INSN_CMPGEUI },=0A= + { LM32BF_INSN_CMPGU, && case_sem_INSN_CMPGU },=0A= + { LM32BF_INSN_CMPGUI, && case_sem_INSN_CMPGUI },=0A= + { LM32BF_INSN_CMPNE, && case_sem_INSN_CMPNE },=0A= + { LM32BF_INSN_CMPNEI, && case_sem_INSN_CMPNEI },=0A= + { LM32BF_INSN_DIVU, && case_sem_INSN_DIVU },=0A= + { LM32BF_INSN_LB, && case_sem_INSN_LB },=0A= + { LM32BF_INSN_LBU, && case_sem_INSN_LBU },=0A= + { LM32BF_INSN_LH, && case_sem_INSN_LH },=0A= + { LM32BF_INSN_LHU, && case_sem_INSN_LHU },=0A= + { LM32BF_INSN_LW, && case_sem_INSN_LW },=0A= + { LM32BF_INSN_MODU, && case_sem_INSN_MODU },=0A= + { LM32BF_INSN_MUL, && case_sem_INSN_MUL },=0A= + { LM32BF_INSN_MULI, && case_sem_INSN_MULI },=0A= + { LM32BF_INSN_NOR, && case_sem_INSN_NOR },=0A= + { LM32BF_INSN_NORI, && case_sem_INSN_NORI },=0A= + { LM32BF_INSN_OR, && case_sem_INSN_OR },=0A= + { LM32BF_INSN_ORI, && case_sem_INSN_ORI },=0A= + { LM32BF_INSN_ORHII, && case_sem_INSN_ORHII },=0A= + { LM32BF_INSN_RCSR, && case_sem_INSN_RCSR },=0A= + { LM32BF_INSN_SB, && case_sem_INSN_SB },=0A= + { LM32BF_INSN_SEXTB, && case_sem_INSN_SEXTB },=0A= + { LM32BF_INSN_SEXTH, && case_sem_INSN_SEXTH },=0A= + { LM32BF_INSN_SH, && case_sem_INSN_SH },=0A= + { LM32BF_INSN_SL, && case_sem_INSN_SL },=0A= + { LM32BF_INSN_SLI, && case_sem_INSN_SLI },=0A= + { LM32BF_INSN_SR, && case_sem_INSN_SR },=0A= + { LM32BF_INSN_SRI, && case_sem_INSN_SRI },=0A= + { LM32BF_INSN_SRU, && case_sem_INSN_SRU },=0A= + { LM32BF_INSN_SRUI, && case_sem_INSN_SRUI },=0A= + { LM32BF_INSN_SUB, && case_sem_INSN_SUB },=0A= + { LM32BF_INSN_SW, && case_sem_INSN_SW },=0A= + { LM32BF_INSN_USER, && case_sem_INSN_USER },=0A= + { LM32BF_INSN_WCSR, && case_sem_INSN_WCSR },=0A= + { LM32BF_INSN_XOR, && case_sem_INSN_XOR },=0A= + { LM32BF_INSN_XORI, && case_sem_INSN_XORI },=0A= + { LM32BF_INSN_XNOR, && case_sem_INSN_XNOR },=0A= + { LM32BF_INSN_XNORI, && case_sem_INSN_XNORI },=0A= + { LM32BF_INSN_BREAK, && case_sem_INSN_BREAK },=0A= + { LM32BF_INSN_SCALL, && case_sem_INSN_SCALL },=0A= + { 0, 0 }=0A= + };=0A= + int i;=0A= +=20=0A= + for (i =3D 0; labels[i].label !=3D 0; ++i)=0A= + {=0A= + #if FAST_P=0A= + CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab =3D labels[i= ].label;=0A= + #else=0A= + CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab =3D labels[i= ].label;=0A= + #endif=0A= + }=0A= +=20=0A= + #undef DEFINE_LABELS=0A= + #endif /* DEFINE_LABELS */=0A= +=20=0A= + #ifdef DEFINE_SWITCH=0A= +=20=0A= + /* If hyper-fast [well not unnecessarily slow] execution is selected, tur= n=0A= + off frills like tracing and profiling. */=0A= + /* FIXME: A better way would be to have TRACE_RESULT check for something= =0A= + that can cause it to be optimized out. Another way would be to emit= =0A= + special handlers into the instruction "stream". */=0A= +=20=0A= + #if FAST_P=0A= + #undef TRACE_RESULT=0A= + #define TRACE_RESULT(cpu, abuf, name, type, val)=0A= + #endif=0A= +=20=0A= + #undef GET_ATTR=0A= + #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZ= E)=0A= + #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attr= s, CGEN_INSN_##attr)=0A= + #else=0A= + #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attr= s, CGEN_INSN_/**/attr)=0A= + #endif=0A= +=20=0A= + {=0A= +=20=0A= + #if WITH_SCACHE_PBB=0A= +=20=0A= + /* Branch to next handler without going around main loop. */=0A= + #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case=0A= + SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)=0A= +=20=0A= + #else /* ! WITH_SCACHE_PBB */=0A= +=20=0A= + #define NEXT(vpc) BREAK (sem)=0A= + #ifdef __GNUC__=0A= + #if FAST_P=0A= + SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)=0A= + #else=0A= + SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)=0A= + #endif=0A= + #else=0A= + SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)=0A= + #endif=0A= +=20=0A= + #endif /* ! WITH_SCACHE_PBB */=0A= +=20=0A= + {=0A= +=20=0A= + CASE (sem, INSN_X_INVALID) : /* --invalid-- */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= +=20=0A= + {=0A= + /* Update the recorded pc in the cpu state struct.=0A= + Only necessary for WITH_SCACHE case, but to avoid the=0A= + conditional compilation .... */=0A= + SET_H_PC (pc);=0A= + /* Virtual insns have zero size. Overwrite vpc with address of next = insn=0A= + using the default-insn-bitsize spec. When executing insns in para= llel=0A= + we may want to queue the fault and continue execution. */=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= + vpc =3D sim_engine_invalid_insn (current_cpu, pc, vpc);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_X_AFTER) : /* --after-- */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= +=20=0A= + {=0A= + #if WITH_SCACHE_PBB_LM32BF=0A= + lm32bf_pbb_after (current_cpu, sem_arg);=0A= + #endif=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_X_BEFORE) : /* --before-- */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= +=20=0A= + {=0A= + #if WITH_SCACHE_PBB_LM32BF=0A= + lm32bf_pbb_before (current_cpu, sem_arg);=0A= + #endif=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= +=20=0A= + {=0A= + #if WITH_SCACHE_PBB_LM32BF=0A= + #ifdef DEFINE_SWITCH=0A= + vpc =3D lm32bf_pbb_cti_chain (current_cpu, sem_arg,=0A= + pbb_br_type, pbb_br_npc);=0A= + BREAK (sem);=0A= + #else=0A= + /* FIXME: Allow provision of explicit ifmt spec in insn spec. */=0A= + vpc =3D lm32bf_pbb_cti_chain (current_cpu, sem_arg,=0A= + CPU_PBB_BR_TYPE (current_cpu),=0A= + CPU_PBB_BR_NPC (current_cpu));=0A= + #endif=0A= + #endif=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_X_CHAIN) : /* --chain-- */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= +=20=0A= + {=0A= + #if WITH_SCACHE_PBB_LM32BF=0A= + vpc =3D lm32bf_pbb_chain (current_cpu, sem_arg);=0A= + #ifdef DEFINE_SWITCH=0A= + BREAK (sem);=0A= + #endif=0A= + #endif=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_X_BEGIN) : /* --begin-- */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= +=20=0A= + {=0A= + #if WITH_SCACHE_PBB_LM32BF=0A= + #if defined DEFINE_SWITCH || defined FAST_P=0A= + /* In the switch case FAST_P is a constant, allowing several optimiza= tions=0A= + in any called inline functions. */=0A= + vpc =3D lm32bf_pbb_begin (current_cpu, FAST_P);=0A= + #else=0A= + #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */=0A= + vpc =3D lm32bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (c= urrent_cpu)));=0A= + #else=0A= + vpc =3D lm32bf_pbb_begin (current_cpu, 0);=0A= + #endif=0A= + #endif=0A= + #endif=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_ADD) : /* add $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ADDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_ADDI) : /* addi $r1,$r0,$imm */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (= f_imm))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_AND) : /* and $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ANDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_ANDI) : /* andi $r1,$r0,$uimm */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ANDSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));= =0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_ANDHII) : /* andhi $r1,$r0,$hi16 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ANDSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16))= ;=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_B) : /* b $r0 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + USI opval =3D lm32bf_b_insn (current_cpu, CPU (h_gr[FLD (f_r0)]), FLD= (f_r0));=0A= + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= +=20=0A= + SEM_BRANCH_FINI (vpc);=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_BI) : /* bi $call */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_bi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + USI opval =3D EXTSISI (FLD (i_call));=0A= + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= +=20=0A= + SEM_BRANCH_FINI (vpc);=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_BE) : /* be $r0,$r1,$branch */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + if (EQSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {=0A= + {=0A= + USI opval =3D FLD (i_branch);=0A= + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= + written |=3D (1 << 3);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= + }=0A= +=20=0A= + abuf->written =3D written;=0A= + SEM_BRANCH_FINI (vpc);=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_BG) : /* bg $r0,$r1,$branch */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + if (GTSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {=0A= + {=0A= + USI opval =3D FLD (i_branch);=0A= + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= + written |=3D (1 << 3);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= + }=0A= +=20=0A= + abuf->written =3D written;=0A= + SEM_BRANCH_FINI (vpc);=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_BGE) : /* bge $r0,$r1,$branch */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + if (GESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {=0A= + {=0A= + USI opval =3D FLD (i_branch);=0A= + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= + written |=3D (1 << 3);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= + }=0A= +=20=0A= + abuf->written =3D written;=0A= + SEM_BRANCH_FINI (vpc);=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_BGEU) : /* bgeu $r0,$r1,$branch */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + if (GEUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {=0A= + {=0A= + USI opval =3D FLD (i_branch);=0A= + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= + written |=3D (1 << 3);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= + }=0A= +=20=0A= + abuf->written =3D written;=0A= + SEM_BRANCH_FINI (vpc);=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_BGU) : /* bgu $r0,$r1,$branch */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + if (GTUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {=0A= + {=0A= + USI opval =3D FLD (i_branch);=0A= + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= + written |=3D (1 << 3);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= + }=0A= +=20=0A= + abuf->written =3D written;=0A= + SEM_BRANCH_FINI (vpc);=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_BNE) : /* bne $r0,$r1,$branch */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + if (NESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {=0A= + {=0A= + USI opval =3D FLD (i_branch);=0A= + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= + written |=3D (1 << 3);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= + }=0A= +=20=0A= + abuf->written =3D written;=0A= + SEM_BRANCH_FINI (vpc);=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_CALL) : /* call $r0 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + {=0A= + SI opval =3D ADDSI (pc, 4);=0A= + CPU (h_gr[((UINT) 29)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= + {=0A= + USI opval =3D CPU (h_gr[FLD (f_r0)]);=0A= + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= + }=0A= +=20=0A= + SEM_BRANCH_FINI (vpc);=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_CALLI) : /* calli $call */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_bi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + {=0A= + SI opval =3D ADDSI (pc, 4);=0A= + CPU (h_gr[((UINT) 29)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= + {=0A= + USI opval =3D EXTSISI (FLD (i_call));=0A= + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= + }=0A= +=20=0A= + SEM_BRANCH_FINI (vpc);=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_CMPE) : /* cmpe $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D EQSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_CMPEI) : /* cmpei $r1,$r0,$imm */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D EQSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f= _imm))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_CMPG) : /* cmpg $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GTSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_CMPGI) : /* cmpgi $r1,$r0,$imm */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GTSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f= _imm))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_CMPGE) : /* cmpge $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_CMPGEI) : /* cmpgei $r1,$r0,$imm */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GESI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f= _imm))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_CMPGEU) : /* cmpgeu $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GEUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_CMPGEUI) : /* cmpgeui $r1,$r0,$uimm */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GEUSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));= =0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_CMPGU) : /* cmpgu $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GTUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_CMPGUI) : /* cmpgui $r1,$r0,$uimm */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GTUSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));= =0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_CMPNE) : /* cmpne $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D NESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_CMPNEI) : /* cmpnei $r1,$r0,$imm */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D NESI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f= _imm))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_DIVU) : /* divu $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + USI opval =3D lm32bf_divu_insn (current_cpu, pc, FLD (f_r0), FLD (f_r= 1), FLD (f_r2));=0A= + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= +=20=0A= + SEM_BRANCH_FINI (vpc);=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_LB) : /* lb $r1,($r0+$imm) */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD= (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_LBU) : /* lbu $r1,($r0+$imm) */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FL= D (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_LH) : /* lh $r1,($r0+$imm) */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD= (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_LHU) : /* lhu $r1,($r0+$imm) */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FL= D (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_LW) : /* lw $r1,($r0+$imm) */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)])= , EXTHISI (TRUNCSIHI (FLD (f_imm)))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_MODU) : /* modu $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + USI opval =3D lm32bf_modu_insn (current_cpu, pc, FLD (f_r0), FLD (f_r= 1), FLD (f_r2));=0A= + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= +=20=0A= + SEM_BRANCH_FINI (vpc);=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_MUL) : /* mul $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D MULSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_MULI) : /* muli $r1,$r0,$imm */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D MULSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (= f_imm))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_NOR) : /* nor $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D INVSI (ORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1= )])));=0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_NORI) : /* nori $r1,$r0,$uimm */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D INVSI (ORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_ui= mm))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_OR) : /* or $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_ORI) : /* ori $r1,$r0,$lo16 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));= =0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_ORHII) : /* orhi $r1,$r0,$hi16 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ORSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16));= =0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_RCSR) : /* rcsr $r2,$csr */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_rcsr.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D CPU (h_csr[FLD (f_csr)]);=0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_SB) : /* sb ($r0+$imm),$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + QI opval =3D CPU (h_gr[FLD (f_r1)]);=0A= + SETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TR= UNCSIHI (FLD (f_imm)))), opval);=0A= + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_SEXTB) : /* sextb $r2,$r0 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D EXTQISI (TRUNCSIQI (CPU (h_gr[FLD (f_r0)])));=0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_SEXTH) : /* sexth $r2,$r0 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D EXTHISI (TRUNCSIHI (CPU (h_gr[FLD (f_r0)])));=0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_SH) : /* sh ($r0+$imm),$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + HI opval =3D CPU (h_gr[FLD (f_r1)]);=0A= + SETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TR= UNCSIHI (FLD (f_imm)))), opval);=0A= + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_SL) : /* sl $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D SLLSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_SLI) : /* sli $r1,$r0,$imm */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D SLLSI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_SR) : /* sr $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D SRASI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_SRI) : /* sri $r1,$r0,$imm */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D SRASI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_SRU) : /* sru $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D SRLSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_SRUI) : /* srui $r1,$r0,$imm */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D SRLSI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_SUB) : /* sub $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D SUBSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_SW) : /* sw ($r0+$imm),$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D CPU (h_gr[FLD (f_r1)]);=0A= + SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TR= UNCSIHI (FLD (f_imm)))), opval);=0A= + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_USER) : /* user $r2,$r0,$r1,$user */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D lm32bf_user_insn (current_cpu, CPU (h_gr[FLD (f_r0)]), C= PU (h_gr[FLD (f_r1)]), FLD (f_user));=0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_WCSR) : /* wcsr $csr,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_wcsr.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + lm32bf_wcsr_insn (current_cpu, FLD (f_csr), CPU (h_gr[FLD (f_r1)]));=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_XOR) : /* xor $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D XORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_XORI) : /* xori $r1,$r0,$uimm */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D XORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));= =0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_XNOR) : /* xnor $r2,$r0,$r1 */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D INVSI (XORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r= 1)])));=0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_XNORI) : /* xnori $r1,$r0,$uimm */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D INVSI (XORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_u= imm))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_BREAK) : /* break */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + USI opval =3D lm32bf_break_insn (current_cpu, pc);=0A= + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= +=20=0A= + SEM_BRANCH_FINI (vpc);=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= + CASE (sem, INSN_SCALL) : /* scall */=0A= + {=0A= + SEM_ARG sem_arg =3D SEM_SEM_ARG (vpc, sc);=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + USI opval =3D lm32bf_scall_insn (current_cpu, pc);=0A= + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= +=20=0A= + SEM_BRANCH_FINI (vpc);=0A= + #undef FLD=0A= + }=0A= + NEXT (vpc);=0A= +=20=0A= +=20=0A= + }=0A= + ENDSWITCH (sem) /* End of semantic switch. */=0A= +=20=0A= + /* At this point `vpc' contains the next insn to execute. */=0A= + }=0A= +=20=0A= + #undef DEFINE_SWITCH=0A= + #endif /* DEFINE_SWITCH */=0A= Index: sim/lm32/sem.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/sem.c=0A= diff -N sim/lm32/sem.c=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/sem.c 20 Dec 2008 22:02:38 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,1669 ----=0A= + /* Simulator instruction semantics for lm32bf.=0A= +=20=0A= + THIS FILE IS MACHINE GENERATED WITH CGEN.=0A= +=20=0A= + Copyright 1996-2005 Free Software Foundation, Inc.=0A= +=20=0A= + This file is part of the GNU simulators.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify=0A= + it under the terms of the GNU General Public License as published by=0A= + the Free Software Foundation; either version 2, or (at your option)=0A= + any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License along= =0A= + with this program; if not, write to the Free Software Foundation, Inc.,= =0A= + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.=0A= +=20=0A= + */=0A= +=20=0A= + #define WANT_CPU lm32bf=0A= + #define WANT_CPU_LM32BF=0A= +=20=0A= + #include "sim-main.h"=0A= + #include "cgen-mem.h"=0A= + #include "cgen-ops.h"=0A= +=20=0A= + #undef GET_ATTR=0A= + #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZ= E)=0A= + #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attr= s, CGEN_INSN_##attr)=0A= + #else=0A= + #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attr= s, CGEN_INSN_/**/attr)=0A= + #endif=0A= +=20=0A= + /* This is used so that we can compile two copies of the semantic code,= =0A= + one with full feature support and one without that runs fast(er).=0A= + FAST_P, when desired, is defined on the command line, -DFAST_P=3D1. *= /=0A= + #if FAST_P=0A= + #define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)=0A= + #undef TRACE_RESULT=0A= + #define TRACE_RESULT(cpu, abuf, name, type, val)=0A= + #else=0A= + #define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)=0A= + #endif=0A= +=20=0A= + /* x-invalid: --invalid-- */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= +=20=0A= + {=0A= + /* Update the recorded pc in the cpu state struct.=0A= + Only necessary for WITH_SCACHE case, but to avoid the=0A= + conditional compilation .... */=0A= + SET_H_PC (pc);=0A= + /* Virtual insns have zero size. Overwrite vpc with address of next = insn=0A= + using the default-insn-bitsize spec. When executing insns in para= llel=0A= + we may want to queue the fault and continue execution. */=0A= + vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= + vpc =3D sim_engine_invalid_insn (current_cpu, pc, vpc);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* x-after: --after-- */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= +=20=0A= + {=0A= + #if WITH_SCACHE_PBB_LM32BF=0A= + lm32bf_pbb_after (current_cpu, sem_arg);=0A= + #endif=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* x-before: --before-- */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= +=20=0A= + {=0A= + #if WITH_SCACHE_PBB_LM32BF=0A= + lm32bf_pbb_before (current_cpu, sem_arg);=0A= + #endif=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* x-cti-chain: --cti-chain-- */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)= =0A= + {=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= +=20=0A= + {=0A= + #if WITH_SCACHE_PBB_LM32BF=0A= + #ifdef DEFINE_SWITCH=0A= + vpc =3D lm32bf_pbb_cti_chain (current_cpu, sem_arg,=0A= + pbb_br_type, pbb_br_npc);=0A= + BREAK (sem);=0A= + #else=0A= + /* FIXME: Allow provision of explicit ifmt spec in insn spec. */=0A= + vpc =3D lm32bf_pbb_cti_chain (current_cpu, sem_arg,=0A= + CPU_PBB_BR_TYPE (current_cpu),=0A= + CPU_PBB_BR_NPC (current_cpu));=0A= + #endif=0A= + #endif=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* x-chain: --chain-- */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= +=20=0A= + {=0A= + #if WITH_SCACHE_PBB_LM32BF=0A= + vpc =3D lm32bf_pbb_chain (current_cpu, sem_arg);=0A= + #ifdef DEFINE_SWITCH=0A= + BREAK (sem);=0A= + #endif=0A= + #endif=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* x-begin: --begin-- */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 0);=0A= +=20=0A= + {=0A= + #if WITH_SCACHE_PBB_LM32BF=0A= + #if defined DEFINE_SWITCH || defined FAST_P=0A= + /* In the switch case FAST_P is a constant, allowing several optimiza= tions=0A= + in any called inline functions. */=0A= + vpc =3D lm32bf_pbb_begin (current_cpu, FAST_P);=0A= + #else=0A= + #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */=0A= + vpc =3D lm32bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (c= urrent_cpu)));=0A= + #else=0A= + vpc =3D lm32bf_pbb_begin (current_cpu, 0);=0A= + #endif=0A= + #endif=0A= + #endif=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* add: add $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ADDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* addi: addi $r1,$r0,$imm */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (= f_imm))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* and: and $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ANDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* andi: andi $r1,$r0,$uimm */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,andi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ANDSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));= =0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* andhii: andhi $r1,$r0,$hi16 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,andhii) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ANDSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16))= ;=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* b: b $r0 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,b) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + USI opval =3D lm32bf_b_insn (current_cpu, CPU (h_gr[FLD (f_r0)]), FLD= (f_r0));=0A= + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= +=20=0A= + SEM_BRANCH_FINI (vpc);=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* bi: bi $call */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,bi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_bi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + USI opval =3D EXTSISI (FLD (i_call));=0A= + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= +=20=0A= + SEM_BRANCH_FINI (vpc);=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* be: be $r0,$r1,$branch */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,be) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + if (EQSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {=0A= + {=0A= + USI opval =3D FLD (i_branch);=0A= + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= + written |=3D (1 << 3);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= + }=0A= +=20=0A= + abuf->written =3D written;=0A= + SEM_BRANCH_FINI (vpc);=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* bg: bg $r0,$r1,$branch */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,bg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + if (GTSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {=0A= + {=0A= + USI opval =3D FLD (i_branch);=0A= + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= + written |=3D (1 << 3);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= + }=0A= +=20=0A= + abuf->written =3D written;=0A= + SEM_BRANCH_FINI (vpc);=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* bge: bge $r0,$r1,$branch */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + if (GESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {=0A= + {=0A= + USI opval =3D FLD (i_branch);=0A= + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= + written |=3D (1 << 3);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= + }=0A= +=20=0A= + abuf->written =3D written;=0A= + SEM_BRANCH_FINI (vpc);=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* bgeu: bgeu $r0,$r1,$branch */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,bgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + if (GEUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {=0A= + {=0A= + USI opval =3D FLD (i_branch);=0A= + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= + written |=3D (1 << 3);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= + }=0A= +=20=0A= + abuf->written =3D written;=0A= + SEM_BRANCH_FINI (vpc);=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* bgu: bgu $r0,$r1,$branch */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,bgu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + if (GTUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {=0A= + {=0A= + USI opval =3D FLD (i_branch);=0A= + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= + written |=3D (1 << 3);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= + }=0A= +=20=0A= + abuf->written =3D written;=0A= + SEM_BRANCH_FINI (vpc);=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* bne: bne $r0,$r1,$branch */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + if (NESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {=0A= + {=0A= + USI opval =3D FLD (i_branch);=0A= + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);=0A= + written |=3D (1 << 3);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= + }=0A= +=20=0A= + abuf->written =3D written;=0A= + SEM_BRANCH_FINI (vpc);=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* call: call $r0 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,call) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_be.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + {=0A= + SI opval =3D ADDSI (pc, 4);=0A= + CPU (h_gr[((UINT) 29)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= + {=0A= + USI opval =3D CPU (h_gr[FLD (f_r0)]);=0A= + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= + }=0A= +=20=0A= + SEM_BRANCH_FINI (vpc);=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* calli: calli $call */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,calli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_bi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + {=0A= + SI opval =3D ADDSI (pc, 4);=0A= + CPU (h_gr[((UINT) 29)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= + {=0A= + USI opval =3D EXTSISI (FLD (i_call));=0A= + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= + }=0A= +=20=0A= + SEM_BRANCH_FINI (vpc);=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* cmpe: cmpe $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,cmpe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D EQSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* cmpei: cmpei $r1,$r0,$imm */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,cmpei) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D EQSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f= _imm))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* cmpg: cmpg $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,cmpg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GTSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* cmpgi: cmpgi $r1,$r0,$imm */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,cmpgi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GTSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f= _imm))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* cmpge: cmpge $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,cmpge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* cmpgei: cmpgei $r1,$r0,$imm */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,cmpgei) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GESI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f= _imm))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* cmpgeu: cmpgeu $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,cmpgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GEUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* cmpgeui: cmpgeui $r1,$r0,$uimm */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,cmpgeui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GEUSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));= =0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* cmpgu: cmpgu $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,cmpgu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GTUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* cmpgui: cmpgui $r1,$r0,$uimm */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,cmpgui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GTUSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));= =0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* cmpne: cmpne $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,cmpne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D NESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* cmpnei: cmpnei $r1,$r0,$imm */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,cmpnei) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D NESI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f= _imm))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* divu: divu $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + USI opval =3D lm32bf_divu_insn (current_cpu, pc, FLD (f_r0), FLD (f_r= 1), FLD (f_r2));=0A= + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= +=20=0A= + SEM_BRANCH_FINI (vpc);=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* lb: lb $r1,($r0+$imm) */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,lb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD= (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* lbu: lbu $r1,($r0+$imm) */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,lbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FL= D (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* lh: lh $r1,($r0+$imm) */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,lh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD= (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* lhu: lhu $r1,($r0+$imm) */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,lhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FL= D (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* lw: lw $r1,($r0+$imm) */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,lw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)])= , EXTHISI (TRUNCSIHI (FLD (f_imm)))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* modu: modu $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,modu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + USI opval =3D lm32bf_modu_insn (current_cpu, pc, FLD (f_r0), FLD (f_r= 1), FLD (f_r2));=0A= + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= +=20=0A= + SEM_BRANCH_FINI (vpc);=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* mul: mul $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D MULSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* muli: muli $r1,$r0,$imm */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,muli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D MULSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (= f_imm))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* nor: nor $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,nor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D INVSI (ORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1= )])));=0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* nori: nori $r1,$r0,$uimm */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,nori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D INVSI (ORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_ui= mm))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* or: or $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* ori: ori $r1,$r0,$lo16 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,ori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));= =0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* orhii: orhi $r1,$r0,$hi16 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,orhii) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D ORSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16));= =0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* rcsr: rcsr $r2,$csr */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,rcsr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_rcsr.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D CPU (h_csr[FLD (f_csr)]);=0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* sb: sb ($r0+$imm),$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,sb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + QI opval =3D CPU (h_gr[FLD (f_r1)]);=0A= + SETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TR= UNCSIHI (FLD (f_imm)))), opval);=0A= + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* sextb: sextb $r2,$r0 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,sextb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D EXTQISI (TRUNCSIQI (CPU (h_gr[FLD (f_r0)])));=0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* sexth: sexth $r2,$r0 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,sexth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D EXTHISI (TRUNCSIHI (CPU (h_gr[FLD (f_r0)])));=0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* sh: sh ($r0+$imm),$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,sh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + HI opval =3D CPU (h_gr[FLD (f_r1)]);=0A= + SETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TR= UNCSIHI (FLD (f_imm)))), opval);=0A= + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* sl: sl $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,sl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D SLLSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* sli: sli $r1,$r0,$imm */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,sli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D SLLSI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* sr: sr $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,sr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D SRASI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* sri: sri $r1,$r0,$imm */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,sri) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D SRASI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* sru: sru $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,sru) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D SRLSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* srui: srui $r1,$r0,$imm */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,srui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D SRLSI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* sub: sub $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D SUBSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* sw: sw ($r0+$imm),$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,sw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_addi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D CPU (h_gr[FLD (f_r1)]);=0A= + SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TR= UNCSIHI (FLD (f_imm)))), opval);=0A= + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* user: user $r2,$r0,$r1,$user */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,user) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D lm32bf_user_insn (current_cpu, CPU (h_gr[FLD (f_r0)]), C= PU (h_gr[FLD (f_r1)]), FLD (f_user));=0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* wcsr: wcsr $csr,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,wcsr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_wcsr.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + lm32bf_wcsr_insn (current_cpu, FLD (f_csr), CPU (h_gr[FLD (f_r1)]));=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* xor: xor $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D XORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));= =0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* xori: xori $r1,$r0,$uimm */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,xori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D XORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));= =0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* xnor: xnor $r2,$r0,$r1 */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,xnor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_user.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D INVSI (XORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r= 1)])));=0A= + CPU (h_gr[FLD (f_r2)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* xnori: xnori $r1,$r0,$uimm */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,xnori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.sfmt_andi.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + SI opval =3D INVSI (XORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_u= imm))));=0A= + CPU (h_gr[FLD (f_r1)]) =3D opval;=0A= + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);=0A= + }=0A= +=20=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* break: break */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,break) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + USI opval =3D lm32bf_break_insn (current_cpu, pc);=0A= + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= +=20=0A= + SEM_BRANCH_FINI (vpc);=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* scall: scall */=0A= +=20=0A= + static SEM_PC=0A= + SEM_FN_NAME (lm32bf,scall) (SIM_CPU *current_cpu, SEM_ARG sem_arg)=0A= + {=0A= + #define FLD(f) abuf->fields.fmt_empty.f=0A= + ARGBUF *abuf =3D SEM_ARGBUF (sem_arg);=0A= + int UNUSED written =3D 0;=0A= + IADDR UNUSED pc =3D abuf->addr;=0A= + SEM_BRANCH_INIT=0A= + SEM_PC vpc =3D SEM_NEXT_VPC (sem_arg, pc, 4);=0A= +=20=0A= + {=0A= + USI opval =3D lm32bf_scall_insn (current_cpu, pc);=0A= + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);=0A= + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);=0A= + }=0A= +=20=0A= + SEM_BRANCH_FINI (vpc);=0A= + return vpc;=0A= + #undef FLD=0A= + }=0A= +=20=0A= + /* Table of all semantic fns. */=0A= +=20=0A= + static const struct sem_fn_desc sem_fns[] =3D {=0A= + { LM32BF_INSN_X_INVALID, SEM_FN_NAME (lm32bf,x_invalid) },=0A= + { LM32BF_INSN_X_AFTER, SEM_FN_NAME (lm32bf,x_after) },=0A= + { LM32BF_INSN_X_BEFORE, SEM_FN_NAME (lm32bf,x_before) },=0A= + { LM32BF_INSN_X_CTI_CHAIN, SEM_FN_NAME (lm32bf,x_cti_chain) },=0A= + { LM32BF_INSN_X_CHAIN, SEM_FN_NAME (lm32bf,x_chain) },=0A= + { LM32BF_INSN_X_BEGIN, SEM_FN_NAME (lm32bf,x_begin) },=0A= + { LM32BF_INSN_ADD, SEM_FN_NAME (lm32bf,add) },=0A= + { LM32BF_INSN_ADDI, SEM_FN_NAME (lm32bf,addi) },=0A= + { LM32BF_INSN_AND, SEM_FN_NAME (lm32bf,and) },=0A= + { LM32BF_INSN_ANDI, SEM_FN_NAME (lm32bf,andi) },=0A= + { LM32BF_INSN_ANDHII, SEM_FN_NAME (lm32bf,andhii) },=0A= + { LM32BF_INSN_B, SEM_FN_NAME (lm32bf,b) },=0A= + { LM32BF_INSN_BI, SEM_FN_NAME (lm32bf,bi) },=0A= + { LM32BF_INSN_BE, SEM_FN_NAME (lm32bf,be) },=0A= + { LM32BF_INSN_BG, SEM_FN_NAME (lm32bf,bg) },=0A= + { LM32BF_INSN_BGE, SEM_FN_NAME (lm32bf,bge) },=0A= + { LM32BF_INSN_BGEU, SEM_FN_NAME (lm32bf,bgeu) },=0A= + { LM32BF_INSN_BGU, SEM_FN_NAME (lm32bf,bgu) },=0A= + { LM32BF_INSN_BNE, SEM_FN_NAME (lm32bf,bne) },=0A= + { LM32BF_INSN_CALL, SEM_FN_NAME (lm32bf,call) },=0A= + { LM32BF_INSN_CALLI, SEM_FN_NAME (lm32bf,calli) },=0A= + { LM32BF_INSN_CMPE, SEM_FN_NAME (lm32bf,cmpe) },=0A= + { LM32BF_INSN_CMPEI, SEM_FN_NAME (lm32bf,cmpei) },=0A= + { LM32BF_INSN_CMPG, SEM_FN_NAME (lm32bf,cmpg) },=0A= + { LM32BF_INSN_CMPGI, SEM_FN_NAME (lm32bf,cmpgi) },=0A= + { LM32BF_INSN_CMPGE, SEM_FN_NAME (lm32bf,cmpge) },=0A= + { LM32BF_INSN_CMPGEI, SEM_FN_NAME (lm32bf,cmpgei) },=0A= + { LM32BF_INSN_CMPGEU, SEM_FN_NAME (lm32bf,cmpgeu) },=0A= + { LM32BF_INSN_CMPGEUI, SEM_FN_NAME (lm32bf,cmpgeui) },=0A= + { LM32BF_INSN_CMPGU, SEM_FN_NAME (lm32bf,cmpgu) },=0A= + { LM32BF_INSN_CMPGUI, SEM_FN_NAME (lm32bf,cmpgui) },=0A= + { LM32BF_INSN_CMPNE, SEM_FN_NAME (lm32bf,cmpne) },=0A= + { LM32BF_INSN_CMPNEI, SEM_FN_NAME (lm32bf,cmpnei) },=0A= + { LM32BF_INSN_DIVU, SEM_FN_NAME (lm32bf,divu) },=0A= + { LM32BF_INSN_LB, SEM_FN_NAME (lm32bf,lb) },=0A= + { LM32BF_INSN_LBU, SEM_FN_NAME (lm32bf,lbu) },=0A= + { LM32BF_INSN_LH, SEM_FN_NAME (lm32bf,lh) },=0A= + { LM32BF_INSN_LHU, SEM_FN_NAME (lm32bf,lhu) },=0A= + { LM32BF_INSN_LW, SEM_FN_NAME (lm32bf,lw) },=0A= + { LM32BF_INSN_MODU, SEM_FN_NAME (lm32bf,modu) },=0A= + { LM32BF_INSN_MUL, SEM_FN_NAME (lm32bf,mul) },=0A= + { LM32BF_INSN_MULI, SEM_FN_NAME (lm32bf,muli) },=0A= + { LM32BF_INSN_NOR, SEM_FN_NAME (lm32bf,nor) },=0A= + { LM32BF_INSN_NORI, SEM_FN_NAME (lm32bf,nori) },=0A= + { LM32BF_INSN_OR, SEM_FN_NAME (lm32bf,or) },=0A= + { LM32BF_INSN_ORI, SEM_FN_NAME (lm32bf,ori) },=0A= + { LM32BF_INSN_ORHII, SEM_FN_NAME (lm32bf,orhii) },=0A= + { LM32BF_INSN_RCSR, SEM_FN_NAME (lm32bf,rcsr) },=0A= + { LM32BF_INSN_SB, SEM_FN_NAME (lm32bf,sb) },=0A= + { LM32BF_INSN_SEXTB, SEM_FN_NAME (lm32bf,sextb) },=0A= + { LM32BF_INSN_SEXTH, SEM_FN_NAME (lm32bf,sexth) },=0A= + { LM32BF_INSN_SH, SEM_FN_NAME (lm32bf,sh) },=0A= + { LM32BF_INSN_SL, SEM_FN_NAME (lm32bf,sl) },=0A= + { LM32BF_INSN_SLI, SEM_FN_NAME (lm32bf,sli) },=0A= + { LM32BF_INSN_SR, SEM_FN_NAME (lm32bf,sr) },=0A= + { LM32BF_INSN_SRI, SEM_FN_NAME (lm32bf,sri) },=0A= + { LM32BF_INSN_SRU, SEM_FN_NAME (lm32bf,sru) },=0A= + { LM32BF_INSN_SRUI, SEM_FN_NAME (lm32bf,srui) },=0A= + { LM32BF_INSN_SUB, SEM_FN_NAME (lm32bf,sub) },=0A= + { LM32BF_INSN_SW, SEM_FN_NAME (lm32bf,sw) },=0A= + { LM32BF_INSN_USER, SEM_FN_NAME (lm32bf,user) },=0A= + { LM32BF_INSN_WCSR, SEM_FN_NAME (lm32bf,wcsr) },=0A= + { LM32BF_INSN_XOR, SEM_FN_NAME (lm32bf,xor) },=0A= + { LM32BF_INSN_XORI, SEM_FN_NAME (lm32bf,xori) },=0A= + { LM32BF_INSN_XNOR, SEM_FN_NAME (lm32bf,xnor) },=0A= + { LM32BF_INSN_XNORI, SEM_FN_NAME (lm32bf,xnori) },=0A= + { LM32BF_INSN_BREAK, SEM_FN_NAME (lm32bf,break) },=0A= + { LM32BF_INSN_SCALL, SEM_FN_NAME (lm32bf,scall) },=0A= + { 0, 0 }=0A= + };=0A= +=20=0A= + /* Add the semantic fns to IDESC_TABLE. */=0A= +=20=0A= + void=0A= + SEM_FN_NAME (lm32bf,init_idesc_table) (SIM_CPU *current_cpu)=0A= + {=0A= + IDESC *idesc_table =3D CPU_IDESC (current_cpu);=0A= + const struct sem_fn_desc *sf;=0A= + int mach_num =3D MACH_NUM (CPU_MACH (current_cpu));=0A= +=20=0A= + for (sf =3D &sem_fns[0]; sf->fn !=3D 0; ++sf)=0A= + {=0A= + const CGEN_INSN *insn =3D idesc_table[sf->index].idata;=0A= + int valid_p =3D (CGEN_INSN_VIRTUAL_P (insn)=0A= + || CGEN_INSN_MACH_HAS_P (insn, mach_num));=0A= + #if FAST_P=0A= + if (valid_p)=0A= + idesc_table[sf->index].sem_fast =3D sf->fn;=0A= + else=0A= + idesc_table[sf->index].sem_fast =3D SEM_FN_NAME (lm32bf,x_invalid);=0A= + #else=0A= + if (valid_p)=0A= + idesc_table[sf->index].sem_full =3D sf->fn;=0A= + else=0A= + idesc_table[sf->index].sem_full =3D SEM_FN_NAME (lm32bf,x_invalid);=0A= + #endif=0A= + }=0A= + }=0A= +=20=0A= Index: sim/lm32/sim-if.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/sim-if.c=0A= diff -N sim/lm32/sim-if.c=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/sim-if.c 20 Dec 2008 22:02:38 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,286 ----=0A= + /* Main simulator entry points specific to Lattice Mico32.=0A= + Written by Jon Beniston =0A= +=20=20=20=20=0A= + This file is part of GDB.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify= =0A= + it under the terms of the GNU General Public License as published by= =0A= + the Free Software Foundation; either version 3 of the License, or=0A= + (at your option) any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program. If not, see . = */=0A= +=20=0A= + #include "sim-main.h"=0A= + #include "sim-options.h"=0A= + #include "libiberty.h"=0A= + #include "bfd.h"=0A= +=20=0A= + #ifdef HAVE_STDLIB_H=0A= + #include =0A= + #endif=0A= +=20=0A= + static void free_state (SIM_DESC);=0A= + static void print_lm32_misc_cpu (SIM_CPU *cpu, int verbose);=0A= + static DECLARE_OPTION_HANDLER (lm32_option_handler);=0A= +=20=0A= + enum {=0A= + OPTION_ENDIAN =3D OPTION_START,=0A= + };=0A= +=20=0A= + /* GDB passes -E, even though it's fixed, so we have to handle it here. c= ommon code only handles it if SIM_HAVE_BIENDIAN is defined, which it isn't = for lm32 */=0A= + static const OPTION lm32_options[] =3D=0A= + {=0A= + { {"endian", required_argument, NULL, OPTION_ENDIAN},=0A= + 'E', "big", "Set endianness",=0A= + lm32_option_handler },=0A= + { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }=0A= + };=0A= +=20=0A= + /* Records simulator descriptor so utilities like lm32_dump_regs can be= =0A= + called from gdb. */=0A= + SIM_DESC current_state;=0A= + =0C=0A= + /* Cover function of sim_state_free to free the cpu buffers as well. */= =0A= +=20=0A= + static void=0A= + free_state (SIM_DESC sd)=0A= + {=0A= + if (STATE_MODULES (sd) !=3D NULL)=0A= + sim_module_uninstall (sd);=0A= + sim_cpu_free_all (sd);=0A= + sim_state_free (sd);=0A= + }=0A= +=20=0A= + /* Find memory range used by program */=0A= +=20=0A= + static unsigned long=20=0A= + find_base (bfd *prog_bfd)=0A= + {=0A= + int found;=0A= + unsigned long base =3D ~(0UL);=0A= + asection *s;=0A= +=20=0A= + found =3D 0;=0A= + for (s =3D prog_bfd->sections; s; s =3D s->next)=0A= + {=0A= + if ( (strcmp (bfd_get_section_name (prog_bfd, s), ".boot") =3D=3D= 0)=0A= + || (strcmp (bfd_get_section_name (prog_bfd, s), ".text") =3D=3D= 0)=0A= + || (strcmp (bfd_get_section_name (prog_bfd, s), ".data") =3D=3D= 0)=0A= + || (strcmp (bfd_get_section_name (prog_bfd, s), ".bss") =3D=3D = 0)=0A= + )=20=0A= + {=0A= + if (!found)=20=0A= + {=0A= + base =3D bfd_get_section_vma (prog_bfd, s);=0A= + found =3D 1;=0A= + }=20=0A= + else=20=0A= + base =3D bfd_get_section_vma (prog_bfd, s) < base ? bfd_get_s= ection_vma (prog_bfd, s) : base;=0A= + }=0A= + }=0A= + return base & ~(0xffffUL);=0A= + }=0A= +=20=0A= + static unsigned long=20=0A= + find_limit (bfd *prog_bfd)=0A= + {=0A= + struct bfd_symbol **asymbols;=0A= + long symsize;=0A= + long symbol_count;=0A= + long s;=0A= +=20=0A= + symsize =3D bfd_get_symtab_upper_bound (prog_bfd);=0A= + if (symsize < 0)=0A= + return 0;=0A= + asymbols =3D (asymbol **) xmalloc (symsize);=0A= + symbol_count =3D bfd_canonicalize_symtab (prog_bfd, asymbols);=0A= + if (symbol_count < 0)=0A= + return 0;=0A= +=20=09=09=0A= + for (s =3D 0; s < symbol_count; s++)=20=0A= + {=0A= + if (!strcmp (asymbols[s]->name, "_fstack"))=20=0A= + return (asymbols[s]->value + 65536) & ~(0xffffUL);=0A= + }=0A= + return 0;=0A= + }=0A= +=20=0A= + /* Handle lm32 specific options */=0A= +=20=0A= + static SIM_RC=0A= + lm32_option_handler (sd, cpu, opt, arg, is_command)=0A= + SIM_DESC sd;=0A= + sim_cpu *cpu;=0A= + int opt;=0A= + char *arg;=0A= + int is_command;=0A= + {=0A= + return SIM_RC_OK;=0A= + }=0A= +=20=0A= + /* Create an instance of the simulator. */=0A= +=20=0A= + SIM_DESC=0A= + sim_open (kind, callback, abfd, argv)=0A= + SIM_OPEN_KIND kind;=0A= + host_callback *callback;=0A= + struct bfd *abfd;=0A= + char **argv;=0A= + {=0A= + SIM_DESC sd =3D sim_state_alloc (kind, callback);=0A= + char c;=0A= + int i;=0A= + unsigned long base, limit;=0A= +=20=0A= + /* The cpu data is kept in a separately allocated chunk of memory. */= =0A= + if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) !=3D SIM_RC_= OK)=0A= + {=0A= + free_state (sd);=0A= + return 0;=0A= + }=0A= +=20=0A= + if (sim_pre_argv_init (sd, argv[0]) !=3D SIM_RC_OK)=0A= + {=0A= + free_state (sd);=0A= + return 0;=0A= + }=0A= + sim_add_option_table (sd, NULL, lm32_options);=0A= +=20=0A= + /* getopt will print the error message so we just have to exit if this = fails.=0A= + FIXME: Hmmm... in the case of gdb we need getopt to call=0A= + print_filtered. */=0A= + if (sim_parse_args (sd, argv) !=3D SIM_RC_OK)=0A= + {=0A= + free_state (sd);=0A= + return 0;=0A= + }=0A= +=20=0A= + #if 0=0A= + /* Allocate a handler for I/O devices=0A= + if no memory for that range has been allocated by the user.=0A= + All are allocated in one chunk to keep things from being=0A= + unnecessarily complicated. */=0A= + if (sim_core_read_buffer (sd, NULL, read_map, &c, LM32_DEVICE_ADDR, 1) = =3D=3D 0)=0A= + sim_core_attach (sd, NULL,=0A= + 0 /*level*/,=0A= + access_read_write,=0A= + 0 /*space ???*/,=0A= + LM32_DEVICE_ADDR, LM32_DEVICE_LEN /*nr_bytes*/,=0A= + 0 /*modulo*/,=0A= + &lm32_devices,=0A= + NULL /*buffer*/);=0A= + #endif=0A= +=20=0A= + /* check for/establish the reference program image */=0A= + if (sim_analyze_program (sd,=0A= + (STATE_PROG_ARGV (sd) !=3D NULL=0A= + ? *STATE_PROG_ARGV (sd)=0A= + : NULL),=0A= + abfd) !=3D SIM_RC_OK)=0A= + {=0A= + free_state (sd);=0A= + return 0;=0A= + }=0A= +=20=0A= + /* Check to see if memory exists at programs start address */=0A= + if (sim_core_read_buffer (sd, NULL, read_map, &c, STATE_START_ADDR (sd)= , 1) =3D=3D 0)=0A= + {=0A= + if (STATE_PROG_BFD (sd) !=3D NULL) {=0A= + /* It doesn't, so we should try to allocate enough memory to hold= program */=0A= + base =3D find_base (STATE_PROG_BFD (sd));=0A= + limit =3D find_limit (STATE_PROG_BFD (sd));=0A= + if (limit =3D=3D 0)=20=0A= + {=0A= + sim_io_eprintf (sd, "Failed to find symbol _fstack in program= . You must specify memory regions with --memory-region.\n");=0A= + free_state (sd);=0A= + return 0;=0A= + }=0A= + /*sim_io_printf (sd, "Allocating memory at 0x%x size 0x%x\n", bas= e, limit);*/=0A= + sim_do_commandf (sd, "memory region 0x%x,0x%x", base, limit);=0A= + }=0A= + }=0A= +=20=0A= + /* Establish any remaining configuration options. */=0A= + if (sim_config (sd) !=3D SIM_RC_OK)=0A= + {=0A= + free_state (sd);=0A= + return 0;=0A= + }=0A= +=20=0A= + if (sim_post_argv_init (sd) !=3D SIM_RC_OK)=0A= + {=0A= + free_state (sd);=0A= + return 0;=0A= + }=0A= +=20=0A= + /* Open a copy of the cpu descriptor table. */=0A= + {=0A= + CGEN_CPU_DESC cd =3D lm32_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->p= rintable_name,=0A= + CGEN_ENDIAN_BIG);=0A= + for (i =3D 0; i < MAX_NR_PROCESSORS; ++i)=0A= + {=0A= + SIM_CPU *cpu =3D STATE_CPU (sd, i);=0A= + CPU_CPU_DESC (cpu) =3D cd;=0A= + CPU_DISASSEMBLER (cpu) =3D sim_cgen_disassemble_insn;=0A= + }=0A= + lm32_cgen_init_dis (cd);=0A= + }=0A= +=20=0A= + /* Initialize various cgen things not done by common framework.=0A= + Must be done after lm32_cgen_cpu_open. */=0A= + cgen_init (sd);=0A= +=20=0A= + /* Store in a global so things like lm32_dump_regs can be invoked=0A= + from the gdb command line. */=0A= + current_state =3D sd;=0A= +=20=0A= + return sd;=0A= + }=0A= +=20=0A= + void=0A= + sim_close (sd, quitting)=0A= + SIM_DESC sd;=0A= + int quitting;=0A= + {=0A= + lm32_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0)));=0A= + sim_module_uninstall (sd);=0A= + }=0A= + =0C=0A= + SIM_RC=0A= + sim_create_inferior (sd, abfd, argv, envp)=0A= + SIM_DESC sd;=0A= + struct bfd *abfd;=0A= + char **argv;=0A= + char **envp;=0A= + {=0A= + SIM_CPU *current_cpu =3D STATE_CPU (sd, 0);=0A= + SIM_ADDR addr;=0A= +=20=0A= + if (abfd !=3D NULL)=0A= + addr =3D bfd_get_start_address (abfd);=0A= + else=0A= + addr =3D 0;=0A= + sim_pc_set (current_cpu, addr);=0A= +=20=0A= + #if 0=0A= + STATE_ARGV (sd) =3D sim_copy_argv (argv);=0A= + STATE_ENVP (sd) =3D sim_copy_argv (envp);=0A= + #endif=0A= +=20=0A= + return SIM_RC_OK;=0A= + }=0A= +=20=0A= + void=0A= + sim_do_command (sd, cmd)=0A= + SIM_DESC sd;=0A= + char *cmd;=0A= + {=20=0A= + if (sim_args_command (sd, cmd) !=3D SIM_RC_OK)=0A= + sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);=0A= + }=0A= Index: sim/lm32/sim-main.h=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/sim-main.h=0A= diff -N sim/lm32/sim-main.h=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/sim-main.h 20 Dec 2008 22:02:38 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,98 ----=0A= + /* Lattice Mico32 simulator support code=0A= + Written by Jon Beniston =0A= +=20=0A= + This file is part of GDB.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify= =0A= + it under the terms of the GNU General Public License as published by= =0A= + the Free Software Foundation; either version 3 of the License, or=0A= + (at your option) any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program. If not, see . = */=0A= +=20=0A= + /* Main header for the LM32 simulator. */=0A= +=20=0A= + #ifndef SIM_MAIN_H=0A= + #define SIM_MAIN_H=0A= +=20=0A= + #define USING_SIM_BASE_H /* FIXME: quick hack */=0A= +=20=0A= + struct _sim_cpu; /* FIXME: should be in sim-basics.h */=0A= + typedef struct _sim_cpu SIM_CPU;=0A= +=20=0A= + #include "symcat.h"=0A= + #include "sim-basics.h"=0A= + #include "cgen-types.h"=0A= + #include "lm32-desc.h"=0A= + #include "lm32-opc.h"=0A= + #include "arch.h"=0A= +=20=0A= + /* These must be defined before sim-base.h. */=0A= + typedef USI sim_cia;=0A= +=20=0A= + #define CIA_GET(cpu) CPU_PC_GET (cpu)=0A= + #define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))=0A= +=20=0A= + #define SIM_ENGINE_HALT_HOOK(sd, cpu, cia) \=0A= + do { \=0A= + if (cpu) /* null if ctrl-c */ \=0A= + sim_pc_set ((cpu), (cia)); \=0A= + } while (0)=0A= + #define SIM_ENGINE_RESTART_HOOK(sd, cpu, cia) \=0A= + do { \=0A= + sim_pc_set ((cpu), (cia)); \=0A= + } while (0)=0A= +=20=0A= + #include "sim-base.h"=0A= + #include "cgen-sim.h"=0A= + #include "lm32-sim.h"=0A= + #include "opcode/cgen.h"=0A= + =0C=0A= + /* The _sim_cpu struct. */=0A= +=20=0A= + struct _sim_cpu {=0A= + /* sim/common cpu base. */=0A= + sim_cpu_base base;=0A= +=20=0A= + /* Static parts of cgen. */=0A= + CGEN_CPU cgen_cpu;=0A= +=20=0A= + /* CPU specific parts go here.=0A= + Note that in files that don't need to access these pieces WANT_CPU_F= OO=0A= + won't be defined and thus these parts won't appear. This is ok in t= he=0A= + sense that things work. It is a source of bugs though.=0A= + One has to of course be careful to not take the size of this=0A= + struct and no structure members accessed in non-cpu specific files c= an=0A= + go after here. Oh for a better language. */=0A= + #if defined (WANT_CPU_LM32BF)=0A= + LM32BF_CPU_DATA cpu_data;=0A= + #endif=0A= +=20=20=0A= + };=0A= + =0C=0A= + /* The sim_state struct. */=0A= +=20=0A= + struct sim_state {=0A= + sim_cpu *cpu;=0A= + #define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)=0A= +=20=0A= + CGEN_STATE cgen_state;=0A= +=20=0A= + sim_state_base base;=0A= + };=0A= + =0C=0A= + /* Misc. */=0A= +=20=0A= + /* Catch address exceptions. */=0A= + extern SIM_CORE_SIGNAL_FN lm32_core_signal;=0A= + #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \=0A= + lm32_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \=0A= + (TRANSFER), (ERROR))=0A= +=20=0A= + #endif /* SIM_MAIN_H */=0A= Index: sim/lm32/tconfig.in=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/tconfig.in=0A= diff -N sim/lm32/tconfig.in=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/tconfig.in 20 Dec 2008 22:02:38 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,27 ----=0A= + /* Lattice Mico32 simulator configuration.=0A= + Contributed by Jon Beniston =0A= +=20=0A= + This file is part of GDB.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify= =0A= + it under the terms of the GNU General Public License as published by= =0A= + the Free Software Foundation; either version 3 of the License, or=0A= + (at your option) any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program. If not, see . = */=0A= +=20=0A= + #ifndef LM32_TCONFIG_H=0A= + #define LM32_TCONFIG_H=0A= +=20=0A= + /* See sim-hload.c. We properly handle LMA. */=0A= + #define SIM_HANDLES_LMA 1=0A= +=20=0A= + #define WITH_SCACHE_PBB 1=0A= +=20=0A= + #endif /* LM32_TCONFIG_H */=0A= Index: sim/lm32/traps.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/traps.c=0A= diff -N sim/lm32/traps.c=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/traps.c 20 Dec 2008 22:02:38 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,263 ----=0A= + /* Lattice Mico32 exception and system call support.=0A= + Contributed by Jon Beniston =0A= +=20=0A= + This file is part of GDB.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify= =0A= + it under the terms of the GNU General Public License as published by= =0A= + the Free Software Foundation; either version 3 of the License, or=0A= + (at your option) any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program. If not, see . = */=0A= +=20=0A= + #define WANT_CPU lm32bf=0A= + #define WANT_CPU_LM32BF=0A= +=20=0A= + #include "sim-main.h"=0A= + #include "lm32-sim.h"=0A= + #include "targ-vals.h"=0A= +=20=20=20=20=0A= + /* Read memory function for system call interface. */=0A= +=20=0A= + static int=0A= + syscall_read_mem (host_callback *cb, struct cb_syscall *sc,=0A= + unsigned long taddr, char *buf, int bytes)=0A= + {=0A= + SIM_DESC sd =3D (SIM_DESC) sc->p1;=0A= + SIM_CPU *cpu =3D (SIM_CPU *) sc->p2;=0A= +=20=0A= + return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);=0A= + }=0A= +=20=0A= + /* Write memory function for system call interface. */=0A= +=20=0A= + static int=0A= + syscall_write_mem (host_callback *cb, struct cb_syscall *sc,=0A= + unsigned long taddr, const char *buf, int bytes)=0A= + {=0A= + SIM_DESC sd =3D (SIM_DESC) sc->p1;=0A= + SIM_CPU *cpu =3D (SIM_CPU *) sc->p2;=0A= +=20=0A= + return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);= =0A= + }=0A= +=20=0A= + /* Handle invalid instructions. */=20=0A= +=20=20=20=20=0A= + SEM_PC=0A= + sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC pc)=0A= + {=0A= + SIM_DESC sd =3D CPU_STATE (current_cpu);=0A= +=20=0A= + sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);= =0A= +=20=0A= + return pc;=0A= + }=0A= +=20=0A= + /* Handle divide instructions. */=0A= +=20=0A= + USI=0A= + lm32bf_divu_insn (SIM_CPU *current_cpu, IADDR pc, USI r0, USI r1, USI r2)= =0A= + {=0A= + SIM_DESC sd =3D CPU_STATE (current_cpu);=0A= + host_callback *cb =3D STATE_CALLBACK (sd);=0A= +=20=0A= + /* Check for divide by zero */=0A= + if (GET_H_GR (r1) =3D=3D 0)=0A= + {=0A= + if (STATE_ENVIRONMENT (sd) !=3D OPERATING_ENVIRONMENT)=0A= + sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGF= PE);=0A= + else=20=0A= + {=0A= + /* Save PC in exception address register. */=0A= + SET_H_GR (30, pc);=0A= + /* Save and clear interrupt enable */=0A= + SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);=0A= + /* Branch to divide by zero exception handler. */=0A= + return GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DIVIDE_BY_ZERO * 32;= =0A= + }=0A= + }=0A= + else=0A= + {=0A= + SET_H_GR (r2, (USI)GET_H_GR (r0) / (USI)GET_H_GR (r1));=0A= + return pc + 4;=0A= + }=0A= + }=0A= +=20=0A= + USI=0A= + lm32bf_modu_insn (SIM_CPU *current_cpu, IADDR pc, USI r0, USI r1, USI r2)= =0A= + {=0A= + SIM_DESC sd =3D CPU_STATE (current_cpu);=0A= + host_callback *cb =3D STATE_CALLBACK (sd);=0A= +=20=0A= + /* Check for divide by zero */=0A= + if (GET_H_GR (r1) =3D=3D 0)=0A= + {=0A= + if (STATE_ENVIRONMENT (sd) !=3D OPERATING_ENVIRONMENT)=0A= + sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGF= PE);=0A= + else=20=0A= + {=0A= + /* Save PC in exception address register. */=0A= + SET_H_GR (30, pc);=0A= + /* Save and clear interrupt enable */=0A= + SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);=0A= + /* Branch to divide by zero exception handler. */=0A= + return GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DIVIDE_BY_ZERO * 32= ;=0A= + }=0A= + }=0A= + else=0A= + {=0A= + SET_H_GR (r2, (USI)GET_H_GR (r0) % (USI)GET_H_GR (r1));=0A= + return pc + 4;=0A= + }=0A= + }=0A= +=20=0A= + /* Handle break instructions. */=0A= +=20=0A= + USI=0A= + lm32bf_break_insn (SIM_CPU *current_cpu, IADDR pc)=0A= + {=0A= + SIM_DESC sd =3D CPU_STATE (current_cpu);=0A= + host_callback *cb =3D STATE_CALLBACK (sd);=0A= + /* Breakpoint. */=0A= + if (STATE_ENVIRONMENT (sd) !=3D OPERATING_ENVIRONMENT)=0A= + {=20=0A= + sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRA= P);=0A= + return pc;=0A= + }=0A= + else=0A= + {=0A= + /* Save PC in breakpoint address register. */=0A= + SET_H_GR (31, pc);=0A= + /* Save and clear interrupt enable */=0A= + SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 2);=0A= + /* Branch to breakpoint exception handler. */=0A= + return GET_H_CSR (LM32_CSR_DEBA) + LM32_EID_BREAKPOINT * 32;=0A= + }=0A= + }=0A= +=20=0A= + /* Handle scall instructions. */=0A= +=20=0A= + USI=0A= + lm32bf_scall_insn (SIM_CPU *current_cpu, IADDR pc)=0A= + {=0A= + SIM_DESC sd =3D CPU_STATE (current_cpu);=0A= + host_callback *cb =3D STATE_CALLBACK (sd);=0A= +=20=0A= + if ( (STATE_ENVIRONMENT (sd) !=3D OPERATING_ENVIRONMENT)=0A= + || (GET_H_GR (8) =3D=3D TARGET_SYS_exit)=0A= + )=20=0A= + {=0A= + /* Delegate system call to host O/S. */=0A= + CB_SYSCALL s;=0A= + CB_SYSCALL_INIT (&s);=0A= + s.p1 =3D (PTR)sd;=0A= + s.p2 =3D (PTR)current_cpu;=0A= + s.read_mem =3D syscall_read_mem;=0A= + s.write_mem =3D syscall_write_mem;=0A= + /* Extract parameters. */=0A= + s.func =3D GET_H_GR (8);=0A= + s.arg1 =3D GET_H_GR (1);=0A= + s.arg2 =3D GET_H_GR (2);=0A= + s.arg3 =3D GET_H_GR (3);=0A= + /* Halt the simulator if the requested system call is _exit. */=0A= + if (s.func =3D=3D TARGET_SYS_exit)=20=0A= + sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);= =0A= + /* Perform the system call. */=0A= + cb_syscall (cb, &s);=0A= + /* Store the return value in the CPU's registers. */=0A= + SET_H_GR (1, s.result);=0A= + SET_H_GR (2, s.result2);=0A= + SET_H_GR (3, s.errcode);=0A= + /* Skip over scall instruction. */=0A= + return pc + 4;=20=20=20=20=20=20=0A= + }=0A= + else=20=0A= + {=0A= + /* Save PC in exception address register. */=0A= + SET_H_GR (30, pc);=0A= + /* Save and clear interrupt enable */=0A= + SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);=0A= + /* Branch to system call exception handler. */=0A= + return GET_H_CSR (LM32_CSR_EBA) + LM32_EID_SYSTEM_CALL * 32;=0A= + }=0A= + }=0A= +=20=0A= + /* Handle b instructions. */=0A= +=20=0A= + USI=0A= + lm32bf_b_insn (SIM_CPU *current_cpu, USI r0, USI f_r0)=0A= + {=0A= + SIM_DESC sd =3D CPU_STATE (current_cpu);=0A= + host_callback *cb =3D STATE_CALLBACK (sd);=0A= +=20=20=20=0A= + /* Restore interrupt enable */=0A= + if (f_r0 =3D=3D 30)=20=0A= + SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 2) >> 1);=0A= + else if (f_r0 =3D=3D 31)=20=0A= + SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 4) >> 2);=0A= + return r0;=20=20=0A= + }=0A= +=20=0A= + /* Handle wcsr instructions. */=0A= +=20=0A= + void=0A= + lm32bf_wcsr_insn (SIM_CPU *current_cpu, USI f_csr, USI r1)=0A= + {=0A= + SIM_DESC sd =3D CPU_STATE (current_cpu);=0A= + host_callback *cb =3D STATE_CALLBACK (sd);=0A= +=20=0A= + /* Writing a 1 to IP CSR clears a bit, writing 0 has no effect */=0A= + if (f_csr =3D=3D LM32_CSR_IP)=20=0A= + SET_H_CSR (f_csr, GET_H_CSR (f_csr) & ~r1);=0A= + else=0A= + SET_H_CSR (f_csr, r1);=0A= + }=0A= +=20=0A= + /* Handle signals. */=0A= +=20=0A= + void=0A= + lm32_core_signal (SIM_DESC sd,=0A= + sim_cpu *cpu,=0A= + sim_cia cia,=0A= + unsigned map,=0A= + int nr_bytes,=0A= + address_word addr,=0A= + transfer_type transfer,=0A= + sim_core_signals sig)=0A= + {=0A= + const char *copy =3D (transfer =3D=3D read_transfer ? "read" : "write")= ;=0A= + address_word ip =3D CIA_ADDR (cia);=0A= + SIM_CPU *current_cpu =3D cpu;=0A= +=20=20=20=0A= + switch (sig)=0A= + {=0A= + case sim_core_unmapped_signal:=0A= + sim_io_eprintf (sd, "core: %d byte %s to unmapped address 0x%lx at = 0x%lx\n",=0A= + nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);=0A= + SET_H_GR (30, ip);=0A= + /* Save and clear interrupt enable */=0A= + SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);=0A= + CIA_SET (cpu, GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DATA_BUS_ERROR *= 32);=0A= + sim_engine_halt (sd, cpu, NULL, LM32_EID_DATA_BUS_ERROR * 32, sim_s= topped, SIM_SIGSEGV);=0A= + break;=0A= + case sim_core_unaligned_signal:=0A= + sim_io_eprintf (sd, "core: %d byte misaligned %s to address 0x%lx a= t 0x%lx\n",=0A= + nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);=0A= + SET_H_GR (30, ip);=0A= + /* Save and clear interrupt enable */=0A= + SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);=0A= + CIA_SET (cpu, GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DATA_BUS_ERROR *= 32);=0A= + sim_engine_halt (sd, cpu, NULL, LM32_EID_DATA_BUS_ERROR * 32, sim_s= topped, SIM_SIGBUS);=0A= + break;=0A= + default:=0A= + sim_engine_abort (sd, cpu, cia,=0A= + "sim_core_signal - internal error - bad switch");=0A= + }=0A= + }=0A= +=20=0A= Index: sim/lm32/user.c=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: sim/lm32/user.c=0A= diff -N sim/lm32/user.c=0A= *** /dev/null 1 Jan 1970 00:00:00 -0000=0A= --- sim/lm32/user.c 20 Dec 2008 22:02:38 -0000=0A= ***************=0A= *** 0 ****=0A= --- 1,28 ----=0A= + /* Semantics for user defined instructions on the Lattice Mico32.=0A= + Contributed by Jon Beniston =0A= +=20=0A= + This file is part of GDB.=0A= +=20=0A= + This program is free software; you can redistribute it and/or modify= =0A= + it under the terms of the GNU General Public License as published by= =0A= + the Free Software Foundation; either version 3 of the License, or=0A= + (at your option) any later version.=0A= +=20=0A= + This program is distributed in the hope that it will be useful,=0A= + but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= + GNU General Public License for more details.=0A= +=20=0A= + You should have received a copy of the GNU General Public License=0A= + along with this program. If not, see . = */=0A= +=20=0A= + #include "sim-main.h"=0A= +=20=20=20=20=0A= + /* Handle user defined instructions */=0A= +=20=0A= + UINT=0A= + lm32bf_user_insn (SIM_CPU *current_cpu, INT r0, INT r1, UINT imm)=0A= + {=0A= + /* FIXME: Should probably call code in a user supplied library. */=20= =20=20=0A= + return 0;=0A= + }=0A= ------=_NextPart_000_0009_01C9642D.7C5A5310--