From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 11465 invoked by alias); 31 Aug 2019 08:13:05 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 11454 invoked by uid 89); 31 Aug 2019 08:13:04 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-10.1 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy=H*F:D*eu, UD:eu, D*eu, H*r:sk:server2 X-HELO: server28.superhosting.bg Received: from server28.superhosting.bg (HELO server28.superhosting.bg) (217.174.156.11) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 31 Aug 2019 08:13:00 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=dinux.eu; s=default; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=yBrV5V4GDIHJj0srQVstoetIB8CHgj1oewHt9FJIt6w=; b=PWtuFJiKbEQ9jP8IA4f5b8kQiw HVsGow3PnP/Vmu8GGUuad8g048Aqh/1LlA0hwb6Sxo+CNXTsvZsBX14pmluNRl+hn98udW0ipKUST l9nf9NB5RWyooXkeDFVDdrYQDGMdPxXqLmzaXNy98LoOfm1LA6LyAyea0W3NZtFm1iNmPNLQJ0LbB QnV5kNjFlfhDNMc9x6XgeYGmrba8nhM7OkcNq/SnhsOJ4deKFIRGlVBFaaazD/jsZCosKl2iwqsAs +R+l/CK4ZdfCS7NT+M8C7WKmQIIc6WksXyt1Uj/AZh9fK+rlP5W9gXwXW4BKnrW6RqWFrbcxmumxl Mr5SN2kQ==; Received: from [95.87.234.74] (port=50482 helo=tpdeb.localnet) by server28.superhosting.bg with esmtpsa (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384:256) (Exim 4.92) (envelope-from ) id 1i3yVA-0007IB-Ck; Sat, 31 Aug 2019 11:12:57 +0300 From: Dimitar Dimitrov To: Andrew Burgess Cc: gdb-patches@sourceware.org Subject: Re: [PATCH v5 1/2] PRU Simulator port Date: Sat, 31 Aug 2019 08:13:00 -0000 Message-ID: <23752374.gxGJgHr7so@tpdeb> In-Reply-To: <20190828121134.GR6076@embecosm.com> References: <20190826040817.8711-1-dimitar@dinux.eu> <20190828121134.GR6076@embecosm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-OutGoing-Spam-Status: No, score=-1.0 X-IsSubscribed: yes X-SW-Source: 2019-08/txt/msg00667.txt.bz2 On Wed, 28 Aug 2019, 15:11:34 EEST Andrew Burgess wrote: > * Dimitar Dimitrov [2019-08-26 07:08:16 +0300]: > > I'd like to contribute a sim port for the TI PRU I/O processor. This > > is the fifth version of the patch series. > > > > The GCC and binutils ports have already been merged. I've sent > > patches for newlib. > > > > Changes since patch series v4: > > - Rebased to latest top-of-tree. > > - Added XCHG instruction support. > > > > v1: https://sourceware.org/ml/gdb-patches/2016-12/msg00143.html > > v2: https://sourceware.org/ml/gdb-patches/2017-02/msg00397.html > > v3: https://sourceware.org/ml/gdb-patches/2017-02/msg00516.html > > v4: https://sourceware.org/ml/gdb-patches/2018-06/msg00484.html > > Thanks for sticking with the patch over the years! I built and tested > this, and all the tests passed. I have a few (hopefully) minor nits, > but this is all looking pretty good. Thank you for the review. I'll resubmit v6 to address all your comments. > ... > > > * configure: Regenerate. > > This file appears to be missing from the patch. Unfortunaly the autogenerated configure file is rather large. I'll send it as a separate patch. > ... > > + the performance of the simulator. Simulation speed is deemed more > > + important. */ > > + > > +/* Please keep the same order as the GP registers. */ > > It isn't clear to me where the order in "... same order as the GP > registers" comes from. Is this order defined in the ISA? Defined in > some other file in GDB or the simulator? Could you expand on this > comment maybe? This enum order is purely easthetical and has no functional impact. I hope the following C comment would sched some light. If it causes too much confusion, I can altogether remove the comment. The relevant ISA documentation can be found on page 31, section 5.2.3.2 in https://elinux.org/images/d/da/Am335xPruReferenceGuide.pdf . +/* For clarity, please keep the same relative order in this enum as in the + corresponding group of GP registers. + + In PRU ISA, Multiplier-Accumulator-Unit's registers are like "shadows" of + the GP registers. MAC registers are implicitly addressed when executing + the XIN/XOUT instructions to access them. Transfer to/from a MAC register + can happen only from/to its corresponding GP peer register. */ + +enum pru_macreg_id { + /* MAC register CPU GP register Description. */ + PRU_MACREG_MODE, /* r25 */ /* Mode (MUL/MAC). */ + PRU_MACREG_PROD_L, /* r26 */ /* Lower 32 bits of product. */ + PRU_MACREG_PROD_H, /* r27 */ /* Higher 32 bits of product. */ + PRU_MACREG_OP_0, /* r28 */ /* First operand. */ + PRU_MACREG_OP_1, /* r29 */ /* Second operand. */ + PRU_MACREG_ACC_L, /* N/A */ /* Accumulator (not exposed) */ + PRU_MACREG_ACC_H, /* N/A */ /* Higher 32 bits of MAC + accumulator. */ + PRU_MAC_NREGS +}; > > > +enum pru_macreg_id { > > + PRU_MACREG_MODE, /* r25 */ > > + PRU_MACREG_PROD_L, /* r26 */ > > + PRU_MACREG_PROD_H, /* r27 */ > > + PRU_MACREG_OP_0, /* r28 */ > > + PRU_MACREG_OP_1, /* r29 */ > > + PRU_MACREG_ACC_L, /* N/A */ > > + PRU_MACREG_ACC_H, /* N/A */ > > + PRU_MAC_NREGS > > +}; > > + Regards, Dimitar