From: Nick Clifton <nickc@redhat.com>
To: Jim Wilson <jim.wilson@linaro.org>, gdb-patches@sourceware.org
Subject: Re: [PATCH] aarch64 sim addv bug fix
Date: Mon, 16 Jan 2017 11:10:00 -0000 [thread overview]
Message-ID: <22c885db-c063-1196-3d69-86363f4df38e@redhat.com> (raw)
In-Reply-To: <CABXYE2W_Mn=K=4jsYXa14UimQedL-JrJD9-tJTdijrfRfOKyqw@mail.gmail.com>
Hi Jim,
> The addv instruction is storing results to general registers instead
> of vector registers. The reserved instruction check is wrong, It
> should be not full in case 2, and unconditionally in case 3.
>
> The testcase fails without the patch, and works with the patch. The
> patch reduces gcc C testsuite failures from 2227 to 2174 (-57).
Approved - please apply.
Cheers
Nick
prev parent reply other threads:[~2017-01-16 11:10 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-14 19:16 Jim Wilson
2017-01-16 11:10 ` Nick Clifton [this message]
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