From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 29568 invoked by alias); 9 Oct 2018 17:39:19 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 29165 invoked by uid 89); 9 Oct 2018 17:39:18 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 09 Oct 2018 17:39:17 +0000 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7377C3082128; Tue, 9 Oct 2018 17:39:16 +0000 (UTC) Received: from [127.0.0.1] (ovpn04.gateway.prod.ext.ams2.redhat.com [10.39.146.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 256F17555A; Tue, 9 Oct 2018 17:39:14 +0000 (UTC) Subject: Re: [PATCH] RISC-V: enable have_nonsteppable_watchpoint by default To: Paul Koning , Craig Blackmore References: <20180917103409.GJ5952@embecosm.com> <77978648-c391-0011-6c03-c7fd38429914@embecosm.com> <20181003223703.GA22933@adacore.com> <20181008095839.GC5952@embecosm.com> <4c4c1369-0f5c-549a-ed82-51563c5e6dd6@redhat.com> <20181008142533.GA2993@adacore.com> <5019D845-3AEB-4287-A8BD-D9F96F5755B7@comcast.net> <20181008145132.GB2993@adacore.com> <5bd138ad-4d1d-254c-9d35-1873b2d8f5f4@embecosm.com> Cc: Joel Brobecker , Andrew Burgess , gdb-patches@sourceware.org From: Pedro Alves Message-ID: <21b55e3b-7d01-8c9c-54e0-dfbffc7f654c@redhat.com> Date: Tue, 09 Oct 2018 17:39:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-SW-Source: 2018-10/txt/msg00224.txt.bz2 -- Thanks, Pedro Alves On 10/09/2018 06:29 PM, Paul Koning wrote: > > >> On Oct 9, 2018, at 1:20 PM, Craig Blackmore wrote: >> >> >> >> On 08/10/18 15:51, Joel Brobecker wrote: >>>>> I think MIPS is one. The documentation is not entirely clear but >>>>> that's what I remember from using it. >>>> x86 is another. But my question is -- do we know of any RISC-V >>>> implementation that triggers after the write, given that the spec >>>> says it should trigger before the write. >> I don't know of any RISC-V implementations that trigger after the write. >> The debug spec has 'suggested breakpoint timings' but the triggers are >> allowed to fire at whatever point is most convenient for the implementation. > > I missed that the question was specific to RISC-V. > > If the spec says that timing is up to the implementation, that seems to mean GDB can't rely on the break occurring before the write -- the fact that current implementations do so isn't sufficient if later implementation are allowed to differ. > > I assume GDB cares which it is, which suggests that the implementation has to tell GDB which flavor of write watchpoint it has. Yes, which is what I had suggested earlier in the thread. But the thing is, no one knows about any implementation that doesn't trap before the write. Does the "point is most convenient" include a few instructions/cycles after the write (more than one insn?). Because, there are archs like that (some ARM variants, IIRC). If so, before/after will not be sufficient. Thus, I still think we should go with the simple approach until we learn about some real implementation that needs something else. Thanks, Pedro Alves