From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id uIp0Oa01K2N3zj0AWB0awg (envelope-from ) for ; Wed, 21 Sep 2022 12:02:53 -0400 Received: by simark.ca (Postfix, from userid 112) id E90901E112; Wed, 21 Sep 2022 12:02:53 -0400 (EDT) Authentication-Results: simark.ca; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=VnJ1O9kF; dkim-atps=neutral X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RDNS_DYNAMIC,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 9ABCD1E0D5 for ; Wed, 21 Sep 2022 12:02:53 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 19975385841A for ; Wed, 21 Sep 2022 16:02:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 19975385841A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1663776173; bh=CfCqybUuM8YSTgaeaWHQLycOlXm0ofoNANAfMXmgdro=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=VnJ1O9kF9tjcGoIIFXgGftmCz0IaurcnnHFUoKdf2wYnBjFya36cKzrl+z6RzmLGj m2tQOnLK36EBalQc/UMaVki9AEddCurAPLygGahE4UeBCeLWJY+bb/a9BIj9ak0iUY lDxD4VTuSTDWV7d9pBCIUiya0KmkbqxpVzK6yBEY= Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 19FA53858406 for ; Wed, 21 Sep 2022 16:01:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 19FA53858406 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 7A8AF30008A; Wed, 21 Sep 2022 16:01:48 +0000 (UTC) To: Tsukasa OI Subject: [PING^2 PATCH 1/1] sim/riscv: Fix RISC-V multiply instructions on the simulator Date: Wed, 21 Sep 2022 16:01:32 +0000 Message-Id: <2123172d1011ad4b770f37a61b64ec49a85e3145.1663776070.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Tsukasa OI via Gdb-patches Reply-To: Tsukasa OI Cc: gdb-patches@sourceware.org Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" Because of recent 'Zmmul' support, the simulator is broken. This is caused by instruction classification changes: [Before] - INSN_CLASS_M : multiply / divide [After Zmmul] - INSN_CLASS_M : divide - INSN_CLASS_ZMMUL : multiply The simulator checks the instruction class to execute an instruction: - INSN_CLASS_I : 'I' - INSN_CLASS_M : 'M' (multiply / divide) - INSN_CLASS_A : 'A' 'Zmmul' moved multiply instructions to INSN_CLASS_ZMMUL and that instruction class is not handled by the simulator. This commit handles INSN_CLASS_ZMMUL for all 'M' instructions and adds a testcase to test all RV32M instructions run without any faults. sim/ChangeLog: * riscv/sim-main.c (execute_one): Add INSN_CLASS_ZMMUL to run multiply instructions correctly. * testsuite/riscv/m-ext.s: New test. --- sim/riscv/sim-main.c | 1 + sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 sim/testsuite/riscv/m-ext.s diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 30d2f1e1c9a..0156f791d4b 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) case INSN_CLASS_I: return execute_i (cpu, iw, op); case INSN_CLASS_M: + case INSN_CLASS_ZMMUL: return execute_m (cpu, iw, op); default: TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class); diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s new file mode 100644 index 00000000000..b85397a32a0 --- /dev/null +++ b/sim/testsuite/riscv/m-ext.s @@ -0,0 +1,18 @@ +# check that the RV32M instructions run without any fault. +# mach: riscv + +.include "testutils.inc" + + start + + .option arch, +m + mul x0, x1, x2 + mulh x0, x1, x2 + mulhu x0, x1, x2 + mulhsu x0, x1, x2 + div x0, x1, x2 + divu x0, x1, x2 + rem x0, x1, x2 + remu x0, x1, x2 + + pass -- 2.34.1