From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 5766 invoked by alias); 24 May 2011 07:19:55 -0000 Received: (qmail 5704 invoked by uid 22791); 24 May 2011 07:19:40 -0000 X-SWARE-Spam-Status: No, hits=1.7 required=5.0 tests=AWL,BAYES_50,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,RFC_ABUSE_POST,TW_EG,TW_NR,TW_SB,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from nm11-vm0.bullet.mail.sp2.yahoo.com (HELO nm11-vm0.bullet.mail.sp2.yahoo.com) (98.139.91.240) by sourceware.org (qpsmtpd/0.43rc1) with SMTP; Tue, 24 May 2011 07:19:17 +0000 Received: from [98.139.91.62] by nm11.bullet.mail.sp2.yahoo.com with NNFMP; 24 May 2011 07:19:16 -0000 Received: from [98.139.91.59] by tm2.bullet.mail.sp2.yahoo.com with NNFMP; 24 May 2011 07:19:16 -0000 Received: from [127.0.0.1] by omp1059.mail.sp2.yahoo.com with NNFMP; 24 May 2011 07:19:16 -0000 Received: (qmail 9808 invoked by uid 60001); 24 May 2011 07:19:16 -0000 Message-ID: <205475.9678.qm@web112514.mail.gq1.yahoo.com> Received: from [115.99.18.98] by web112514.mail.gq1.yahoo.com via HTTP; Tue, 24 May 2011 00:19:16 PDT Date: Tue, 24 May 2011 07:19:00 -0000 From: paawan oza Subject: Re: [PATCH] arm reversible : To: =?iso-8859-1?Q?Petr_Hluz=EDn?= Cc: gdb-patches@sourceware.org MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2011-05/txt/msg00549.txt.bz2 Hi, please find the updated patch below. except one, all from Petr are implemen= ted=20 in this. execuse me for typo if any,do not hesitate to point it out. PATCH STARTS --------------------------------- diff -urN arm_orig/arm-linux-tdep.c arm_new/arm-linux-tdep.c --- arm_orig/arm-linux-tdep.c 2011-03-03 09:21:13.000000000 +0530 +++ arm_new/arm-linux-tdep.c 2011-05-07 14:20:31.000000000 +0530 @@ -998,6 +998,9 @@ set_gdbarch_fetch_tls_load_module_address (gdbarch, svr4_fetch_objfile_link_map); =20 + /* Enable process record. */ + set_gdbarch_process_record (gdbarch, arm_process_record); + tramp_frame_prepend_unwinder (gdbarch, &arm_linux_sigreturn_tramp_frame); tramp_frame_prepend_unwinder (gdbarch, @@ -1025,6 +1028,8 @@ =20 =20 tdep->syscall_next_pc =3D arm_linux_syscall_next_pc; + + tdep->arm_swi_record =3D NULL; } =20 /* Provide a prototype to silence -Wmissing-prototypes. */ diff -urN arm_orig/arm-tdep.c arm_new/arm-tdep.c --- arm_orig/arm-tdep.c 2011-03-03 09:21:13.000000000 +0530 +++ arm_new/arm-tdep.c 2011-05-24 12:43:20.000000000 +0530 @@ -54,6 +54,8 @@ #include "gdb_assert.h" #include "vec.h" =20 +#include "record.h" + #include "features/arm-with-m.c" =20 static int arm_debug; @@ -7929,3 +7931,1736 @@ NULL, /* FIXME: i18n: "ARM debugging is %s. */ &setdebuglist, &showdebuglist); } + + + +/* ARM-reversible process record data structures. */ + +#define ARM_INSN_SIZE_BYTES 4=20=20=20=20 +#define THUMB_INSN_SIZE_BYTES 2 +#define THUMB2_INSN_SIZE_BYTES 4 +=20=20=20=20 +#define GET_REG_VAL(REGCACHE,NO,VAL) \ + regcache_raw_read_unsigned (REGCACHE, NO, VAL); + +#define GET_REG_VAL_SIGNED(REGCACHE,NO,VAL) \ + regcache_raw_read_unsigned (REGCACHE, NO, VAL); + +#define INSN_S_L_BIT_NUM 20 + +#define REG_ALLOC(REGS,LENGTH,RECORD_BUF) \ +do \ + { \ + if (LENGTH) \ + { \ + REGS =3D (uint32_t*) xmalloc (sizeof(uint32_t) * (LENGTH)); \ + while(LENGTH) \ + { \ + REGS[LENGTH - 1] =3D RECORD_BUF[LENGTH - 1]; \ + LENGTH--; \ + } \ + } \ + } \ +while (0) + +#define MEM_ALLOC(MEMS,LENGTH,RECORD_BUF) \ +do \ + { \ + if (LENGTH) \ + { \ + MEMS =3D (struct arm_mem_r *)xmalloc \ + (sizeof(struct arm_mem_r) * (LENGTH)); \ + while(LENGTH) \ + { \ + MEMS[LENGTH - 1].addr =3D RECORD_BUF[(LENGTH * 2) - 1]; \ + MEMS[LENGTH - 1].len =3D RECORD_BUF[(LENGTH * 2) - 2]; \ + LENGTH--; \ + } \ + } \ + } \ +while (0) + + +/* ARM memory record structure. */ +struct arm_mem_r +{ + uint32_t len; /* record length. */ + CORE_ADDR addr; /* memory address. */ +}; + +/* ARM instruction record.=20=20 +contains opcode of current insn and execution state (before entry to=20 +decode_insn() ),=20 +contains list of to-be-modified registers and memory blocks (on return fro= m=20 +decode_insn() ). */ +typedef struct insn_decode_record_t +{ + struct gdbarch *gdbarch; + struct regcache *regcache; + CORE_ADDR this_addr; /* address of the insn being decoded. */ + uint32_t arm_insn; /* should accommodate thumb. */ + uint32_t cond; /* condition code. */ + uint32_t opcode; /* insn opcode. */ + uint32_t decode; /* insn decode bits. */ + uint32_t mem_rec_count; /* no of mem recors */ + uint32_t reg_rec_count; /* no of reg records */ + uint32_t *arm_regs; /* registers to be saved for this record. = */ + struct arm_mem_r *arm_mems; /* memory to be saved for this record. */ +} insn_decode_record; + + +/* checks ARM SBZ and SBO mendatory fields. */ + +static int +sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo) +{ + uint32_t ones =3D bits (insn, bit_num - 1, (bit_num -1) + (len - 1)); +=20=20=20=20=20=20 + if (!len) + return 1; + + if(!sbo) + ones =3D ~ones; + + while (ones) + { + if (!(ones & sbo)) + { + return 0; + } + ones =3D ones >> 1; + } + return 1; +} + +/* handling ARM extension space insns. */ + +static int=20 +handle_extension_space (insn_decode_record *arm_insn_r) +{=20=20 + uint32_t ret =3D 0; + uint32_t opcode1 =3D 0, opcode2 =3D 0; + + opcode1 =3D bits (arm_insn_r->arm_insn, 25, 27); + if ((3 =3D=3D opcode1) && (bit (arm_insn_r->arm_insn, 4))) + { + ret =3D -1; + /* undefined instruction on ARM V5; need to handle if later versions + define it. */ + } +=20=20 + opcode2 =3D bits (arm_insn_r->arm_insn, 4, 7); +=20=20 + if ((!opcode1) && (9 =3D=3D opcode2)) + { + ret =3D -1; + /* handle arithmetic insn extension space. */ + } + + opcode1 =3D bits (arm_insn_r->arm_insn, 26, 27); + opcode2 =3D bits (arm_insn_r->arm_insn, 23, 24); + + if ((!opcode1) && (2 =3D=3D opcode2) && (!bit (arm_insn_r->arm_insn, 20)= )) + { + ret =3D -1; + /* handle control insn extension space. */ + } + + opcode1 =3D bits (arm_insn_r->arm_insn, 25, 27); + if ((!opcode1) && (bit (arm_insn_r->arm_insn, 7)) \ + && (bit(arm_insn_r->arm_insn, 4))) + { + ret =3D -1; + /* handle load/store insn extension space. */ + } + + opcode1 =3D bits (arm_insn_r->arm_insn, 23, 27); + if ((24 =3D=3D opcode1) && (bit (arm_insn_r->arm_insn, 21))) + { + ret =3D -1; + /* handle coprocessor insn extension space. */ + } + + /* to be done for ARMv5 and later; as of now we return -1. */ + if (-1 =3D=3D ret) + printf_unfiltered (_("Process record does not support instruction 0x%0= x " + "at address %s.\n"), + arm_insn_r->arm_insn, + paddress (arm_insn_r->gdbarch, arm_insn_r->this_add= r)); + return ret; +} + +/* handling opcode 000 insns. */ + +static int=20 +arm_handle_data_proc_misc_ld_str_insn (insn_decode_record *arm_insn_r) +{ + struct regcache *reg_cache =3D arm_insn_r->regcache; + uint32_t record_buf[8], record_buf_mem[8]; + + struct + { + ULONGEST unsigned_regval; + } u_buf[2]; + + + uint32_t reg_src1 =3D 0, reg_src2 =3D 0, reg_dest =3D 0; + uint32_t immed_high =3D 0, immed_low =3D 0,offset_8 =3D 0, tgt_mem_addr = =3D 0; + uint32_t opcode1 =3D 0; + + memset(&u_buf, 0, sizeof(u_buf)); + + arm_insn_r->opcode =3D bits (arm_insn_r->arm_insn, 21, 24); + arm_insn_r->decode =3D bits (arm_insn_r->arm_insn, 4, 7); + opcode1 =3D bits (arm_insn_r->arm_insn, 20, 24); + + /* data processing insn /multiply insn. */=20=20=20=20=20 + if ((9 =3D=3D arm_insn_r->decode)=20 + && (((4 <=3D arm_insn_r->opcode) && (7 >=3D arm_insn_r->opcode)) + || ((0 =3D=3D arm_insn_r->opcode) || (1 =3D=3D arm_insn_r->opcode)))) + { + /* handle multiply instructions. */ + /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */ + if ((0 =3D=3D arm_insn_r->opcode) || (1 =3D=3D arm_insn_r->opcode)) + { + /* handle MLA and MUL. */ + record_buf[0] =3D bits (arm_insn_r->arm_insn, 16, 19); + record_buf[1] =3D ARM_PS_REGNUM; + arm_insn_r->reg_rec_count =3D 2;=20=20=20=20=20=20=20=20=20=20= =20=20 + } + else if ((4 <=3D arm_insn_r->opcode) && (7 >=3D arm_insn_r->opcode= )) + { + /* handle SMLAL, SMULL, UMLAL, UMULL. */ + record_buf[0] =3D bits (arm_insn_r->arm_insn, 16, 19); + record_buf[1] =3D bits (arm_insn_r->arm_insn, 12, 15); + record_buf[2] =3D ARM_PS_REGNUM;=20=20 + arm_insn_r->reg_rec_count =3D 3; + }=20=20=20=20=20=20=20=20 + } + else if ((bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))=20 + && ((11 =3D=3D arm_insn_r->decode) || (13 =3D=3D arm_insn_r->decod= e))) + { + /* handle misc load insns, as 20th bit (L =3D 1). */ + /* LDR insn has a capability to do branching, if + MOV LR, PC is preccedded by LDR insn having Rn as R15=20 + in that case, it emulates branch and link insn, and henc= e we=20 + need to save CSPR and PC as well. I am not sure this is = right=20 + place as opcode =3D 010 LDR insn make this happen, if R1= 5 was=20 + used. */ + reg_dest =3D bits (arm_insn_r->arm_insn, 12, 15); + if (15 !=3D reg_dest) + { + record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15); + arm_insn_r->reg_rec_count =3D 1; + } + else + { + record_buf[0] =3D reg_dest; + record_buf[1] =3D ARM_PS_REGNUM;=20 + arm_insn_r->reg_rec_count =3D 2; + } + } + else if (((9 =3D=3D arm_insn_r->opcode) || (11 =3D=3D arm_insn_r->opcode= )) + && (sbo_sbz (arm_insn_r->arm_insn, 5, 12, 0)) + && (sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)) + && (2 =3D=3D bits (arm_insn_r->arm_insn, 20, 21))) + { + /* handle MSR insn. */ + if (9 =3D=3D arm_insn_r->opcode) + { + /* CSPR is going to be changed. */ + record_buf[0] =3D ARM_PS_REGNUM; + arm_insn_r->reg_rec_count =3D 1; + }=20=20=20=20 + else + { + /* SPSR is going to be changed. */ + /* how to read SPSR value ? */ + printf_unfiltered (_("Process record does not support instructio= n " + "0x%0x at address %s.\n"), + arm_insn_r->arm_insn, + paddress (arm_insn_r->gdbarch,=20 arm_insn_r->this_addr)); + return -1; + } + }=20=20=20 + else if ((9 =3D=3D arm_insn_r->decode)=20 + && ((8 =3D=3D arm_insn_r->opcode) || (10 =3D=3D arm_insn_r->opc= ode)) + && (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))) + { + /* Handling SWP, SWPB. */ + /* these insns, changes register and memory as well. */ + /* SWP or SWPB insn. */ + /* get memory address given by Rn. */ + reg_src1 =3D bits (arm_insn_r->arm_insn, 16, 19);=20 + GET_REG_VAL (reg_cache, reg_src1, &u_buf[0].unsigned_regval); + /* SWP insn ?, swaps word. */ + if (8 =3D=3D arm_insn_r->opcode) + { + record_buf_mem[0] =3D 4; + } + else + {=20=20=20 + /* SWPB insn, swaps only byte. */ + record_buf_mem[0] =3D 1; + } + record_buf_mem[1] =3D u_buf[0].unsigned_regval; + arm_insn_r->mem_rec_count =3D 1; + record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15);=20=20=20=20 + arm_insn_r->reg_rec_count =3D 1; + } + else if ((3 =3D=3D arm_insn_r->decode) && (0x12 =3D=3D opcode1) + && (sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))) + { + /* handle BLX, branch and link/exchange. */ + if (9 =3D=3D arm_insn_r->opcode) + { + /* branch is chosen by setting T bit of CSPR, bitp[0] of Rm,=20 + and R14 stores the return address. */ + record_buf[0] =3D ARM_PS_REGNUM; + record_buf[1] =3D ARM_LR_REGNUM; + arm_insn_r->reg_rec_count =3D 2; + } + } + else if ((7 =3D=3D arm_insn_r->decode) && (0x12 =3D=3D opcode1)) + { + /* handle enhanced software breakpoint insn, BKPT */ + /* CPSR is changed to be executed in ARM state, disabling normal=20 + interrupts, entering abort mode. */ + /* accorindly to high vector configuration PC is set accordingly */ + /* what if user hit breakpoint and type reverse, in=20 + that case, we need to go back with previous CPSR and=20 + Program Counter. */ + record_buf[0] =3D ARM_PS_REGNUM; + record_buf[1] =3D ARM_LR_REGNUM; + arm_insn_r->reg_rec_count =3D 2; +=20=20=20=20=20=20 + /* save SPSR also; how? */ + printf_unfiltered (_("Process record does not support instruction " + "0x%0x at address %s.\n"), + arm_insn_r->arm_insn, + paddress (arm_insn_r->gdbarch, arm_insn_r->this_ad= dr)); + return -1; + }=20=20 + else if ((11 =3D=3D arm_insn_r->decode) + && (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))) + { + /* handle enhanced store insns and DSP insns (e.g. LDRD)=20 + let us begin according to addressing modes for store insns=20 + STRH insn, addresing modes are taken following. */ + if ((14 =3D=3D arm_insn_r->opcode) || (10 =3D=3D arm_insn_r->opcode)) + { + /* 1) handle misc store, immediate offset. */ + immed_low =3D bits (arm_insn_r->arm_insn, 0, 3); + immed_high =3D bits (arm_insn_r->arm_insn, 8, 11); + reg_src1 =3D bits (arm_insn_r->arm_insn, 16, 19); + GET_REG_VAL (reg_cache, reg_src1,=20 &u_buf[0].unsigned_regval);=20=20=20=20=20=20=20=20=20=20=20=20 + if (15 =3D=3D reg_src1) + { + /* if R15 was used as Rn, hence current PC+8. */ + u_buf[0].unsigned_regval =3D u_buf[0].unsigned_regval + 8; + }=20=20=20=20=20=20=20=20=20=20=20=20 + offset_8 =3D (immed_high << 4) | immed_low; + /* calculate target store address. */ + if (14 =3D=3D arm_insn_r->opcode) + { + tgt_mem_addr =3D u_buf[0].unsigned_regval + offset_8; + } + else + { + tgt_mem_addr =3D u_buf[0].unsigned_regval - offset_8; + } + record_buf_mem[0] =3D 2; + record_buf_mem[1] =3D tgt_mem_addr; + arm_insn_r->mem_rec_count =3D 1; + } + else if ((12 =3D=3D arm_insn_r->opcode) || (8 =3D=3D arm_insn_r->opcod= e)) + { + /* 2) store, register offset. */ + /* get Rm. */ + reg_src1 =3D bits (arm_insn_r->arm_insn, 0, 3);=20=20 + /* get Rn. */ + reg_src2 =3D bits (arm_insn_r->arm_insn, 16, 19); + GET_REG_VAL (reg_cache, reg_src1, &u_buf[0].unsigned_regval); + GET_REG_VAL (reg_cache, reg_src2,=20 &u_buf[1].unsigned_regval);=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20 + if (15 =3D=3D reg_src2) + { + /* if R15 was used as Rn, hence current PC+8. */ + u_buf[0].unsigned_regval =3D u_buf[0].unsigned_regval + 8; + }=20=20=20=20=20=20=20=20=20=20=20=20 + /* calculate target store address, Rn +/- Rm, register offset. */ + if (12 =3D=3D arm_insn_r->opcode) + { + tgt_mem_addr =3D u_buf[0].unsigned_regval + u_buf[1].unsigned_= regval; + } + else + { + tgt_mem_addr =3D u_buf[1].unsigned_regval - u_buf[0].unsigned_= regval; + }=20=20=20=20=20=20=20=20=20=20=20=20 + record_buf_mem[0] =3D 2; + record_buf_mem[1] =3D tgt_mem_addr; + arm_insn_r->mem_rec_count =3D 1; + } + else if ((11 =3D=3D arm_insn_r->opcode) || (15 =3D=3D arm_insn_r->opco= de) + || (2 =3D=3D arm_insn_r->opcode) || (6 =3D=3D arm_insn_r->opcode)) + { + /* 3) store, immediate pre-indexed. */=20=20=20=20=20=20=20=20=20= =20=20=20 + /* 5) store, immediate post-indexed. */ + immed_low =3D bits (arm_insn_r->arm_insn, 0, 3);=20=20 + immed_high =3D bits (arm_insn_r->arm_insn, 8, 11); + offset_8 =3D (immed_high << 4) | immed_low; + reg_src1 =3D bits (arm_insn_r->arm_insn, 16, 19); + GET_REG_VAL(reg_cache, reg_src1, &u_buf[0].unsigned_regval); + /* calculate target store address, Rn +/- Rm, register offset. */ + if ((15 =3D=3D arm_insn_r->opcode) || (6 =3D=3D arm_insn_r->opcode= )) + { + tgt_mem_addr =3D u_buf[0].unsigned_regval + offset_8; + } + else + { + tgt_mem_addr =3D u_buf[0].unsigned_regval - offset_8; + }=20=20=20=20=20=20=20=20=20=20=20=20 + record_buf_mem[0] =3D 2; + record_buf_mem[1] =3D tgt_mem_addr; + arm_insn_r->mem_rec_count =3D 1; + /* record Rn also as it changes. */ + record_buf[0] =3D bits (arm_insn_r->arm_insn, 16, 19);=20=20 + arm_insn_r->reg_rec_count =3D 1; + } + else if ((9 =3D=3D arm_insn_r->opcode) || (13 =3D=3D arm_insn_r->opcod= e) + || (0 =3D=3D arm_insn_r->opcode) || (4 =3D=3D arm_insn_r->opcode)) + { + /* 4) store, register pre-indexed. */ + /* 6) store, register post -indexed. */ + reg_src1 =3D bits (arm_insn_r->arm_insn, 0, 3);=20=20 + reg_src2 =3D bits (arm_insn_r->arm_insn, 16, 19); + GET_REG_VAL (reg_cache, reg_src1, &u_buf[0].unsigned_regval); + GET_REG_VAL (reg_cache, reg_src2, &u_buf[1].unsigned_regval); + /* calculate target store address, Rn +/- Rm, register offset. */ + if ((13 =3D=3D arm_insn_r->opcode) || (4 =3D=3D arm_insn_r->opcode= )) + { + tgt_mem_addr =3D u_buf[0].unsigned_regval + u_buf[1].unsigned_= regval; + } + else + { + tgt_mem_addr =3D u_buf[1].unsigned_regval - u_buf[0].unsigned_= regval; + }=20=20=20=20=20=20=20=20=20=20=20=20 + record_buf_mem[0] =3D 2; + record_buf_mem[1] =3D tgt_mem_addr; + arm_insn_r->mem_rec_count =3D 1; + /* record Rn also as it changes. */ + record_buf[0] =3D bits (arm_insn_r->arm_insn, 16, 19);=20=20=20=20= =20=20=20=20=20=20=20=20=20=20 + arm_insn_r->reg_rec_count =3D 1; + } + /* DSP insns (e.g. LDRD) TBD. */ + }=20=20 + else if ((1 =3D=3D arm_insn_r->decode) && (0x12 =3D=3D opcode1) + && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1)) + { + /* handle BX, branch and link/exchange. */ + /* branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */ + record_buf[0] =3D ARM_PS_REGNUM; + arm_insn_r->reg_rec_count =3D 1; + }=20=20 + else if ((1 =3D=3D arm_insn_r->decode) && (0x16 =3D=3D opcode1) + && (sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1)) + && (sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1))) + { + /* count leading zeros: CLZ. */ + record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15); + arm_insn_r->reg_rec_count =3D 1; + } + else if ((!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) + && ((8 =3D=3D arm_insn_r->opcode) || (10 =3D=3D arm_insn_r->opco= de)) + && (sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)) + && (sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)) + ) + {=20=20=20=20=20=20 + /* handle MRS insn. */ + record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15);=20=20 + arm_insn_r->reg_rec_count =3D 1; + }=20=20=20=20=20=20 + else if (arm_insn_r->opcode <=3D 15)=20 + { + /* normal data processing insns. */ + /* out of 11 shifter operands mode, all the insn modifies destinatio= n=20 + register, which is specified by 13-16 decode. */ + record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15); + record_buf[1] =3D ARM_PS_REGNUM;=20=20=20=20=20=20=20=20 + arm_insn_r->reg_rec_count =3D 2; + } + else + { + gdb_assert_not_reached ("no decoding pattern found"); + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_m= em); + return 0; +} + +/* handling opcode 001 insns. */ + +static int=20 +arm_handle_data_proc_imm_insn (insn_decode_record *arm_insn_r) +{ + uint32_t record_buf[8], record_buf_mem[8]; + + arm_insn_r->opcode =3D bits (arm_insn_r->arm_insn, 21, 24); + arm_insn_r->decode =3D bits (arm_insn_r->arm_insn, 4, 7); + + if (((9 =3D=3D arm_insn_r->opcode) || (11 =3D=3D arm_insn_r->opcode)) + && (2 =3D=3D bits (arm_insn_r->arm_insn, 20, 21)) + && (sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)) + ) + { + /* handle MSR insn. */ + if (9 =3D=3D arm_insn_r->opcode) + { + /*CSPR is going to be changed. */ + record_buf[0] =3D ARM_PS_REGNUM; + arm_insn_r->reg_rec_count =3D 1; + }=20=20=20=20 + else + { + /* SPSR is going to be changed. */ + /* Oza: FIX ME ? how to read SPSR value? */ + } + }=20=20=20 + else if (arm_insn_r->opcode <=3D 15)=20 + { + /* normal data processing insns. */ + /* out of 11 shifter operands mode, all the insn modifies destinatio= n=20 + register, which is specified by 13-16 decode. */ + record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15); + record_buf[1] =3D ARM_PS_REGNUM;=20=20=20=20=20=20=20=20 + arm_insn_r->reg_rec_count =3D 2; + } + else + { + gdb_assert_not_reached ("no decoding pattern found"); + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_m= em); + return 0; +} + +/* handling opcode 010 insns. */ + +static int=20 +arm_handle_ld_st_imm_offset_insn (insn_decode_record *arm_insn_r) +{ + struct regcache *reg_cache =3D arm_insn_r->regcache; + + uint32_t reg_src1 =3D 0 , reg_dest =3D 0; + uint32_t offset_12 =3D 0, tgt_mem_addr =3D 0; + uint32_t record_buf[8], record_buf_mem[8]; + + struct + { + ULONGEST unsigned_regval; + } u_buf; + + memset(&u_buf, 0, sizeof(u_buf)); + arm_insn_r->opcode =3D bits (arm_insn_r->arm_insn, 21, 24); + arm_insn_r->decode =3D bits (arm_insn_r->arm_insn, 4, 7); + + if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))=20 + { + reg_dest =3D bits (arm_insn_r->arm_insn, 12, 15); + /* LDR insn has a capability to do branching, if + MOV LR, PC is precedded by LDR insn having Rn as R15=20 + in that case, it emulates branch and link insn, and hence we= =20 + need to save CSPR and PC as well. */ + if (15 !=3D reg_dest) + { + record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15); + arm_insn_r->reg_rec_count =3D 1; + } + else + { + record_buf[0] =3D reg_dest; + record_buf[1] =3D ARM_PS_REGNUM;=20 + arm_insn_r->reg_rec_count =3D 2; + } + } + else + { + if ((8 =3D=3D arm_insn_r->opcode) || (10 =3D=3D arm_insn_r->opcode)= =20=20=20=20=20 + || (12 =3D=3D arm_insn_r->opcode) || (14 =3D=3D arm_insn_r->opcode) + || (9 =3D=3D arm_insn_r->opcode) || (11 =3D=3D arm_insn_r->opcode)= =20=20=20=20=20 + || (13 =3D=3D arm_insn_r->opcode) || (15 =3D=3D arm_insn_r->opcode)= =20=20=20=20=20=20=20=20=20 + || (0 =3D=3D arm_insn_r->opcode) || (2 =3D=3D arm_insn_r->opcode)=20= =20=20=20=20 + || (4 =3D=3D arm_insn_r->opcode) || (6 =3D=3D arm_insn_r->opcode) + || (1 =3D=3D arm_insn_r->opcode) || (3 =3D=3D arm_insn_r->opcode) + || (5 =3D=3D arm_insn_r->opcode) || (7 =3D=3D arm_insn_r->opcode)) + { + /* store, immediate offset, immediate pre-indexed, + immediate post-indexed. */=20=20=20=20=20=20=20=20= =20=20 + reg_src1 =3D bits (arm_insn_r->arm_insn, 16, 19); + offset_12 =3D bits (arm_insn_r->arm_insn, 0, 11); + GET_REG_VAL (reg_cache, reg_src1, &u_buf.unsigned_regval); + /* U =3D=3D 1 */ + if (bit (arm_insn_r->arm_insn, 23)) + {=20=20=20 + tgt_mem_addr =3D u_buf.unsigned_regval + offset_12; + } + else + { + tgt_mem_addr =3D u_buf.unsigned_regval - offset_12; + } + + switch(arm_insn_r->opcode) + { + case 8: + case 12:=20=20=20=20=20=20=20=20=20=20 + case 9:=20=20=20 + case 13:=20=20=20 + case 1:=20=20=20 + case 5:=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 + /* STR insn, STRT insn. */ + record_buf_mem[0] =3D 4;=20=20=20=20 + break;=20=20=20 + + case 10: + case 14:=20=20=20=20=20=20=20=20=20=20=20=20 + case 11:=20=20=20 + case 15:=20=20=20 + case 3:=20=20=20 + case 7:=20=20=20 + /* STRB insn, STRBT insn. */ + record_buf_mem[0] =3D 1;=20=20=20=20 + break;=20=20=20 + + default: + gdb_assert_not_reached ("Invalid addressing mode for insn"= ); + break;=20=20=20 + }=20=20=20=20=20=20=20 + record_buf_mem[1] =3D tgt_mem_addr;=20=20=20=20 + arm_insn_r->mem_rec_count =3D 1; +=20=20=20=20=20=20=20=20=20=20 + if ((9 =3D=3D arm_insn_r->opcode) || (11 =3D=3D arm_insn_r->opco= de)=20=20=20=20=20 + || (13 =3D=3D arm_insn_r->opcode) || (15 =3D=3D arm_insn_r->opco= de) + || (0 =3D=3D arm_insn_r->opcode) || (2 =3D=3D arm_insn_r->opcode= )=20=20=20=20=20 + || (4 =3D=3D arm_insn_r->opcode) || (6 =3D=3D arm_insn_r->opcode= )=20=20=20=20=20=20=20=20=20=20 + || (1 =3D=3D arm_insn_r->opcode) || (3 =3D=3D arm_insn_r->opcode) + || (5 =3D=3D arm_insn_r->opcode) || (7 =3D=3D arm_insn_r->opcode= )) + { + /* we are handling pre-indexed mode; post-indexed mode; + where Rn is going to be changed. */ + record_buf[0] =3D reg_src1;=20=20=20=20 + arm_insn_r->reg_rec_count =3D 1; + }=20=20 + }=20=20 + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_m= em); + return 0; +} + +/* handling opcode 011 insns. */ + +static int=20 +arm_handle_ld_st_reg_offset_insn (insn_decode_record *arm_insn_r) +{ + struct regcache *reg_cache =3D arm_insn_r->regcache; + + uint32_t shift_imm =3D 0; + uint32_t reg_src1 =3D 0, reg_src2 =3D 0, reg_dest =3D 0; + uint32_t immed_high =3D 0, immed_low =3D 0, offset_12 =3D 0, tgt_mem_add= r =3D 0; + uint32_t record_buf[8], record_buf_mem[8]; + + struct + { + ULONGEST signed_word; + ULONGEST unsigned_regval; + } u_buf[2]; + + memset(&u_buf, 0, sizeof(u_buf)); + arm_insn_r->opcode =3D bits (arm_insn_r->arm_insn, 21, 24); + arm_insn_r->decode =3D bits (arm_insn_r->arm_insn, 4, 7); + + /* handle enhanced store insns and LDRD DSP insn, + let us begin according to addressing modes for store insns=20 + STRH insn. */ + + /* LDR or STR? */ + if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) + { + reg_dest =3D bits (arm_insn_r->arm_insn, 12, 15); + /* LDR insn has a capability to do branching, if + MOV LR, PC is precedded by LDR insn having Rn as R15=20 + in that case, it emulates branch and link insn, and hence we= =20 + need to save CSPR and PC as well. */ + if (15 !=3D reg_dest) + { + record_buf[0] =3D bits (arm_insn_r->arm_insn, 12, 15); + arm_insn_r->reg_rec_count =3D 1; + } + else + { + record_buf[0] =3D reg_dest; + record_buf[1] =3D ARM_PS_REGNUM;=20 + arm_insn_r->reg_rec_count =3D 2; + }=20 + } + else + { + if ((8 =3D=3D arm_insn_r->opcode) || (10 =3D=3D arm_insn_r->opcode)=20= =20=20=20=20 + || (12 =3D=3D arm_insn_r->opcode) || (14 =3D=3D arm_insn_r->opcode) + || (9 =3D=3D arm_insn_r->opcode) || (11 =3D=3D arm_insn_r->opcode)=20= =20=20=20=20 + || (13 =3D=3D arm_insn_r->opcode) || (15 =3D=3D arm_insn_r->opcode)=20= =20=20=20=20=20=20=20=20 + || (0 =3D=3D arm_insn_r->opcode) || (2 =3D=3D arm_insn_r->opcode)=20= =20=20=20=20 + || (4 =3D=3D arm_insn_r->opcode) || (6 =3D=3D arm_insn_r->opcode)=20= =20=20=20=20=20=20=20=20 + || (1 =3D=3D arm_insn_r->opcode) || (3 =3D=3D arm_insn_r->opcode) + || (5 =3D=3D arm_insn_r->opcode) || (7 =3D=3D arm_insn_r->opcode)) + { + if (! bits (arm_insn_r->arm_insn, 4, 11)) + { + /* store insn, register offset and register pre-indexed,=20 + register post-indexed. */ + /* get Rm. */ + reg_src1 =3D bits (arm_insn_r->arm_insn, 0, 3);=20=20 + /* get Rn. */ + reg_src2 =3D bits (arm_insn_r->arm_insn, 16, 19); + GET_REG_VAL (reg_cache, reg_src1, &u_buf[0].unsigned_regval); + GET_REG_VAL (reg_cache, reg_src2,=20 &u_buf[1].unsigned_regval);=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20 + if (15 =3D=3D reg_src2) + { + /* if R15 was used as Rn, hence current PC+8. */ + /* pre-indexed mode doesnt reach here ; illegal insn. */ + u_buf[0].unsigned_regval =3D u_buf[0].unsigned_regval + 8; + }=20=20=20=20=20=20=20=20=20=20=20=20 + /* calculate target store address, Rn +/- Rm, register offset.= */ + /* U =3D=3D 1. */ + if (bit (arm_insn_r->arm_insn, 23)) + { + tgt_mem_addr =3D u_buf[0].unsigned_regval +=20 u_buf[1].unsigned_regval; + } + else + { + tgt_mem_addr =3D u_buf[1].unsigned_regval -=20 u_buf[0].unsigned_regval; + }=20=20=20=20=20=20=20=20=20=20=20=20 + + switch(arm_insn_r->opcode) + { + case 8: + case 12:=20=20=20=20=20=20=20=20=20=20 + case 9:=20=20=20 + case 13:=20=20=20 + case 1:=20=20=20 + case 5:=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 + /* STR insn, STRT insn. */ + record_buf_mem[0] =3D 4;=20=20=20=20 + break;=20=20=20 + + case 10: + case 14:=20=20=20=20=20=20=20=20=20=20=20=20 + case 11:=20=20=20 + case 15:=20=20=20 + case 3:=20=20=20 + case 7:=20=20=20 + /* STRB insn, STRBT insn. */ + record_buf_mem[0] =3D 1;=20=20=20=20 + break;=20=20=20 + + default: + gdb_assert_not_reached ("Invalid addressing mode for ins= n"); + break;=20=20=20 + }=20=20=20=20=20=20=20 + record_buf_mem[1] =3D tgt_mem_addr; + arm_insn_r->mem_rec_count =3D 1; + + if ((9 =3D=3D arm_insn_r->opcode) || (11 =3D=3D arm_insn_r->op= code)=20=20=20=20=20 + || (13 =3D=3D arm_insn_r->opcode) || (15 =3D=3D arm_insn_r->op= code) + || (0 =3D=3D arm_insn_r->opcode) || (2 =3D=3D arm_insn_r->opco= de)=20=20=20=20=20 + || (4 =3D=3D arm_insn_r->opcode) || (6 =3D=3D arm_insn_r->opco= de)=20=20=20=20=20=20=20=20=20 + || (1 =3D=3D arm_insn_r->opcode) || (3 =3D=3D arm_insn_r->opco= de) + || (5 =3D=3D arm_insn_r->opcode) || (7 =3D=3D arm_insn_r->opco= de)) + { + /* Rn is going to be changed in pre-indexed mode and=20 + post-indexed mode as well. */ + record_buf[0] =3D reg_src2;=20=20 + arm_insn_r->reg_rec_count =3D 1; + }=20=20=20=20=20 + } + else + { + /* store insn, scaled register offset; scaled pre-indexed. */ + offset_12 =3D bits (arm_insn_r->arm_insn, 5, 6); + /* get Rm. */ + reg_src1 =3D bits (arm_insn_r->arm_insn, 0, 3);=20=20 + /* get Rn. */ + reg_src2 =3D bits (arm_insn_r->arm_insn, 16, 19); + /* get shift_imm. */ + shift_imm =3D bits (arm_insn_r->arm_insn, 7, 11); + GET_REG_VAL (reg_cache, reg_src1, &u_buf[0].unsigned_regval); + GET_REG_VAL_SIGNED (reg_cache, reg_src1, &u_buf[0].signed_word= ); + GET_REG_VAL (reg_cache, reg_src2, &u_buf[1].unsigned_regval);= =20=20=20 + /* offset_12 used as shift. */ + switch(offset_12) + { + case 0: + /* offset_12 used as index. */ + offset_12 =3D u_buf[0].unsigned_regval << shift_imm; + break; +=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 + case 1: + offset_12 =3D (!shift_imm)?0:u_buf[0].unsigned_regval >>= =20 shift_imm;=20 + break; +=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 + case 2: + if (!shift_imm) + { + if (bit (u_buf[0].unsigned_regval, 31)) + { + offset_12 =3D 0xFFFFFFFF; + } + else + { + offset_12 =3D 0; + } + } + else + { + /* this is arithmetic shift. */ + offset_12 =3D u_buf[0].signed_word >> shift_imm; + } + break;=20=20 +=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 + case 3: + if (!shift_imm) + { + GET_REG_VAL (reg_cache, ARM_PS_REGNUM,=20 &u_buf[1].unsigned_regval); + /* get C flag value and shift it by 31. */ + offset_12 =3D (((bit (u_buf[1].unsigned_regval, 29))= << 31)=20 \ + | (u_buf[0].unsigned_regval) >> 1); + } + else + {=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20 + offset_12 =3D (u_buf[0].unsigned_regval >> shift_imm= ) \ + | (u_buf[0].unsigned_regval << (sizeof(uint32_t) = -=20 shift_imm)); + } + break; + + default: + gdb_assert_not_reached ("Invalid addressing mode for ins= n"); + break; + }=20=20=20=20=20=20 + + GET_REG_VAL (reg_cache, reg_src2, &u_buf[1].unsigned_regval);= =20 + /* U =3D=3D 1 */ + if (bit (arm_insn_r->arm_insn, 23)) + { + tgt_mem_addr =3D u_buf[1].unsigned_regval + offset_12; + } + else + { + tgt_mem_addr =3D u_buf[1].unsigned_regval - offset_12; + }=20=20=20=20=20=20=20 +=20=20=20=20=20=20=20=20=20=20=20=20 + switch (arm_insn_r->opcode) + { + case 8: + case 12:=20=20=20=20=20=20=20=20=20=20 + case 9:=20=20=20 + case 13:=20=20=20 + case 1:=20=20=20 + case 5:=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 + /* STR insn, STRT insn. */ + record_buf_mem[0] =3D 4;=20=20=20=20 + break;=20=20=20 + + case 10: + case 14:=20=20=20=20=20=20=20=20=20=20=20=20 + case 11:=20=20=20 + case 15:=20=20=20 + case 3:=20=20=20 + case 7:=20=20=20 + /* STRB insn, STRBT insn. */ + record_buf_mem[0] =3D 1;=20=20=20=20 + break;=20=20=20 + + default: + gdb_assert_not_reached ("Invalid addressing mode for ins= n"); + break;=20=20=20 + }=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 + record_buf_mem[1] =3D tgt_mem_addr; + arm_insn_r->mem_rec_count =3D 1; +=20=20=20=20=20=20=20=20=20=20=20=20 + if ((9 =3D=3D arm_insn_r->opcode) || (11 =3D=3D arm_insn_r->op= code)=20=20=20=20=20 + || (13 =3D=3D arm_insn_r->opcode) || (15 =3D=3D arm_insn_r->op= code) + || (0 =3D=3D arm_insn_r->opcode) || (2 =3D=3D arm_insn_r->opco= de)=20=20=20=20=20 + || (4 =3D=3D arm_insn_r->opcode) || (6 =3D=3D arm_insn_r->opco= de)=20=20=20=20=20=20=20=20=20 + || (1 =3D=3D arm_insn_r->opcode) || (3 =3D=3D arm_insn_r->opco= de) + || (5 =3D=3D arm_insn_r->opcode) || (7 =3D=3D arm_insn_r->opco= de)) + { + /* Rn is going to be changed in register scaled pre-indexe= d=20 + mode, and scaled post indexed mode. */ + record_buf[0] =3D reg_src2;=20=20 + arm_insn_r->reg_rec_count =3D 1; + } + }=20=20=20=20=20=20=20=20=20=20=20=20 + }=20=20 + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_m= em); + return 0;=20=20=20 +} + +/* handling opcode 100 insns. */ + +static int=20 +arm_handle_ld_st_multiple_insn (insn_decode_record *arm_insn_r) +{=20=20=20 + struct regcache *reg_cache =3D arm_insn_r->regcache; + + uint32_t register_list[16]=3D{0}, register_count=3D0, register_bits=3D0;= =20=20=20=20=20=20=20 + uint32_t shift_imm=3D0; + uint32_t reg_src1=3D0, reg_src2=3D0, addr_mode=3D0; + uint32_t start_address=3D0, index =3D 0; + uint32_t record_buf[24], record_buf_mem[48]; + + struct + { + ULONGEST unsigned_regval; + } u_buf[2]; + + memset (&u_buf, 0, sizeof(u_buf)); + + /* this mode is exclusively for load and store multiple. */ + /* handle incremenrt after/before and decrment after.before mode; + Rn is changing depending on W bit, but as of now we store Rn too=20 without optmization. */ + + if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) + { + /* LDR (1,2,3) where LDR (3) changes CPSR too. */ + + register_bits =3D bits (arm_insn_r->arm_insn, 0, 15); + /* get Rn. */ + reg_src1 =3D bits (arm_insn_r->arm_insn, 16, 19); + while (register_bits) + { + if (register_bits & 0x00000001) + register_list[register_count++] =3D 1; + register_bits =3D register_bits >> 1; + } +=20=20=20=20=20=20 + /* extra space for Base Register and CPSR; wihtout optmization. */ + record_buf[register_count] =3D reg_src1; + record_buf[register_count + 1] =3D ARM_PS_REGNUM; + for (register_count =3D 0; register_count < 8; register_count++) + { + if (register_list[register_count]) + { + /* register_count gives total no of registers and dually wor= king=20 + as reg number. */ + record_buf[index] =3D register_count; + index++; + } + } + arm_insn_r->reg_rec_count =3D register_count + 2; + } + else + { + /* it handles both STM(1) and STM(2). */ + addr_mode =3D bits (arm_insn_r->arm_insn, 23, 24);=20=20=20=20 + + register_bits =3D bits (arm_insn_r->arm_insn, 0, 15); + /* get Rn. */ + reg_src1 =3D bits (arm_insn_r->arm_insn, 16, 19); + GET_REG_VAL (reg_cache, reg_src1, &u_buf[0].unsigned_regval); + while (register_bits) + { + if (register_bits & 0x00000001) + register_count++; + register_bits =3D register_bits >> 1; + } + + switch(addr_mode) + { + /* Decrement after. */=20 + case 0:=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20 + start_address =3D (u_buf[0].unsigned_regval) - (register_count *= 4) +=20 4; + while (register_count) + { + record_buf_mem[(register_count * 2) - 1] =3D start_address; + record_buf_mem[(register_count * 2) - 2] =3D 4; + start_address =3D start_address + 4; + register_count--; + } + arm_insn_r->mem_rec_count =3D register_count; + break;=20=20=20=20 + + /* Increment after. */ + case 1: + start_address =3D u_buf[0].unsigned_regval; + while (register_count) + { + record_buf_mem[(register_count * 2) - 1] =3D start_address; + record_buf_mem[(register_count * 2) - 2] =3D 4; + start_address =3D start_address + 4; + register_count--; + } + arm_insn_r->mem_rec_count =3D register_count; + break;=20=20=20=20 + + /* Decrement before. */ + case 2: +=20=20=20=20=20=20=20=20=20=20 + start_address =3D (u_buf[0].unsigned_regval) - (register_count *= 4); + while (register_count) + {=20=20=20=20 + record_buf_mem[(register_count * 2) - 1] =3D start_address; + record_buf_mem[(register_count * 2) - 2] =3D 4; + start_address =3D start_address + 4; + register_count--; + } + arm_insn_r->mem_rec_count =3D register_count; + break;=20=20=20=20 + + /* Increment before. */ + case 3: + start_address =3D u_buf[0].unsigned_regval + 4; + while (register_count) + { + record_buf_mem[(register_count * 2) - 1] =3D start_address; + record_buf_mem[(register_count * 2) - 2] =3D 4; + start_address =3D start_address + 4; + register_count--; + } + arm_insn_r->mem_rec_count =3D register_count; + break;=20=20=20=20 + + default: + gdb_assert_not_reached ("Invalid addressing mode for insn"); + break;=20=20=20=20 + } + + /* base register also changes; based on condition and W bit. */ + /* we save it anyway without optimization. */ + record_buf[0] =3D reg_src1; + arm_insn_r->reg_rec_count =3D 1; + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_m= em); + return 0;=20=20=20 +} + +/* handling opcode 101 insns. */ + +static int=20 +arm_handle_brn_insn (insn_decode_record *arm_insn_r) +{ + + uint32_t record_buf[8]; + + /* handle B, BL, BLX(1) insns. */ + /* wihtout optmization we save link register,=20 + CSPR for the insn which changes T bit. */ + record_buf[0] =3D ARM_PS_REGNUM; + record_buf[1] =3D ARM_LR_REGNUM; + arm_insn_r->reg_rec_count =3D 2;=20=20 + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); +=20=20=20=20 + return 0; +} + +/* handling opcode 110 insns. */ + +static int=20 +arm_handle_coproc_insn (insn_decode_record *arm_insn_r) +{ + printf_unfiltered (_("Process record does not support instruction " + "0x%0x at address %s.\n"), + arm_insn_r->arm_insn, + paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)= ); + + return -1;=20=20=20 +} + +/* handling opcode 111 insns. */ + +static int=20 +arm_handle_coproc_data_proc_insn (insn_decode_record *arm_insn_r) +{ + struct gdbarch_tdep *tdep =3D gdbarch_tdep (arm_insn_r->gdbarch); + struct regcache *reg_cache =3D arm_insn_r->regcache; +=20=20=20 + uint32_t shift_imm =3D 0; + uint32_t reg_src1 =3D 0, reg_src2 =3D 0, addr_mode =3D 0; + uint32_t start_address =3D 0; + + /* handle SWI insn; system call would be handled over here. */ + + arm_insn_r->opcode =3D bits (arm_insn_r->arm_insn, 24, 27); + if (15 =3D=3D arm_insn_r->opcode)=20 + { + /* handle arm syscall insn. */ + if (tdep->arm_swi_record !=3D NULL) + { + tdep->arm_swi_record(reg_cache); + } + else + { + printf_unfiltered (_("no syscall record support\n")); + return -1; + } + } + + printf_unfiltered (_("Process record does not support instruction " + "0x%0x at address %s.\n"), + arm_insn_r->arm_insn, + paddress (arm_insn_r->gdbarch,=20 arm_insn_r->this_addr)); + return -1;=20=20=20 +} + +/* handling opcode 000 insns. */ + +static int=20 +thumb_handle_shift_add_sub_insn (insn_decode_record *thumb_insn_r) +{ + uint32_t record_buf[8]; + uint32_t reg_src1 =3D 0; + + + struct + { + ULONGEST unsigned_regval; + } u_buf; + + reg_src1 =3D bits (thumb_insn_r->arm_insn, 0, 2); + + record_buf[0] =3D ARM_PS_REGNUM; + record_buf[1] =3D reg_src1; + thumb_insn_r->reg_rec_count =3D 2; + + REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_b= uf); + + return 0;=20=20=20 +} + + +/* handling opcode 001 insns. */ + +static int=20 +thumb_handle_add_sub_cmp_mov_insn (insn_decode_record *thumb_insn_r) +{ + uint32_t record_buf[8];=20 + uint32_t reg_src1 =3D 0; + + reg_src1 =3D bits (thumb_insn_r->arm_insn, 8, 10); + + record_buf[0] =3D ARM_PS_REGNUM; + record_buf[1] =3D reg_src1; + thumb_insn_r->reg_rec_count =3D 2; + + REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_b= uf); + + return 0;=20=20 +} + +/* handling opcode 010 insns. */ + +static int=20 +thumb_handle_ld_st_reg_offset_insn (insn_decode_record *thumb_insn_r) +{ + struct regcache *reg_cache =3D thumb_insn_r->regcache; + uint32_t record_buf[8], record_buf_mem[8]; + + uint32_t reg_src1 =3D 0, reg_src2 =3D 0; + uint32_t opcode1 =3D 0, opcode2 =3D 0, opcode3 =3D 0; + +=20=20 + struct + { + ULONGEST unsigned_regval; + gdb_byte buf[4]; + } u_buf[2]; + + opcode1 =3D bits (thumb_insn_r->arm_insn, 10, 12); + + if (bit (thumb_insn_r->arm_insn, 12)) + { + /* handle load/store register offset. */=20 + opcode2 =3D bits (thumb_insn_r->arm_insn, 9, 10);=20=20 + if ((opcode2 >=3D 12) && (opcode2 <=3D 15)) + {=20=20=20=20=20=20=20=20=20 + /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */ + reg_src1 =3D bits (thumb_insn_r->arm_insn,0, 2);=20=20=20=20=20= =20=20=20=20=20=20 + record_buf[0] =3D reg_src1; + thumb_insn_r->reg_rec_count =3D 1; + } + else if ((opcode2 >=3D 8) && (opcode2 <=3D 10)) + { + /* STR(2), STRB(2), STRH(2) . */ + reg_src1 =3D bits (thumb_insn_r->arm_insn, 3, 5); + reg_src2 =3D bits (thumb_insn_r->arm_insn, 6, 8); + GET_REG_VAL (reg_cache, reg_src1, &u_buf[0].unsigned_regval); + GET_REG_VAL (reg_cache, reg_src2, &u_buf[1].unsigned_regval); + if (8 =3D=3D opcode2) + record_buf_mem[0] =3D 4; /* STR (2). */=20=20=20=20=20=20= =20=20=20=20=20=20=20 + else if (10 =3D=3D opcode2) + record_buf_mem[0] =3D 1; /* STRB (2). */ + else if (9 =3D=3D opcode2) + record_buf_mem[0] =3D 2; /* STRH (2). */ + record_buf_mem[1] =3D=20 u_buf[0].unsigned_regval+u_buf[1].unsigned_regval;=20 + thumb_insn_r->mem_rec_count =3D 1; + }=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 + }=20=20=20=20=20=20=20=20=20=20=20=20 + else if (bit (thumb_insn_r->arm_insn, 11)) + { + /* handle load from literal pool. */=20=20 + /* LDR(3). */ + reg_src1 =3D bits (thumb_insn_r->arm_insn, 8, 10);=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 + record_buf[0] =3D reg_src1; + thumb_insn_r->reg_rec_count =3D 1; + }=20=20=20=20 + else if (opcode1) + { + opcode2 =3D bits (thumb_insn_r->arm_insn, 8, 9); + opcode3 =3D bits (thumb_insn_r->arm_insn, 0, 2); + if ((3 =3D=3D opcode2) && (!opcode3)) + { + /* branch with exchange. */ + record_buf[0] =3D ARM_PS_REGNUM; + thumb_insn_r->reg_rec_count =3D 1; + } + else + { + /* format 8; special data processing insns. */ + reg_src1 =3D bits (thumb_insn_r->arm_insn, 0, 2); + record_buf[0] =3D ARM_PS_REGNUM; + record_buf[1] =3D reg_src1; + thumb_insn_r->reg_rec_count =3D 2; + } + } + else + { + /* format 5; data processing insns. */ + reg_src1 =3D bits (thumb_insn_r->arm_insn, 0, 2); + if (bit (thumb_insn_r->arm_insn, 7)) + { + reg_src1 =3D reg_src1 + 8; + } + record_buf[0] =3D ARM_PS_REGNUM; + record_buf[1] =3D reg_src1; + thumb_insn_r->reg_rec_count =3D 2; + }=20=20 + + REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_b= uf); + MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,=20 record_buf_mem); +=20=20 + return 0; +} + +/* handling opcode 001 insns. */ + +static int=20 +thumb_handle_ld_st_imm_offset_insn (insn_decode_record *thumb_insn_r) +{ + struct regcache *reg_cache =3D thumb_insn_r->regcache; + uint32_t record_buf[8], record_buf_mem[8]; +=20=20 + uint32_t reg_val1 =3D 0; + uint32_t reg_src1 =3D 0; + uint32_t opcode =3D 0, immed_5 =3D 0; + + struct + { + ULONGEST unsigned_regval; + } u_buf; + + opcode =3D bits (thumb_insn_r->arm_insn, 11, 12); + + if (opcode) + { + /* LDR(1). */ + reg_src1 =3D bits (thumb_insn_r->arm_insn, 0, 2); + record_buf[0] =3D reg_src1; + thumb_insn_r->reg_rec_count =3D 1; + } + else + { + /* STR(1). */ + reg_src1 =3D bits (thumb_insn_r->arm_insn, 3, 5); + immed_5 =3D bits (thumb_insn_r->arm_insn, 6, 10); + GET_REG_VAL (reg_cache, reg_src1, &u_buf.unsigned_regval); + record_buf_mem[0] =3D 4; + record_buf_mem[1] =3D u_buf.unsigned_regval + (immed_5 * 4); + thumb_insn_r->mem_rec_count =3D 1; + } +=20=20 + REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_b= uf); + MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,=20 record_buf_mem); + + return 0; +} + +/* handling opcode 100 insns. */ + +static int=20 +thumb_handle_ld_st_stack_insn (insn_decode_record *thumb_insn_r) +{=20 + struct regcache *reg_cache =3D thumb_insn_r->regcache; + uint32_t record_buf[8], record_buf_mem[8]; +=20=20 + uint32_t reg_val1 =3D 0; + uint32_t reg_src1 =3D 0; + uint32_t opcode =3D 0, immed_8 =3D 0, immed_5 =3D 0; + + struct + { + ULONGEST unsigned_regval; + } u_buf; + + opcode =3D bits (thumb_insn_r->arm_insn, 11, 12); + + if (3 =3D=3D opcode) + { + /* LDR(4). */ + reg_src1 =3D bits (thumb_insn_r->arm_insn, 8, 10); + record_buf[0] =3D reg_src1; + thumb_insn_r->reg_rec_count =3D 1; + } + else if (1 =3D=3D opcode) + { + /* LDRH(1). */ + reg_src1 =3D bits (thumb_insn_r->arm_insn, 0, 2); + record_buf[0] =3D reg_src1; + thumb_insn_r->reg_rec_count =3D 1; + } + else if (2 =3D=3D opcode) + { + /* STR(3). */ + immed_8 =3D bits (thumb_insn_r->arm_insn, 0, 7); + GET_REG_VAL (reg_cache, ARM_SP_REGNUM, &u_buf.unsigned_regval); + record_buf_mem[0] =3D 4; + record_buf_mem[1] =3D u_buf.unsigned_regval + (immed_8 * 4); + thumb_insn_r->mem_rec_count =3D 1; + } + else if (0 =3D=3D opcode) + { + /* STRH(1). */ + immed_5 =3D bits (thumb_insn_r->arm_insn, 6, 10); + reg_src1 =3D bits (thumb_insn_r->arm_insn, 3, 5); + GET_REG_VAL (reg_cache, reg_src1, &u_buf.unsigned_regval); + record_buf_mem[0] =3D 2; + record_buf_mem[1] =3D u_buf.unsigned_regval + (immed_5 * 2); + thumb_insn_r->mem_rec_count =3D 1; + } + + REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_b= uf); + MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,=20 record_buf_mem); +=20=20 + return 0; +} + +/* handling opcode 101 insns. */ + +static int=20 +thumb_handle_misc_insn (insn_decode_record *thumb_insn_r) +{ + struct regcache *reg_cache =3D thumb_insn_r->regcache; +=20=20 + uint32_t reg_val1 =3D 0; + uint32_t reg_src1 =3D 0; + uint32_t opcode =3D 0, opcode1 =3D 0, opcode2 =3D 0, immed_8 =3D 0, imme= d_5 =3D 0; + uint32_t register_bits =3D 0, register_count =3D 0; + uint32_t register_list[8] =3D {0}, index =3D 0, start_address =3D 0; + uint32_t record_buf[24], record_buf_mem[48]; + + struct + { + ULONGEST unsigned_regval; + } u_buf; + + opcode =3D bits (thumb_insn_r->arm_insn, 11, 12); + opcode1 =3D bits (thumb_insn_r->arm_insn, 8, 12); + opcode2 =3D bits (thumb_insn_r->arm_insn, 9, 12); + + if (14 =3D=3D opcode2) + { + /* POP. */ + register_bits =3D bits (thumb_insn_r->arm_insn, 0, 7); + while (register_bits) + { + if (register_bits & 0x00000001) + register_list[register_count++] =3D 1; + register_bits =3D register_bits >> 1; + } + record_buf[register_count] =3D ARM_PS_REGNUM; + record_buf[register_count + 1] =3D ARM_SP_REGNUM; + for (register_count =3D 0; register_count < 8; register_count++) + { + if (register_list[register_count]) + { + record_buf[index] =3D register_count; + index++; + } + } + thumb_insn_r->reg_rec_count =3D register_count + 2; + } + else if (10 =3D=3D opcode2) + { + /* PUSH. */ + register_bits =3D bits (thumb_insn_r->arm_insn, 0, 7); + GET_REG_VAL (reg_cache, ARM_PC_REGNUM, &u_buf.unsigned_regval); + while (register_bits) + { + if (register_bits & 0x00000001) + register_count++; + register_bits =3D register_bits >> 1; + } + start_address =3D u_buf.unsigned_regval - \ + (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count)= ) ; + while (register_count) + { + record_buf_mem[(register_count * 2) - 1] =3D start_address; + record_buf_mem[(register_count * 2) - 2] =3D 4; + start_address =3D start_address + 4; + register_count--; + } + thumb_insn_r->mem_rec_count =3D register_count; + record_buf[0] =3D ARM_SP_REGNUM; + thumb_insn_r->reg_rec_count =3D 1; + } + else if (0x1E =3D=3D opcode1) + { + /* BKPT insn. */ + /* handle enhanced software breakpoint insn, BKPT. */ + /* CPSR is changed to be executed in ARM state, disabling normal=20 + interrupts, entering abort mode. */ + /* accorindly to high vector configuration PC is set accordingly. */ + /* Oza: FIX ME ? what if user hit breakpoint and type reverse, in=20 + that case, we need to go back with previous CPSR and=20 + Program Counter.. */ + record_buf[0] =3D ARM_PS_REGNUM; + record_buf[1] =3D ARM_LR_REGNUM; + thumb_insn_r->reg_rec_count =3D 2; + /* save SPSR also; how?. */ + printf_unfiltered (_("Process record does not support instruction " + "0x%0x at address %s.\n"), + thumb_insn_r->arm_insn, + paddress (thumb_insn_r->gdbarch,=20 thumb_insn_r->this_addr)); + return -1; + } + else if ((0 =3D=3D opcode) || (1 =3D=3D opcode)) + { + /* ADD(5), ADD(6). */ + reg_src1 =3D bits (thumb_insn_r->arm_insn, 8, 10); + record_buf[0] =3D reg_src1; + thumb_insn_r->reg_rec_count =3D 1; + }=20=20 + else if (2 =3D=3D opcode) + { + /* ADD(7), SUB(4). */ + reg_src1 =3D bits (thumb_insn_r->arm_insn, 8, 10); + record_buf[0] =3D ARM_SP_REGNUM; + thumb_insn_r->reg_rec_count =3D 1; + } +=20=20 + REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_b= uf); + MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,=20 record_buf_mem); +=20=20 + return 0; +} + +/* handling opcode 110 insns. */ + +static int=20 +thumb_handle_swi_insn (insn_decode_record *thumb_insn_r)=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20 +{ + struct gdbarch_tdep *tdep =3D gdbarch_tdep (thumb_insn_r->gdbarch); + struct regcache *reg_cache =3D thumb_insn_r->regcache; +=20=20 + uint32_t reg_val1 =3D 0; + uint32_t reg_src1 =3D 0; + uint32_t opcode1 =3D 0, opcode2 =3D 0, register_bits =3D 0, register_cou= nt =3D 0; + uint32_t register_list[8] =3D {0}, index =3D 0, start_address =3D 0; + uint32_t record_buf[24], record_buf_mem[48]; + + struct + { + ULONGEST unsigned_regval; + } u_buf; + + opcode1 =3D bits (thumb_insn_r->arm_insn, 8, 12); + opcode2 =3D bits (thumb_insn_r->arm_insn, 11, 12); + + if (1 =3D=3D opcode2) + { + + /* LDMIA. */ + register_bits =3D bits (thumb_insn_r->arm_insn, 0, 7); + /* get Rn. */ + reg_src1 =3D bits (thumb_insn_r->arm_insn, 8, 10); + while (register_bits) + { + if (register_bits & 0x00000001) + register_list[register_count++] =3D 1; + register_bits =3D register_bits >> 1; + } + record_buf[register_count] =3D reg_src1; + for (register_count =3D 0; register_count < 8; register_count++) + { + if (register_list[register_count]) + { + record_buf[index] =3D register_count; + index++; + } + } + thumb_insn_r->reg_rec_count =3D register_count + 1; + } + else if (0 =3D=3D opcode2) + { + /* it handles both STMIA. */ + register_bits =3D bits (thumb_insn_r->arm_insn, 0, 7); + /* get Rn. */ + reg_src1 =3D bits (thumb_insn_r->arm_insn, 8, 10); + GET_REG_VAL (reg_cache, reg_src1, &u_buf.unsigned_regval); + while (register_bits) + { + if (register_bits & 0x00000001) + register_count++; + register_bits =3D register_bits >> 1; + } + start_address =3D u_buf.unsigned_regval; + while (register_count) + { + record_buf_mem[(register_count * 2) - 1] =3D start_address; + record_buf_mem[(register_count * 2) - 2] =3D 4; + start_address =3D start_address + 4; + register_count--; + } + thumb_insn_r->mem_rec_count =3D register_count; + } + else if (0x1F =3D=3D opcode1) + { + /* handle arm syscall insn. */ + if (tdep->arm_swi_record !=3D NULL) + { + tdep->arm_swi_record(reg_cache); + } + else + { + printf_unfiltered (_("no syscall record support\n")); + return -1; + } + } + + /* B(1), conditional branch is automatically taken care in process_recor= d,=20 + as PC is saved there. */ + + REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_b= uf); + MEM_ALLOC (thumb_insn_r->arm_mems, thumb_insn_r->mem_rec_count,=20 record_buf_mem); +=20=20 + return 0; +} + +/* handling opcode 111 insns. */ + +static int=20 +thumb_handle_branch_insn (insn_decode_record *thumb_insn_r) +{ + uint32_t record_buf[8]; + uint32_t reg_val1 =3D 0; + uint32_t reg_src1 =3D 0; + uint32_t opcode =3D 0, immed_5 =3D 0; + + + /* BL , BLX(1). */=20=20 + record_buf[0] =3D ARM_PS_REGNUM; + record_buf[1] =3D ARM_LR_REGNUM; + thumb_insn_r->reg_rec_count =3D 2; + + /* B(2) is automatically taken care in process_record, as PC is saved=20 + there. */ + + REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_b= uf); +=20=20 + return 0;=20=20=20=20=20 +} + + +/* decode arm/thumb insn depending on condition cods and opcodes; and disp= atch=20 it. */ + +static int=20 +decode_insn (insn_decode_record *arm_record, uint32_t insn_size) +{ + + /* (starting from numerical 0); bits 25, 26, 27 decodes type of arm=20 instruction. */ + static int (*const arm_handle_insn[8])=20 + (insn_decode_record*) =3D=20 + {=20 + arm_handle_data_proc_misc_ld_str_insn, /* 000. */ + arm_handle_data_proc_imm_insn, /* 001. */ + arm_handle_ld_st_imm_offset_insn, /* 010. */ + arm_handle_ld_st_reg_offset_insn, /* 011. */=20=20 + arm_handle_ld_st_multiple_insn, /* 100. */ + arm_handle_brn_insn, /* 101. */ + arm_handle_coproc_insn, /* 110. */ + arm_handle_coproc_data_proc_insn /* 111. */=20=20 + }; +=20=20 + /* (starting from numerical 0); bits 13,14,15 decodes type of thumb=20 instruction. */ + static int (*const thumb_handle_insn[8])=20 + (insn_decode_record*) =3D + { \ + thumb_handle_shift_add_sub_insn, /* 000. */ + thumb_handle_add_sub_cmp_mov_insn, /* 001. */ + thumb_handle_ld_st_reg_offset_insn, /* 010. */ + thumb_handle_ld_st_imm_offset_insn, /* 011. */=20=20 + thumb_handle_ld_st_stack_insn, /* 100. */ + thumb_handle_misc_insn, /* 101. */ + thumb_handle_swi_insn, /* 110. */ + thumb_handle_branch_insn /* 111. */=20=20 + }; + + struct + { + gdb_byte buf[insn_size]; + } u_buf; + + uint32_t ret=3D0, insn_id =3D 0; +=20=20=20=20 + memset (&u_buf, 0, sizeof(u_buf)); + if (target_read_memory (arm_record->this_addr, &u_buf.buf[0], insn_size)= )=20=20=20=20 + {=20=20=20=20=20=20=20=20 + if (record_debug) + { + printf_unfiltered (_("Process record: error reading memory at " + "addr %s len =3D %d.\n"), + paddress (arm_record->gdbarch, arm_record->this_addr), insn_size= ); + return -1; + } + } + else if (ARM_INSN_SIZE_BYTES =3D=3D insn_size) + { + arm_record->arm_insn =3D (uint32_t) extract_unsigned_integer (&u_buf= .buf[0] + , ARM_INSN_SIZE_BYTES , gdbarch_byte_order (arm_record->gdbar= ch));=20 + arm_record->cond =3D bits (arm_record->arm_insn, 28, 31);=20 + insn_id =3D bits (arm_record->arm_insn, 25, 27); + ret =3D (0x0F !=3D arm_record->cond)=20 + ? arm_handle_insn[insn_id] (arm_record)=20 + : handle_extension_space (arm_record); + }=20=20=20=20 + else if (THUMB_INSN_SIZE_BYTES =3D=3D insn_size) + { + /* As thumb does not have condition codes, following field is useles= s.=20=20 */ + arm_record->cond =3D -1;=20=20=20 + arm_record->arm_insn =3D (uint32_t) extract_unsigned_integer (&u_buf= .buf[0] + , THUMB_INSN_SIZE_BYTES , gdbarch_byte_order (arm_record->gdbar= ch)); +=20=20=20=20=20=20 + insn_id =3D bits (arm_record->arm_insn, 13, 15); + ret =3D thumb_handle_insn[insn_id] (arm_record); + } + else if (THUMB2_INSN_SIZE_BYTES =3D=3D insn_size) + { + /* yet to be implemented; handle thumb2 part here. */ + printf_unfiltered (_("Process record does not support instruction 0x= %0x " + "at address %s.\n"), + arm_record->arm_insn, + paddress (arm_record->gdbarch,=20 arm_record->this_addr)); + ret =3D -1; + } + else + { + /* throw assertion. */ + gdb_assert(0); + } +=20=20 + return ret; +} + +/* Parse the current instruction and record the values of the registers and + memory that will be changed in current instruction to "record_arch_list= ". + Return -1 if something is wrong.. */ + +int=20 +arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache, + CORE_ADDR insn_addr) +{ + + enum bfd_endian byte_order =3D gdbarch_byte_order (gdbarch);=20=20 + uint32_t no_of_rec =3D 0; + uint32_t ret =3D 0; + ULONGEST t_bit =3D 0; + + struct + { + ULONGEST unsigned_regval; + } u_buf; + + insn_decode_record arm_record; + memset (&u_buf, 0, sizeof(u_buf)); + + memset (&arm_record, 0, sizeof (insn_decode_record)); + arm_record.regcache =3D regcache; + arm_record.this_addr =3D insn_addr; + arm_record.gdbarch =3D gdbarch; + + + if (record_debug > 1) + { + fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record " + "addr =3D %s\n", + paddress (gdbarch, arm_record.this_addr)); + } + + /* check the insn, whether it is thumb or arm one. */ + + t_bit =3D arm_psr_thumb_bit (arm_record.gdbarch); + GET_REG_VAL (arm_record.regcache, ARM_PS_REGNUM, &u_buf.unsigned_regval); +=20=20=20=20 + if (!(u_buf.unsigned_regval & t_bit)) + { + /* we are decoding arm insn. */ + ret =3D decode_insn (&arm_record, ARM_INSN_SIZE_BYTES);=20=20=20=20= =20=20 + } + else + { + /* we are decoding thumb insn. */ + ret =3D decode_insn (&arm_record, THUMB_INSN_SIZE_BYTES);=20=20=20=20 + } + + if (0 =3D=3D ret) + { + /* record registers. */ + record_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM); + if (arm_record.arm_regs) + { + for (no_of_rec =3D 0; no_of_rec < arm_record.reg_rec_count;=20 no_of_rec++) + { + if (record_arch_list_add_reg (arm_record.regcache \ + ,=20 (arm_record.arm_regs[no_of_rec]))); + ret =3D -1; + } + }=20=20=20 + /* record memories. */ + if (arm_record.arm_mems) + { + for (no_of_rec =3D 0; no_of_rec < arm_record.mem_rec_count;=20 no_of_rec++) + { + if (record_arch_list_add_mem \ + ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr, + arm_record.arm_mems[no_of_rec].len)) + ret =3D -1; + } + } + + if (record_arch_list_add_end ()) + ret =3D -1; + } + + if (arm_record.arm_regs) + xfree (arm_record.arm_regs); + if (arm_record.arm_mems) + xfree (arm_record.arm_mems); +=20=20 + return ret;=20 +} diff -urN arm_orig/arm-tdep.h arm_new/arm-tdep.h --- arm_orig/arm-tdep.h 2011-03-03 09:21:13.000000000 +0530 +++ arm_new/arm-tdep.h 2011-05-07 14:20:31.000000000 +0530 @@ -200,6 +200,9 @@ /* Return the expected next PC if FRAME is stopped at a syscall instruction. */ CORE_ADDR (*syscall_next_pc) (struct frame_info *frame); + + /* Parse swi insn args, sycall record. */ + int (*arm_swi_record) (struct regcache *regcache); }; =20 /* Structures used for displaced stepping. */ @@ -310,6 +313,10 @@ struct displaced_step_closure *, CORE_ADDR, CORE_ADDR, struct regcache *); =20 +extern int arm_process_record (struct gdbarch *gdbarch, + struct regcache *regcache, CORE_ADDR addr); + + /* Functions exported from armbsd-tdep.h. */ =20 /* Return the appropriate register set for the core section identified