From: Sergey Matyukevich <geomatsi@gmail.com>
To: Kirill Radkin <kirill.radkin@syntacore.com>
Cc: gdb-patches@sourceware.org, Ilya Mamay <mmamayka01@gmail.com>,
Sergey Matyukevich <geomatsi@gmail.com>
Subject: Re: [PATCH 1/2] RISC-V Vector Extension Support
Date: Mon, 14 Sep 2026 23:58:27 +0300 [thread overview]
Message-ID: <20260914210132.439986-1-geomatsi@gmail.com> (raw)
In-Reply-To: <20251107165534.1688124-1-kirill.radkin@syntacore.com>
Hi Kirill and all,
Thanks for working on this! I am not subscribed to gdb-patches, so please keep me
in CC. Just wanted to let you know that some time ago Ilya Mamay and I implemented
some bits of related functionality in the Linux kernel, see [1]. Those changes are
in the Linux kernel mainline since v7.0. The parts of those changes that may be
relevant here are as follows:
1. NT_RISCV_VECTOR now returns -ENODATA instead of -EINVAL when the V
extension is supported but not yet activated for the tracee. EINVAL is
now reserved for "V not supported at all". This was changed specifically
to match what gdbserver already expects. Before this change kernels
returned EINVAL in both cases.
2. vlenb in the vector context is now initialised correctly rather than
left zero until the first context switch after the state goes dirty.
Before that change early attach with ptrace could see zero vlenb.
3. PTRACE_SETREGSET on NT_RISCV_VECTOR now strictly validates the input
vector CSRs. The attempts to set reserved bits or invalid fields
combinations are rejected. Also strict VL checks are enforced against
calculated VLMAX values.
Our kernel patch series also added a new selftest that exercies exactly
those paths, see tools/testing/selftests/riscv/vector/validate_v_ptrace.c
in the kernel source tree. The v_csr_invalid and v_csr_valid fixture variants
there document what the kernel now accepts and rejects,
which may be useful as a reference.
I tested our kernel changes on rv32/rv64 qemu and on RISC-V hardware including
c908 (RVV 1.0) and c906 (XTheadVector 1.0 which is close to RVV 0.7.1, see [2]).
So let me know if I can help with testing your gdb patch series on the same
platforms.
Finally...
1. IIUC despite our changes, you will have to support both behaviours for a while
in order to support older kernels =(
2. Could you please check setup_vector_regset in your patch. The vlenb is in bytes,
so either do not multiply vecreg_size by 8 or multiply sizeof by 8 as well (e.g.
if you need bits).
[1] https://lore.kernel.org/linux-riscv/20251214163537.1054292-1-geomatsi@gmail.com/
[2] https://github.com/XUANTIE-RV/thead-extension-spec/blob/master/xtheadvector.adoc
Regards,
Sergey
prev parent reply other threads:[~2026-09-14 21:02 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-07 16:55 Kirill Radkin
2025-11-07 16:55 ` [PATCH 2/2] RISC-V Vector Extension Support Testing Kirill Radkin
2026-09-03 22:30 ` [PATCH 1/2] RISC-V Vector Extension Support Peter Bergner
2026-09-14 20:58 ` Sergey Matyukevich [this message]
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