Add support for the FEAT_S1POE POR_EL0 register on AArch64.

This patch adds POR_EL0 to the AArch64 register set and reads/writes it
using the NT_ARM_POE ptrace regset.

It also adds POE pseudo-registers por_p0 through por_p15, with each
pseudo-register mapping to a 4-bit field in POR_EL0, starting from the
least-significant nibble.

POR_EL0 and the POE pseudo-registers are added to the "por" register
group, allowing them to be displayed together using the
"info registers por" command.

With this change, POR_EL0 is accessible through:

* info registers
* info registers por_el0
* info registers por
* p $por_el0
* p/x $por_el0
* set $por_el0 = <value>

The individual POE fields can also be accessed and modified through
$por_p0 to $por_p15.

Example:
(gdb) info register por_el0
por_el0        0x7                 [ P0=rwx ]
(gdb) set $por_el0=0xffffffff77777777
(gdb) info registers por_el0
por_el0        0xffffffff77777777 [ P15=??? P14=??? P13=??? P12=???
                                    P11=??? P10=??? P9=??? P8=???
                                    P7=rwx P6=rwx P5=rwx P4=rwx
                                    P3=rwx P2=rwx P1=rwx P0=rwx ]
(gdb) info registers por
por_el0        0xffffffff77777777 [ P15=??? P14=??? P13=??? P12=???
                                    P11=??? P10=??? P9=??? P8=???
                                    P7=rwx P6=rwx P5=rwx P4=rwx
                                    P3=rwx P2=rwx P1=rwx P0=rwx ]
por_p0         0x7                rwx
por_p1         0x7                rwx
por_p2         0x7                rwx
por_p3         0x7                rwx
por_p4         0x7                rwx
por_p5         0x7                rwx
por_p6         0x7                rwx
por_p7         0x7                rwx
por_p8         0xf                ???
por_p9         0xf                ???
por_p10        0xf                ???
por_p11        0xf                ???
por_p12        0xf                ???
por_p13        0xf                ???
por_p14        0xf                ???
por_p15        0xf                ???

Individual POE pseudo-registers can be written independently, with the
corresponding 4-bit field in POR_EL0 updated accordingly.  For example:

(gdb) set $por_el0=0x7
(gdb) info registers por_el0
por_el0        0x0000000000000007 [ P0=rwx ]
(gdb) set $por_p1=0x7
(gdb) info registers por_el0
por_el0        0x0000000000000077 [ P1=rwx P0=rwx ]
---
 gdb/Makefile.in              |   2 +
 gdb/aarch64-linux-nat.c      |  64 ++++++++
 gdb/aarch64-tdep.c           | 274 +++++++++++++++++++++++++++++++++++
 gdb/aarch64-tdep.h           |  12 ++
 gdb/arch/aarch64-poe-linux.h |  29 ++++
 gdb/arch/aarch64.c           |   4 +
 gdb/arch/aarch64.h           |   8 +-
 gdb/features/Makefile        |   1 +
 gdb/features/aarch64-poe.c   |  14 ++
 gdb/features/aarch64-poe.xml |  11 ++
 gdb/nat/aarch64-poe-linux.h  |  29 ++++
 11 files changed, 447 insertions(+), 1 deletion(-)
 create mode 100644 gdb/arch/aarch64-poe-linux.h
 create mode 100644 gdb/features/aarch64-poe.c
 create mode 100644 gdb/features/aarch64-poe.xml
 create mode 100644 gdb/nat/aarch64-poe-linux.h