From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id 2b0eFNPEh2qgDjMAWB0awg (envelope-from ) for ; Thu, 20 Aug 2026 23:24:03 -0400 Authentication-Results: simark.ca; dkim=pass (2048-bit key; unprotected) header.d=embedded-brains.de header.i=@embedded-brains.de header.a=rsa-sha256 header.s=34EE5404-8E36-11F0-B577-2ECCAB4968F5 header.b=XVwBrxro; dkim-atps=neutral Received: by simark.ca (Postfix, from userid 112) id 4D2571E0A3; Thu, 20 Aug 2026 23:24:03 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-25) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-5.4 required=5.0 tests=ARC_SIGNED,ARC_VALID,BAYES_00, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham autolearn_force=no version=4.0.1 Received: from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 8C66A1E09B for ; Thu, 20 Aug 2026 23:24:02 -0400 (EDT) Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2324B4BB1C3C for ; Fri, 21 Aug 2026 03:24:02 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2324B4BB1C3C Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=embedded-brains.de header.i=@embedded-brains.de header.a=rsa-sha256 header.s=34EE5404-8E36-11F0-B577-2ECCAB4968F5 header.b=XVwBrxro Received: from dedi548.your-server.de (dedi548.your-server.de [85.10.215.148]) by sourceware.org (Postfix) with ESMTPS id 6CB504BAE7FB for ; Fri, 21 Aug 2026 03:23:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6CB504BAE7FB Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embedded-brains.de Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embedded-brains.de ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 6CB504BAE7FB Authentication-Results: sourceware.org; arc=none smtp.remote-ip=85.10.215.148 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1787282606; cv=none; b=ogjQ+/YVLO8iF7z6YpEpj+Ie9SvzCW7UEKP4zqH5nIm8HYiQ+db+kQu1veo2lbVDBnc4AF9K911be3lxNZqRfsx+WrBopvxQtHVnAgP9syosYL08kvEGpZ8VCEXMXqRheLmIltH3CujSfTZtEPQqRdYqbYKL/e2pqwehSPC+bsc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1787282606; c=relaxed/simple; bh=95AZoaB4EXSNdRhCe9U0gzkqbpwXKTD1ZZJOd0qR4jE=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=fNhBVeANZ+jSHRFAY5g82sdOxUZJ5iNpAxfyH2DDTkhqqcOtR0SeskodaRVxe9jxHUETRTl5HYpPjprxtsDaf/ZAgR5SHCrkNbhYVUdoNlhZTtuLokLNsPP/keu2WFMUqoNz7pXpqrrKPwPMXWK1nAZuEKiCbrAJd1V1YX6Y0C0= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=embedded-brains.de header.i=@embedded-brains.de header.a=rsa-sha256 header.s=34EE5404-8E36-11F0-B577-2ECCAB4968F5 header.b=XVwBrxro DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6CB504BAE7FB Received: from sslproxy08.your-server.de ([78.47.166.52]) by dedi548.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96.2) (envelope-from ) id 1wxFqi-000LYD-0N; Fri, 21 Aug 2026 05:23:20 +0200 Received: from localhost ([127.0.0.1]) by sslproxy08.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1wxFqi-0005fD-2j; Fri, 21 Aug 2026 05:23:20 +0200 Received: from localhost (localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id 155B7480047; Fri, 21 Aug 2026 05:23:20 +0200 (CEST) Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavis, port 10032) with ESMTP id DbO76ZxVuiTA; Fri, 21 Aug 2026 05:23:19 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id A8C67480052; Fri, 21 Aug 2026 05:23:19 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.10.3 mail.embedded-brains.de A8C67480052 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embedded-brains.de; s=34EE5404-8E36-11F0-B577-2ECCAB4968F5; t=1787282599; bh=DMAFSv0fRWRgqyOvlVvMaAfaWXwF36RaTgfuIZh6KAI=; h=From:To:Date:Message-ID:MIME-Version; b=XVwBrxro3cbaalqRHIHJ0Gjj59/EDZ4hPJxFw8L5RmVJFoqvKjHNEvKGl4UBbgBzF lmiS7EwKVPYVbzuv+whgzCbt2cMWaOoS+WSDTThJnyB83n84JtDgP9CiKt99wNXQEC AwRkzxU24jJ3PTt/GqQIWA39eDSwn3w/YoifyHmf85OHguRD6sdloNFMqEY+rk0DTW sgMsmCuIZfbF4WQ5ecI/bPl2nw7f/I76iznm5ZhAN2tNFsns1wyMVNPTUfVd3aSodU uBvFTLXvMzKkp1HbVr7V58lQ7aHTbcOe034ie69Jgrs5BrHg+ORonoz0tboLc/zPs2 op5FM4HAlOpSQ== X-Virus-Scanned: amavis at zimbra.eb.localhost Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavis, port 10026) with ESMTP id ABDAQHo04dTq; Fri, 21 Aug 2026 05:23:19 +0200 (CEST) Received: from zimbra.eb.localhost (unknown [10.10.171.10]) by mail.embedded-brains.de (Postfix) with ESMTPSA id B2466480047; Fri, 21 Aug 2026 05:23:18 +0200 (CEST) From: Sebastian Huber To: gdb-patches@sourceware.org Cc: "Maciej W . Rozycki" , Andrew Burgess Subject: [PATCH v2 6/6] sim/mips: Recognise a software interrupt request Date: Fri, 21 Aug 2026 05:23:04 +0200 Message-ID: <20260821032304.293603-7-sebastian.huber@embedded-brains.de> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260821032304.293603-1-sebastian.huber@embedded-brains.de> References: <20260821032304.293603-1-sebastian.huber@embedded-brains.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Status: pass [(embedded-brains.de) - 78.47.166.52] X-Virus-Scanned: Clear (ClamAV 1.4.3/28098/Thu Aug 20 08:24:22 2026) X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org The simulator ignored the Cause.IP0 and Cause.IP1 software generated interrupts of the MIPS Architecture For Programmers Volume III: The MIPS Privileged Resource Architecture. A client which requested one got no exception. Check the request wherever an instruction enables the interrupts or writes a pending bit. These places are the writes to the Status and Cause registers, ERET, RFE and EI. Deliver the interrupt through the event queue and not in place, because signal_exception() leaves the handler address in the program counter for an interrupt. The simulator would overwrite it with the result of the current instruction. --- sim/mips/interp.c | 51 ++++++++++++++++++++++++++++++++++++++-- sim/mips/micromips.igen | 1 + sim/mips/mips.igen | 1 + sim/mips/mips3264r2.igen | 1 + sim/mips/sim-main.h | 2 ++ 5 files changed, 54 insertions(+), 2 deletions(-) diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 8118b290a17..4a461879804 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -321,6 +321,46 @@ interrupts_enabled (sim_cpu *cpu) return (Debug & Debug_DM) =3D=3D 0; } =20 +/* A software interrupt is requested while the interrupts are enabled an= d a + software interrupt pending bit of the Cause register meets its mask b= it in + the Status register. The Cause.IP bits meet the Status.IM bits. See= the + MIPS Architecture For Programmers Volume III: The MIPS Privileged Res= ource + Architecture, the Interrupts chapter. */ +static int +software_interrupt_requested (sim_cpu *cpu) +{ + if (!interrupts_enabled (cpu)) + return 0; + + /* Only the software interrupts. A hardware interrupt keeps its pendi= ng bit + set until its device is served. The device model delivers it. */ + return (CAUSE & SR & (cause_SW1 | cause_SW0)) !=3D 0; +} + +static void +software_interrupt_event (SIM_DESC sd, void *data) +{ + sim_cpu *cpu =3D STATE_CPU (sd, 0); + address_word cia =3D CPU_PC_GET (cpu); + + /* Check again, because the write which scheduled this event may have = been + undone in the meantime. */ + if (software_interrupt_requested (cpu)) + SignalExceptionInterrupt (0); +} + +/* Deliver a requested software interrupt at the next instruction bounda= ry. + The delivery cannot happen here: signal_exception() leaves the handle= r + address in the program counter for an interrupt and the instruction w= hich + the simulator executes would overwrite it. This is why the hardware + interrupts arrive through the event queue as well. */ +void +check_software_interrupts (SIM_DESC sd, sim_cpu *cpu) +{ + if (software_interrupt_requested (cpu)) + sim_events_schedule (sd, 1, software_interrupt_event, NULL); +} + void interrupt_event (SIM_DESC sd, void *data) { @@ -2295,14 +2335,20 @@ decode_coproc (SIM_DESC sd, if (op =3D=3D cp0_mfc0 || op =3D=3D cp0_dmfc0) GPR[rt] =3D SR; else - SR =3D GPR[rt]; + { + SR =3D GPR[rt]; + check_software_interrupts (sd, cpu); + } break; /* 13 =3D Cause R4000 VR4100 VR4300 */ case 13: if (op =3D=3D cp0_mfc0 || op =3D=3D cp0_dmfc0) GPR[rt] =3D CAUSE; else - CAUSE =3D GPR[rt]; + { + CAUSE =3D GPR[rt]; + check_software_interrupts (sd, cpu); + } break; /* 14 =3D EPC R4000 VR4100 VR4300 */ case 14: @@ -2427,6 +2473,7 @@ decode_coproc (SIM_DESC sd, =20 /* shift IE/KU history bits right */ SR =3D LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2)= , 3, 0); + check_software_interrupts (sd, cpu); =20 /* TODO: CACHE register */ #endif /* SUBTARGET_R3900 */ diff --git a/sim/mips/micromips.igen b/sim/mips/micromips.igen index 8bb48cac1e4..2149aee352f 100644 --- a/sim/mips/micromips.igen +++ b/sim/mips/micromips.igen @@ -995,6 +995,7 @@ NIA =3D EPC; SR &=3D ~status_EXL; } + check_software_interrupts (SD, CPU); } =20 =20 diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 3b52f2df43f..4becc3da31e 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -6715,6 +6715,7 @@ NIA =3D EPC; SR &=3D ~status_EXL; } + check_software_interrupts (SD, CPU); } =20 =20 diff --git a/sim/mips/mips3264r2.igen b/sim/mips/mips3264r2.igen index 67598e84433..2864d9b77de 100644 --- a/sim/mips/mips3264r2.igen +++ b/sim/mips/mips3264r2.igen @@ -94,6 +94,7 @@ TRACE_ALU_INPUT0 (); GPR[rt] =3D EXTEND32 (SR); SR |=3D status_IE; + check_software_interrupts (SD, CPU); TRACE_ALU_RESULT1 (GPR[rt]); } =20 diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index 28a4221dfd5..73a3f9c992b 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -655,6 +655,8 @@ enum ExceptionCause { =20 void interrupt_event (SIM_DESC sd, void *data); =20 +void check_software_interrupts (SIM_DESC sd, sim_cpu *cpu); + void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int = exception, ...); #define SignalException(exc,instruction) signal_exception (SD, CPU, = cia, (exc), (instruction)) #define SignalExceptionInterrupt(level) signal_exception (SD, CPU, = cia, Interrupt, level) --=20 2.51.0