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Rozycki" , Andrew Burgess Subject: [PATCH v2 5/6] sim/mips: Keep the pending interrupts in Cause Date: Fri, 21 Aug 2026 05:23:03 +0200 Message-ID: <20260821032304.293603-6-sebastian.huber@embedded-brains.de> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260821032304.293603-1-sebastian.huber@embedded-brains.de> References: <20260821032304.293603-1-sebastian.huber@embedded-brains.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Status: pass [(embedded-brains.de) - 78.47.166.52] X-Virus-Scanned: Clear (ClamAV 1.4.3/28098/Thu Aug 20 08:24:22 2026) X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org signal_exception() assigned the whole Cause register. It discarded the interrupt pending field, so the handler of an interrupt read Cause.IP as zero. The handler could not tell which interrupt the processor delivered. The R3900 path keeps the field already. Keep the interrupt pending field on the other targets as well. Add cause_IPALL_mask for the complete field, because cause_IP_mask covers only the six hardware interrupts. --- sim/mips/interp.c | 4 ++-- sim/mips/sim-main.h | 4 ++++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/sim/mips/interp.c b/sim/mips/interp.c index dc918bb9281..8118b290a17 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -1962,7 +1962,7 @@ signal_exception (SIM_DESC sd, /* See figure 5-17 for an outline of the code below */ if (! (SR & status_EXL)) { - CAUSE =3D (exception << 2); + CAUSE =3D (CAUSE & cause_IPALL_mask) | (exception << 2); if (STATE & simDELAYSLOT) { STATE &=3D ~simDELAYSLOT; @@ -1976,7 +1976,7 @@ signal_exception (SIM_DESC sd, } else { - CAUSE =3D (exception << 2); + CAUSE =3D (CAUSE & cause_IPALL_mask) | (exception << 2); /* vector =3D 0x180; */ } SR |=3D status_EXL; diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index b6cb4e12258..28a4221dfd5 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -557,6 +557,10 @@ struct mips_sim_state { #define cause_SW1 (1 << 9) /* Software interrupt 1 */ #define cause_IP_mask (0x3f) /* Interrupt pending field */ #define cause_IP_shift (10) +/* The complete interrupt pending field, IP7:IP0. Its bits meet the + Status.IM bits. */ +#define cause_IPALL_mask ((cause_IP_mask << cause_IP_shift) \ + | cause_SW1 | cause_SW0) =20 #define cause_set_EXC(x) CAUSE =3D (CAUSE & ~cause_EXC_mask) | ((x << = cause_EXC_shift) & cause_EXC_mask) #define cause_set_EXC2(x) CAUSE =3D (CAUSE & ~cause_EXC2_mask) | ((x << = cause_EXC2_shift) & cause_EXC2_mask) --=20 2.51.0