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Rozycki" , Andrew Burgess Subject: [PATCH v2 4/6] sim/mips: Check all interrupt enable conditions Date: Fri, 21 Aug 2026 05:23:02 +0200 Message-ID: <20260821032304.293603-5-sebastian.huber@embedded-brains.de> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260821032304.293603-1-sebastian.huber@embedded-brains.de> References: <20260821032304.293603-1-sebastian.huber@embedded-brains.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Status: pass [(embedded-brains.de) - 78.47.166.52] X-Virus-Scanned: Clear (ClamAV 1.4.3/28098/Thu Aug 20 08:24:22 2026) X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org interrupt_event() tested Status.IE alone. On a target with an exception level it delivered an interrupt while Status.EXL was set. The simulator entered the exception handler again through the vector and left EPC at the address of the older exception. The handler lost its resume point. The test also let an interrupt through in debug mode. Collect the conditions which enable an interrupt in interrupts_enabled(). Use this function for the delivery. --- sim/mips/interp.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 5dbd1482b99..dc918bb9281 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -295,12 +295,38 @@ static const OPTION mips_options[] =3D =20 int interrupt_pending; =20 +/* The interrupts are enabled while the Status register enables them and= the + processor is at no exception level, at no error level and not in debu= g + mode: + + Status.IE =3D 1, Status.EXL =3D 0, Status.ERL =3D 0, Debug.DM =3D 0 + + MIPS Architecture For Programmers Volume III: The MIPS Privileged Res= ource + Architecture, the Interrupts chapter. The R3000 generation, which th= e + R3900 belongs to, has no exception level and no error level. It disa= bles + the interrupts through the interrupt enable stack of its Status regis= ter, + so only the current enable takes part. See the IDT R30xx Family Soft= ware + Reference Manual, the Status register of the CPU control chapter. */ +static int +interrupts_enabled (sim_cpu *cpu) +{ + if ((SR & status_IE) =3D=3D 0) + return 0; + +#ifndef SUBTARGET_R3900 + if ((SR & (status_EXL | status_ERL)) !=3D 0) + return 0; +#endif + + return (Debug & Debug_DM) =3D=3D 0; +} + void interrupt_event (SIM_DESC sd, void *data) { sim_cpu *cpu =3D STATE_CPU (sd, 0); /* FIXME */ address_word cia =3D CPU_PC_GET (cpu); - if (SR & status_IE) + if (interrupts_enabled (cpu)) { interrupt_pending =3D 0; SignalExceptionInterrupt (1); /* interrupt "1" */ --=20 2.51.0