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b=qKWsqoEQTt6RFXPdw58IEvGC+OyRq7LKnPsbhNrqO4XklrsaehyK+esURljXP1MrA ot822QpWqCQG2nNl6zEy/ZjZANn6MB37hRGh0Uwreor2u94xiELwfZfro0Y6VOB4Fl GFm8DvCF1lAxfB8jaYDIXSfzUMBbmF0PJun6mbLd/b426suTgYLl7QzZxBk6Swq+fs KT9ZirX9e0n81hxZexKyXeFx0M63neB4JsfvSNwLJd0ZWSF7yObWipBVWL3zItmS7z ldC7jVkykXawWkm10qCcHnWsxH+90GHYLvQVCUF+W6w4t8WZBLHYFge1LBdgdkSFw1 c1F22K96pEWyQ== X-Virus-Scanned: amavis at zimbra.eb.localhost Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavis, port 10026) with ESMTP id ymQ8VwYcJh8D; Fri, 21 Aug 2026 05:23:15 +0200 (CEST) Received: from zimbra.eb.localhost (unknown [10.10.171.10]) by mail.embedded-brains.de (Postfix) with ESMTPSA id 0DAA7480047; Fri, 21 Aug 2026 05:23:14 +0200 (CEST) From: Sebastian Huber To: gdb-patches@sourceware.org Cc: "Maciej W . Rozycki" , Andrew Burgess Subject: [PATCH v2 3/6] sim/mips: Deliver the reserved instruction exception Date: Fri, 21 Aug 2026 05:23:01 +0200 Message-ID: <20260821032304.293603-4-sebastian.huber@embedded-brains.de> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260821032304.293603-1-sebastian.huber@embedded-brains.de> References: <20260821032304.293603-1-sebastian.huber@embedded-brains.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Status: pass [(embedded-brains.de) - 78.47.166.52] X-Virus-Scanned: Clear (ClamAV 1.4.3/28098/Thu Aug 20 08:24:22 2026) X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org The ReservedInstruction and CoProcessorUnusable cases of signal_exception() compute CAUSE, SR and EPC and set PC to the exception handler address, and then assign PC =3D EPC, which discards all of it. The client resumes on the faulting instruction rather than in its handler, so it raises the same exception again and never advances. The address error cases immediately above deliberately do not do this and say so in a comment. The consequence is that a target which handles the exception never runs. A compiler emits rdhwr to read the thread pointer for every access to a thread-local object on every MIPS target, because the instruction exists since MIPS32r2 and the operating system is expected to emulate it where the processor lacks it. The R3900 lacks it. Approved-By: Andrew Burgess --- sim/mips/interp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sim/mips/interp.c b/sim/mips/interp.c index a2757ec5ef7..5dbd1482b99 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -1992,7 +1992,8 @@ signal_exception (SIM_DESC sd, =20 case ReservedInstruction: case CoProcessorUnusable: - PC =3D EPC; + /* Leave PC at the exception handler address. This allows emulating + an instruction the CPU lacks. */ sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGILL); =20 --=20 2.51.0