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b=cJfEqzb4fMABN6nDltJ0l15ZB9DVY9JN1knmlFQAVd95OgzpxLpPyVKgy4I/aVbxm jgWl74LmxcFxEASq3fdHfzB6+12GnrBbeekCxnEoAuPWKGvG1+KnrbjX5pZjErpQM7 AjR3dNGNmADzymC7nA75o3dtAkdaBzCMfWXnQW42/3MeHI9kziRbWZc19tKXL8eQBM 80PaWXf1aS22YyZ4GjcNyzMZJjKMKoJILTbnQ5tyESdj5/wHBCor/r2LkcQJL/fVHT UrmI1DHBHOcpDLzGhk+CbuBncfoJ6nE+eIQWyXBnTQcS77OZCUFLorHmtZyt8egrvC 5u8Wq+7lqB07g== X-Virus-Scanned: amavis at zimbra.eb.localhost Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavis, port 10026) with ESMTP id H1KrT8oT64Lp; Fri, 21 Aug 2026 05:23:12 +0200 (CEST) Received: from zimbra.eb.localhost (unknown [10.10.171.10]) by mail.embedded-brains.de (Postfix) with ESMTPSA id 575F5480047; Fri, 21 Aug 2026 05:23:11 +0200 (CEST) From: Sebastian Huber To: gdb-patches@sourceware.org Cc: "Maciej W . Rozycki" , Andrew Burgess Subject: [PATCH v2 0/6] sim: Fix MIPS livelocks and add software interrupts Date: Fri, 21 Aug 2026 05:22:58 +0200 Message-ID: <20260821032304.293603-1-sebastian.huber@embedded-brains.de> X-Mailer: git-send-email 2.51.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Status: pass [(embedded-brains.de) - 78.47.166.52] X-Virus-Scanned: Clear (ClamAV 1.4.3/28098/Thu Aug 20 08:24:22 2026) X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org The MIPS simulator cannot run an operating system on the jmr3904 board. Three defects stop the client. An event handler which deschedules an overdue event trips an assertion. A HI/LO hazard aborts the run loop and the client resumes on the same instruction. The reserved instruction exception discards the handler address, so a client which emulates rdhwr makes no progress. The simulator also lacks the Cause.IP0 and Cause.IP1 software generated interrupts of the MIPS Privileged Resource Architecture. A client which requests one gets no exception. Patches 4 and 5 prepare the interrupt delivery for patch 6. Patches 1 to 3 are unchanged and carry their Approved-By tag. Changes since v1: - Patch 4 is new. interrupt_event() tested Status.IE alone. On a target with an exception level it delivered a watch interrupt while Status.EXL was set. The simulator re-entered the exception handler from the vector and the handler lost its resume point. The patch gathers the enable conditions in interrupts_enabled() and gives both places the same test. The test covers Debug.DM, as the review asked. - Patch 5 is new. signal_exception() assigned the whole Cause register on every target except the R3900, which discarded the pending interrupt bits. The handler of a software interrupt read Cause.IP as zero and could not tell the source. The patch keeps the pending field. - interrupt_requested() becomes software_interrupt_requested() and check_interrupts() becomes check_software_interrupts(), as the review asked. The second function loses its static linkage, because the instruction descriptions call it. - The call after the ERET emulation of decode_coproc() is gone. No caller passes cp0_eret or cp0_deret to decode_coproc(), so both arms are dead code and the call never ran. The live ERET emulation sits in mips.igen and micromips.igen, and the call goes there. - The EI instruction of mips3264r2.igen sets Status.IE, so it calls check_software_interrupts() as well. - cause_IPSW_mask and cause_IPSW_shift are gone. The existing cause_SW0 and cause_SW1 name the same two bits. Status.IM and Cause.IP share bits 15:8, so the test needs no shift. The new cause_IPALL_mask covers the whole pending field for patch 5. The following points of the review stay open: - DERET calls no check. The micromips DERET body is empty and mips.igen has no DERET encoding, so the series has nothing to hook. - Only the dead DERET arm clears Debug.DM. After an sdbbp the new test blocks every interrupt for the rest of the run. - interrupt_pending receives no non-zero value anywhere in the tree. I leave it alone. - ErrorEPC and Status.ERL keep their present state. - The series carries no test. sim/testsuite/mips installs no exception vector and has no linker script for one. Sebastian Huber (6): sim: Allow an overdue event to be descheduled sim/mips: Do not abort on a HI/LO hazard sim/mips: Deliver the reserved instruction exception sim/mips: Check all interrupt enable conditions sim/mips: Keep the pending interrupts in Cause sim/mips: Recognise a software interrupt request sim/common/sim-events.c | 6 ++- sim/mips/interp.c | 86 +++++++++++++++++++++++++++++++++++++--- sim/mips/micromips.igen | 1 + sim/mips/mips.igen | 26 +++++++++--- sim/mips/mips3264r2.igen | 1 + sim/mips/sim-main.h | 6 +++ 6 files changed, 113 insertions(+), 13 deletions(-) --=20 2.51.0