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h=From:To:Date:Message-ID:MIME-Version; b=AuRng0gXVVOer/AkomFYPAVpeAAWd2OSYps0ein4tNNBX44Wci0sFGFonSGi88iIV V3i4yaYOPtwy2D5tB3Cv5Bd9cOxXEKc5Ph1v09TB9rEBA4iHg4Af3KaldROGiNH5GT 2aU/6+G3PRdFuJccKW9KCN77qik/nXvfepxVATeRxkXUJE/LYzfqoajm+qiyeZ2QkK BbBLenuBFuH7OIyv9ZUDCZHpwVygksdUtZwFNisVgCw95ywvKXBnXgm1aWUQtPj8/I NEODJV3HfSZA2+h3A7fWp2Ak39iksdlDwJJmZArMQIh+7bNUK+kmbkbcsS5DS6ro8y mfjxy00Ty8HIA== X-Virus-Scanned: amavis at zimbra.eb.localhost Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavis, port 10026) with ESMTP id jv0RHqqg3WcP for ; Mon, 17 Aug 2026 01:44:07 +0200 (CEST) Received: from zimbra.eb.localhost (unknown [10.10.171.14]) by mail.embedded-brains.de (Postfix) with ESMTPSA id 307D7480074 for ; Mon, 17 Aug 2026 01:44:07 +0200 (CEST) From: Sebastian Huber To: gdb-patches@sourceware.org Subject: [PATCH 4/4] sim/mips: Recognise a software interrupt request Date: Mon, 17 Aug 2026 01:43:56 +0200 Message-ID: <20260816234357.278358-5-sebastian.huber@embedded-brains.de> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260816234357.278358-1-sebastian.huber@embedded-brains.de> References: <20260816234357.278358-1-sebastian.huber@embedded-brains.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Status: pass [(embedded-brains.de) - 78.46.172.3] X-Virus-Scanned: Clear (ClamAV 1.4.3/28094/Sun Aug 16 08:26:19 2026) X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org Add support for the Cause.IP0 and Cause.IP1 software generated interrupts defined by the MIPS Architecture For Programmers Volume III: The MIPS Privileged Resource Architecture. Deliver it from the event queue rather than in place, because signal_exception() leaves the handler address in the program counter for an interrupt and the instruction being executed would overwrite it. Signed-off-by: Sebastian Huber --- sim/mips/interp.c | 64 +++++++++++++++++++++++++++++++++++++++++++-- sim/mips/sim-main.h | 2 ++ 2 files changed, 64 insertions(+), 2 deletions(-) diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 5dbd1482b99..fddb96d00ed 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -295,6 +295,58 @@ static const OPTION mips_options[] =3D =20 int interrupt_pending; =20 +/* An interrupt is requested while the interrupts are enabled and a pend= ing + bit of the Cause register meets its mask bit in the Status register: + + Status.IE =3D 1, Status.EXL =3D 0, Status.ERL =3D 0, Cause.IP & Sta= tus.IM !=3D 0 + + MIPS Architecture For Programmers Volume III: The MIPS Privileged Res= ource + Architecture, the Interrupts chapter. The R3000 generation, which th= e + R3900 belongs to, has no exception level and disables the interrupts = by + shifting the interrupt enable stack of its Status register instead, s= o only + the current enable takes part; see the IDT R30xx Family Software Refe= rence + Manual, the Status register of the CPU control chapter. */ +static int +interrupt_requested (sim_cpu *cpu) +{ + if ((SR & status_IE) =3D=3D 0) + return 0; + +#ifndef SUBTARGET_R3900 + if ((SR & (status_EXL | status_ERL)) !=3D 0) + return 0; +#endif + + /* Only the software interrupts. A hardware interrupt keeps its pendi= ng bit + set until its device is served. The device model delivers it. */ + return ((CAUSE >> cause_IPSW_shift) & (SR >> status_IM_shift) + & cause_IPSW_mask) !=3D 0; +} + +static void +software_interrupt_event (SIM_DESC sd, void *data) +{ + sim_cpu *cpu =3D STATE_CPU (sd, 0); + address_word cia =3D CPU_PC_GET (cpu); + + /* Recheck, because the write which scheduled this may have been undon= e in + the meantime. */ + if (interrupt_requested (cpu)) + SignalExceptionInterrupt (0); +} + +/* Deliver a pending interrupt at the next instruction boundary. It can= not be + delivered here: signal_exception() leaves the handler address in the = program + counter for an interrupt and the instruction which is being executed = would + overwrite it. This is why the hardware interrupts arrive through the= event + queue as well. */ +static void +check_interrupts (SIM_DESC sd, sim_cpu *cpu) +{ + if (interrupt_requested (cpu)) + sim_events_schedule (sd, 1, software_interrupt_event, NULL); +} + void interrupt_event (SIM_DESC sd, void *data) { @@ -2269,14 +2321,20 @@ decode_coproc (SIM_DESC sd, if (op =3D=3D cp0_mfc0 || op =3D=3D cp0_dmfc0) GPR[rt] =3D SR; else - SR =3D GPR[rt]; + { + SR =3D GPR[rt]; + check_interrupts (sd, cpu); + } break; /* 13 =3D Cause R4000 VR4100 VR4300 */ case 13: if (op =3D=3D cp0_mfc0 || op =3D=3D cp0_dmfc0) GPR[rt] =3D CAUSE; else - CAUSE =3D GPR[rt]; + { + CAUSE =3D GPR[rt]; + check_interrupts (sd, cpu); + } break; /* 14 =3D EPC R4000 VR4100 VR4300 */ case 14: @@ -2391,6 +2449,7 @@ decode_coproc (SIM_DESC sd, { PC =3D EPC; SR &=3D ~status_EXL; + check_interrupts (sd, cpu); } } else if (op =3D=3D cp0_rfe && sel =3D=3D 0x10) @@ -2401,6 +2460,7 @@ decode_coproc (SIM_DESC sd, =20 /* shift IE/KU history bits right */ SR =3D LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2)= , 3, 0); + check_interrupts (sd, cpu); =20 /* TODO: CACHE register */ #endif /* SUBTARGET_R3900 */ diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index b6cb4e12258..3af02e49c0e 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -557,6 +557,8 @@ struct mips_sim_state { #define cause_SW1 (1 << 9) /* Software interrupt 1 */ #define cause_IP_mask (0x3f) /* Interrupt pending field */ #define cause_IP_shift (10) +#define cause_IPSW_mask (0x3) /* Software interrupt pending, I= P1:IP0 */ +#define cause_IPSW_shift (8) =20 #define cause_set_EXC(x) CAUSE =3D (CAUSE & ~cause_EXC_mask) | ((x << = cause_EXC_shift) & cause_EXC_mask) #define cause_set_EXC2(x) CAUSE =3D (CAUSE & ~cause_EXC2_mask) | ((x << = cause_EXC2_shift) & cause_EXC2_mask) --=20 2.51.0