From: Guinevere Larsen <guinevere@redhat.com>
To: gdb-patches@sourceware.org
Cc: Guinevere Larsen <guinevere@redhat.com>
Subject: [PATCH 1/2] gdb/record: Add support for recording BMI1 instructions
Date: Wed, 17 Jun 2026 11:00:57 -0300 [thread overview]
Message-ID: <20260617140058.20727-2-guinevere@redhat.com> (raw)
In-Reply-To: <20260617124201.15794-1-guinevere@redhat.com>
This commit adds support for recording all instructions of the Bit
Manipulation Instruction set 1, for x86 cpus. The specific instructions
are:
* andn
* bls[i|r|msk]
* bextr
* [l|t]zcnt
Also add them to the avx test. While BMI is a different set of
instructions, there are no currently existing CPUs that have access to
AVX2 and don't have access to BMI1 and BMI2, so it seems like a
reasonable idea to keep them together, as the avx test already requires
AVX2.
---
gdb/i386-tdep.c | 48 +++++++++++++++----
gdb/testsuite/gdb.reverse/i386-avx-reverse.c | 38 +++++++++++++++
.../gdb.reverse/i386-avx-reverse.exp | 41 ++++++++++++++++
3 files changed, 117 insertions(+), 10 deletions(-)
diff --git a/gdb/i386-tdep.c b/gdb/i386-tdep.c
index a19d774841c..8b4dfb43f61 100644
--- a/gdb/i386-tdep.c
+++ b/gdb/i386-tdep.c
@@ -5125,25 +5125,52 @@ i386_record_vex (struct i386_record_s *ir, uint8_t vex_w, uint8_t vex_r,
case 0xe5: /* VPMULHW */
case 0xe6: /* VCVTDQ2PD, VCVTTPD2DQ and VCVTPD2DQ. */
case 0xf1: /* VPSLLW, dynamic shift. */
- case 0xf2: /* VPSLLD, dynamic shift. */
- case 0xf3: /* VPSLLQ, dynamic shift. */
+ case 0xf2: /* VPSLLD, dynamic shift and ANDN. */
+ case 0xf3: /* VPSLLQ, dynamic shift and BLSI, BLSR and BLSMSK. */
case 0xf4: /* VPMULUDQ */
case 0xf6: /* VPSADBW. */
case 0xfc: /* VPADDB */
case 0xfd: /* VPADDW */
case 0xfe: /* VPADDD */
{
- /* This set of instructions all share the same exact way to encode
- the destination register, so there's no reason to try and
- differentiate them. */
i386_record_modrm (ir);
int reg_offset = ir->reg + vex_r * 8;
- gdb_assert (tdep->num_ymm_regs > reg_offset);
- record_full_arch_list_add_reg (ir->regcache,
- tdep->ymm0_regnum + reg_offset);
+ if (opcode == 0xf2 && ir->map_select == 2) /* ANDN. */
+ {
+ record_full_arch_list_add_reg (ir->regcache,
+ ir->regmap[X86_RECORD_REAX_REGNUM
+ + reg_offset]);
+ record_full_arch_list_add_reg
+ (ir->regcache, ir->regmap[X86_RECORD_EFLAGS_REGNUM]);
+ }
+ else if (opcode == 0xf3 && ir->map_select == 2)
+ {
+ /* BLSI, BLSR and BLSMSK. */
+ record_full_arch_list_add_reg (ir->regcache,
+ ir->regmap[X86_RECORD_REAX_REGNUM
+ + ir->vvvv]);
+ record_full_arch_list_add_reg
+ (ir->regcache, ir->regmap[X86_RECORD_EFLAGS_REGNUM]);
+ }
+ else
+ {
+ /* This set of instructions all share the same exact way to
+ encode the destination register, so there's no reason to
+ try and differentiate them. */
+ gdb_assert (tdep->num_ymm_regs > reg_offset);
+ record_full_arch_list_add_reg (ir->regcache,
+ tdep->ymm0_regnum + reg_offset);
+ }
}
break;
+ case 0xf7: /* BEXTR. */
+ i386_record_modrm (ir);
+ record_full_arch_list_add_reg (ir->regcache,
+ ir->regmap[X86_RECORD_REAX_REGNUM
+ + ir->reg + vex_r * 8]);
+ break;
+
case 0x2e: /* VUCOMIS[S|D]. */
case 0x2f: /* VCOMIS[S|D]. */
{
@@ -7031,8 +7058,9 @@ Do you want to stop the program?"),
I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
break;
- case 0x0fbc: /* bsf */
- case 0x0fbd: /* bsr */
+ case 0x0fbc: /* bsf and tzcnt. */
+ case 0x0fbd: /* bsr and lzcnt. */
+ i386_record_modrm (&ir);
I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
break;
diff --git a/gdb/testsuite/gdb.reverse/i386-avx-reverse.c b/gdb/testsuite/gdb.reverse/i386-avx-reverse.c
index cfbd77c8992..190bc6f4a7a 100644
--- a/gdb/testsuite/gdb.reverse/i386-avx-reverse.c
+++ b/gdb/testsuite/gdb.reverse/i386-avx-reverse.c
@@ -765,6 +765,43 @@ convert_test ()
return 0; /* end convert_test */
}
+int
+bmi_test ()
+{
+ /* start bmi_test. */
+ /* Using GDB, load these values onto registers for testing.
+ eax = 0x1312
+ ebx = 0xdeadbeef
+ ecx = 0xcafeface
+ r8 = 0
+ this way it's easy to confirm we're undoing things correctly. */
+
+ asm volatile ("andn %rbx, %rax, %r8");
+ asm volatile ("andn %ebx, %eax, %ecx");
+
+ asm volatile ("bextr %rcx, %r8, %rbx");
+ asm volatile ("bextr %ebx, %ecx, %r8d");
+
+ asm volatile ("blsi %rax, %rcx");
+ asm volatile ("blsi %ebx, %r8d");
+
+ asm volatile ("blsmsk %r8, %rbx");
+ asm volatile ("blsmsk %eax, %eax");
+
+ asm volatile ("blsr %rcx, %rbx");
+ asm volatile ("blsr %r8d, %ecx");
+
+ asm volatile ("lzcnt %rax, %r8");
+ asm volatile ("lzcnt %eax, %ecx");
+ asm volatile ("lzcnt %ax, %bx");
+
+ asm volatile ("tzcnt %rax, %rcx");
+ asm volatile ("tzcnt %eax, %ebx");
+ asm volatile ("tzcnt %ax, %r8w");
+
+ return 0; /* end bmi_test */
+}
+
/* This include is used to allocate the dynamic buffer and have
the pointers aligned to a 32-bit boundary, so we can test instructions
that require aligned memory. */
@@ -806,5 +843,6 @@ main ()
compare_test ();
pack_test ();
convert_test ();
+ bmi_test ();
return 0; /* end of main */
}
diff --git a/gdb/testsuite/gdb.reverse/i386-avx-reverse.exp b/gdb/testsuite/gdb.reverse/i386-avx-reverse.exp
index 2268f2c2872..e1780267ad0 100644
--- a/gdb/testsuite/gdb.reverse/i386-avx-reverse.exp
+++ b/gdb/testsuite/gdb.reverse/i386-avx-reverse.exp
@@ -23,6 +23,8 @@
require supports_reverse
require have_avx
require have_avx2
+# This test also requires BMI1 support. All real hardware in existence
+# that supports AVX2 also supports those though, so we don't check it.
# TODO: this is the case because I used xmm15 all over the test.
# Some parts of the test require xmm15 to validate some code paths, but
@@ -1195,3 +1197,42 @@ if {[record_full_function "convert"] == true} {
}
gdb_test "finish" "Run till exit from.*convert_test.*" \
"leaving convert"
+
+
+# Preparation and testing BMI instructions.
+gdb_test_no_output \
+ "set \$r8 = 0" "set r8 for bmi test"
+gdb_test_no_output \
+ "set \$eax = 0x1312" "set eax for bmi test"
+gdb_test_no_output "set \$ebx = 0xdeadbeef" "set ebx for bmi test"
+gdb_test_no_output "set \$ecx = 0xcafeface" "set ecx for bmi test"
+
+if {[record_full_function "bmi"] == true} {
+
+ test_one_general_register "tzcnt" "r8" "0x3e"
+ test_one_general_register "tzcnt" "ebx" "0xe"
+ test_one_general_register "tzcnt" "ecx" "0x1e"
+
+ test_one_general_register "lzcnt" "ebx" "0x0"
+ test_one_general_register "lzcnt" "ecx" "0x0"
+ test_one_general_register "lzcnt" "r8" "0x0"
+
+ test_one_general_register "blsr" "ecx" "0x2"
+ test_one_general_register "blsr" "ebx" "0xffffffff"
+
+ test_one_general_register "blsmsk" "eax" "0x1312"
+ test_one_general_register "blsmsk" "ebx" "0x0"
+
+ test_one_general_register "blsi" "r8" "0x0"
+ test_one_general_register "blsi" "ecx" "0xdeadaced"
+
+ test_one_general_register "bextr" "eax" "0x1312"
+ test_one_general_register "bextr" "ebx" "0xdeadbeef"
+
+ test_one_general_register "andn" "ecx" "0xcafeface"
+ test_one_general_register "andn" "r8" "0x0"
+} else {
+ untested "couldn't run bmi tests"
+}
+gdb_test "finish" "Run till exit from.*bmi_test.*" \
+ "leaving bmi"
--
2.54.0
next prev parent reply other threads:[~2026-06-17 14:01 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-17 12:41 [PATCH 0/2] Add support for BMI1 and BMI2 recording Guinevere Larsen
2026-06-17 14:00 ` Guinevere Larsen [this message]
2026-06-17 14:00 ` [PATCH 2/2] gdb/record: add support for BMI2 instructions Guinevere Larsen
2026-07-03 18:22 ` Guinevere Larsen
2026-07-07 9:18 ` Schimpe, Christina
2026-07-07 13:57 ` Guinevere Larsen
2026-07-09 13:19 ` Schimpe, Christina
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