From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id m263CuUCGmj9PhcAWB0awg (envelope-from ) for ; Tue, 06 May 2025 08:39:01 -0400 Authentication-Results: simark.ca; dkim=pass (2048-bit key; unprotected) header.d=whileone-in.20230601.gappssmtp.com header.i=@whileone-in.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=tipJ68Ob; dkim-atps=neutral Received: by simark.ca (Postfix, from userid 112) id 1366F1E10E; Tue, 6 May 2025 08:39:01 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-25) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-9.0 required=5.0 tests=ARC_SIGNED,ARC_VALID,BAYES_00, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, RCVD_IN_VALIDITY_CERTIFIED,RCVD_IN_VALIDITY_RPBL,RCVD_IN_VALIDITY_SAFE autolearn=ham autolearn_force=no version=4.0.1 Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 4E2EC1E092 for ; Tue, 6 May 2025 08:38:58 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CE9C1385C6FF for ; Tue, 6 May 2025 12:38:57 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CE9C1385C6FF Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=whileone-in.20230601.gappssmtp.com header.i=@whileone-in.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=tipJ68Ob Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by sourceware.org (Postfix) with ESMTPS id 9A631385C6F0 for ; Tue, 6 May 2025 12:38:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9A631385C6F0 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=whileone.in Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=whileone.in ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 9A631385C6F0 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::62b ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1746535097; cv=none; b=DWoqtmz+sJK3OuCDQHSAWSvagg774j6/caj1uiGEu63d2cMY8x4SqwaARn+jpXRNnSPBYm0BoU82EyRZGUtqgleIHO4mb9jZF7GC1J2r3miU8lOTnRceTPt7fVnRN95WU/B80ttEyQqWaKjRMOVoNtfRNkG+Nomm89TnnthsIko= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1746535097; c=relaxed/simple; bh=g4yulChjX3QF/Fw8Nzwki8rBatJQnsmkPnIULRttNts=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=Xc1V+/KBPZHKTbFKiAxKhulUwfF9psCZYso4fafZ/k4tlr/AQIBJ7R04SRIbAh9a6UYu/EkJlztibf6z/37J1XZnQ1/ijG/ssROcgyFB89rBAnmkhR8lLunhMstihDQEpK4Dtmteg0FlyhbSzjUjpPgSm1/cLmVpA6APmS+S1o0= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9A631385C6F0 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-223f4c06e9fso51273465ad.1 for ; Tue, 06 May 2025 05:38:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=whileone-in.20230601.gappssmtp.com; s=20230601; t=1746535095; x=1747139895; darn=sourceware.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=f8ybDxRBgzuvsWNIyEnmV8FMRKq5Ply4k6ODZl2ixek=; b=tipJ68ObBiyuZjbBw7JqXNJECBcpDAaIQCVXTMaiAgDDxh1Cu6pq+2uCTQy7kShKNo d+vHucH8cjjCQuEjBXrEkhhJx2bVmf38S/hX+BViaUXaukQk9w40jKP1L67GHksKbznt 3q+JKHzIW2G/I80mFbClZZ6Mh6gqq0XqK8BSXbdjpKmcBR45uDqKtoQiVpmBaC68r42q zAMe7jR7JMQADE8h0mYxyaO1Ntm6t5+aQAbEGhLzCB0PTTmtJI8s6z9Xfw9PFSsO9VPt MCrcW7ZYKfwGoM6h82Wsa8C7fI8PIN+OckqHTfDhv5v8s5Fj6MbWcs1zDYfK9JOQIGdT p+nA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746535095; x=1747139895; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=f8ybDxRBgzuvsWNIyEnmV8FMRKq5Ply4k6ODZl2ixek=; b=QGKGQfXhFa/XR3+ob7e9VO/CzYwAHvLRqhgvmpodCfjmjQP+yaMNd4yW6igpwbd59q tLqhZ8CxTW+Cm8GTgVLy+1KiyCbiiaZkH1juyOTJQDUT3d/qiP8rljJjVmbn7bMUUxly 96pgC1i5uL0y9l/LLLMiBWgrzDeiUD2hnYidJOy4UyO1slpsaesz8NlAaRNJuE3LSmt5 03/MCWsUQrtkjUk3DH57aN/4E6XUHoOVMzwVXmg+ZW73Hcqa3vJuG5XFVpMxcLpwQh8R QyI5kXbaTZa+eG9qC3Iaiwtt0af/VR5ag3IUoRFgafujSfng79S9RVDeBwPEya80g1ST w+5A== X-Gm-Message-State: AOJu0YwCwmpfdpteHzH15qB1vC1xuXemwnbQ9ZmWH6n/u34WDYE/SjMc jBiSEUtlVqfM99jdfmPzjOlwrA/4iQLOHzzW03cG9TjtjkA/URmzaWmCOWjp5UQeE0JHduDlKxA s X-Gm-Gg: ASbGncspGJdJMFXRXhISDI4ppMg1IDfA71zmhZWjJvy/sF7jFsFx729nkTXphgP5t9V 44U3eA9ZuSFSf3Ac2bfN0Ig4+r5TZ3jqWiE/iKaaj0xLaUUdil5UCQzrp9vVXc7YBkDSQMeDzDr Mtqr2DKFap9CsuPiDhNF4neadOIJZH9NFpZoIE/0ZMzfVYAMW/rOqwCS9mKFHL24Nf8+q2ob/Ic f2y9kEyeYecoat0p7eZHNUzJgcTmxfpfDb0QHsA6xjPSkhHhkUOnd5CzkJC6iglZ/30mFc2MCV5 9+p4rGOpTBs= X-Google-Smtp-Source: AGHT+IGnEbVxJtc6+yvDm3sjBlD+owWBxXHm+Dw+hEDH0Yfn1uZrsKzTSnxPzUuoSuOZlfn/dLckvA== X-Received: by 2002:a17:902:d486:b0:215:58be:334e with SMTP id d9443c01a7336-22e32776bf1mr44226815ad.10.1746535094947; Tue, 06 May 2025 05:38:14 -0700 (PDT) Received: from ubuntu.. ([122.170.108.66]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22e169667dbsm67991715ad.22.2025.05.06.05.38.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 May 2025 05:38:14 -0700 (PDT) From: Sameer Natu X-Google-Original-From: Sameer Natu To: gdb-patches@sourceware.org Cc: Sameer Natu , Greg Savin Subject: [PATCH v4] RISC-V: support for vector register accesses via ptrace() in RISC-V Linux native Date: Tue, 6 May 2025 12:37:09 +0000 Message-ID: <20250506123711.2243088-2-snatu@whileone.in> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org From: Sameer Natu A v4 re-spin of the original patch. Tested with latest kernel 6.14.2 on RISCV QEMU. Removed Magic Numbers from v2 patch and worked on review comments of v2 patch. Co-Authored-By: Greg Savin --- gdb/arch/riscv.c | 180 ++++++++++++++++++++++++++++++++++- gdb/nat/riscv-linux-tdesc.c | 68 +++++++++++++ gdb/nat/riscv-linux-tdesc.h | 24 +++++ gdb/riscv-linux-nat.c | 162 +++++++++++++++++++++++++++++++ gdb/riscv-linux-tdep.c | 133 ++++++++++++++++++++++++++ gdb/riscv-tdep.c | 49 +++++++++- gdb/riscv-tdep.h | 6 ++ gdbserver/linux-riscv-low.cc | 110 +++++++++++++++++++++ include/elf/common.h | 1 + 9 files changed, 726 insertions(+), 7 deletions(-) diff --git a/gdb/arch/riscv.c b/gdb/arch/riscv.c index a6188ea3a8c..f1f5d83d60a 100644 --- a/gdb/arch/riscv.c +++ b/gdb/arch/riscv.c @@ -25,12 +25,30 @@ #include "../features/riscv/64bit-fpu.c" #include "../features/riscv/rv32e-xregs.c" +#include "opcode/riscv-opc.h" + #ifndef GDBSERVER #define STATIC_IN_GDB static #else #define STATIC_IN_GDB #endif +#ifdef GDBSERVER +/* Work around issue where trying to include riscv-tdep.h (to get access to canonical RISCV_V0_REGNUM declaration + from that header) is problamtic for gdbserver build. */ +#define RISCV_V0_REGNUM 4162 +#else +#include "riscv-tdep.h" +#include "defs.h" +#endif + +static int +create_feature_riscv_vector_from_features (struct target_desc *result, + long regnum, + const struct riscv_gdbarch_features + features); + + /* See arch/riscv.h. */ STATIC_IN_GDB target_desc_up @@ -83,15 +101,169 @@ riscv_create_target_description (const struct riscv_gdbarch_features features) else if (features.flen == 8) regnum = create_feature_riscv_64bit_fpu (tdesc.get (), regnum); - /* Currently GDB only supports vector features coming from remote - targets. We don't support creating vector features on native targets - (yet). */ if (features.vlen != 0) - error (_("unable to create vector feature")); + regnum = + create_feature_riscv_vector_from_features (tdesc.get (), + regnum, features); return tdesc; } + + +/* Usually, these target_desc instances are static for an architecture, and expressable + in XML format, but this is a special case where length of a RISC-V vector register + is not architecturally fixed to a constant (the maximuim width is a defined constant, + but it's nice to tailor a target description the actual VLENB) */ +static int +create_feature_riscv_vector_from_features (struct target_desc *result, + long regnum, + const struct riscv_gdbarch_features + features) +{ + struct tdesc_feature *feature; + unsigned long bitsize; + + feature = tdesc_create_feature (result, "org.gnu.gdb.riscv.vector"); + tdesc_type *element_type; + + /* if VLENB is present (which we know it is present if execution reaches this function), + then we know by definition that it is at least 4 bytes wide */ + + element_type = tdesc_named_type (feature, "uint8"); + tdesc_create_vector (feature, "bytes", element_type, features.vlen); + + element_type = tdesc_named_type (feature, "uint16"); + tdesc_create_vector (feature, "shorts", element_type, features.vlen / 2); + + element_type = tdesc_named_type (feature, "uint32"); + tdesc_create_vector (feature, "words", element_type, features.vlen / 4); + + /* Need VLENB value checks for element chunks larger than 4 bytes */ + + if (features.vlen >= 8) + { + element_type = tdesc_named_type (feature, "uint64"); + tdesc_create_vector (feature, "longs", element_type, features.vlen / 8); + } + + /* QEMU and OpenOCD include the quads width in their target descriptions, so we're + following that precedent, even if it's not particularly useful in practice, yet */ + + if (features.vlen >= 16) + { + element_type = tdesc_named_type (feature, "uint128"); + tdesc_create_vector (feature, "quads", element_type, + features.vlen / 16); + } + + tdesc_type_with_fields *type_with_fields; + type_with_fields = tdesc_create_union (feature, "riscv_vector"); + tdesc_type *field_type; + + if (features.vlen >= 16) + { + field_type = tdesc_named_type (feature, "quads"); + tdesc_add_field (type_with_fields, "q", field_type); + } + if (features.vlen >= 8) + { + field_type = tdesc_named_type (feature, "longs"); + tdesc_add_field (type_with_fields, "l", field_type); + } + + /* Again, we know vlenb is >= 4, so no if guards needed for words/shorts/bytes */ + + field_type = tdesc_named_type (feature, "words"); + tdesc_add_field (type_with_fields, "w", field_type); + + field_type = tdesc_named_type (feature, "shorts"); + tdesc_add_field (type_with_fields, "s", field_type); + + field_type = tdesc_named_type (feature, "bytes"); + tdesc_add_field (type_with_fields, "b", field_type); + + /* Register vector and CSR definitions using stable magic regnums to + ensure compatibility across GDB and gdbserver builds. */ + tdesc_create_reg (feature, "vstart", regnum++, 1, NULL, features.xlen * 8, "int"); + tdesc_create_reg (feature, "vxsat", regnum++, 1, NULL, features.xlen * 8, "int"); + tdesc_create_reg (feature, "vxrm", regnum++, 1, NULL, features.xlen * 8, "int"); + tdesc_create_reg (feature, "vcsr", regnum++, 1, NULL, features.xlen * 8, "int"); + tdesc_create_reg (feature, "vl", regnum++, 1, NULL, features.xlen * 8, "int"); + tdesc_create_reg (feature, "vtype", regnum++, 1, NULL, features.xlen * 8, "int"); + tdesc_create_reg (feature, "vlenb", regnum++, 1, NULL, features.xlen * 8, "int"); + + bitsize = features.vlen * 8; + tdesc_create_reg (feature, "v0", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v1", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v2", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v3", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v4", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v5", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v6", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v7", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v8", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v9", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v10", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v11", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v12", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v13", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v14", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v15", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v16", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v17", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v18", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v19", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v20", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v21", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v22", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v23", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v24", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v25", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v26", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v27", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v28", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v29", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v30", regnum++, 1, NULL, bitsize, + "riscv_vector"); + tdesc_create_reg (feature, "v31", regnum++, 1, NULL, bitsize, + "riscv_vector"); + + + return regnum; +} + + #ifndef GDBSERVER /* Wrapper used by std::unordered_map to generate hash for feature set. */ diff --git a/gdb/nat/riscv-linux-tdesc.c b/gdb/nat/riscv-linux-tdesc.c index 254a25ccefe..80d1ca64ba9 100644 --- a/gdb/nat/riscv-linux-tdesc.c +++ b/gdb/nat/riscv-linux-tdesc.c @@ -22,14 +22,18 @@ #include "elf/common.h" #include "nat/gdb_ptrace.h" #include "nat/riscv-linux-tdesc.h" +#include "gdbsupport/gdb_setjmp.h" #include +#include /* Work around glibc header breakage causing ELF_NFPREG not to be usable. */ #ifndef NFPREG # define NFPREG 33 #endif +static unsigned long safe_read_vlenb (); + /* See nat/riscv-linux-tdesc.h. */ struct riscv_gdbarch_features @@ -78,5 +82,69 @@ riscv_linux_read_features (int tid) break; } + features.vlen = safe_read_vlenb (); + return features; } + +static SIGJMP_BUF sigill_guard_jmp_buf; + +static void +sigill_guard (int sig) +{ + /* this will gets us back to caller deeper in the call stack, with an indication that + an illegal instruction condition was encountered */ + SIGLONGJMP (sigill_guard_jmp_buf, -1); + + /* control won't get here */ +} + + + +static unsigned long +safe_read_vlenb () +{ + /* Surrounding the attempt here to read VLENB CSR to have a signal handler set up + to trap illegal instruction condition (SIGILL), and if a trap happens during this call, + get control back within this function and return 0 in that case. + */ + unsigned long vlenb = 0; + struct sigaction our_action = { 0 }; + struct sigaction original_action; + int sysresult; + + + our_action.sa_handler = sigill_guard; + + sysresult = sigaction (SIGILL, &our_action, &original_action); + if (sysresult != 0) + { + perror + ("Error installing temporary SIGILL handler in safe_read_vlenb()"); + } + + if (SIGSETJMP (sigill_guard_jmp_buf, 1) == 0) + { + asm ("csrr %0, vlenb":"=r" (vlenb)); + } + else + { + /* Must've generated an illegal instruction condition; we'll figure this means + no vector unit is present */ + vlenb = 0; + } + + + if (sysresult == 0) + { + /* re-install former handler */ + sysresult = sigaction (SIGILL, &original_action, NULL); + if (sysresult != 0) + { + perror + ("Error re-installing original SIGILL handler in safe_read_vlenb()"); + } + + } + return vlenb; +} diff --git a/gdb/nat/riscv-linux-tdesc.h b/gdb/nat/riscv-linux-tdesc.h index de10d91caae..76f8d2f0cdd 100644 --- a/gdb/nat/riscv-linux-tdesc.h +++ b/gdb/nat/riscv-linux-tdesc.h @@ -20,9 +20,33 @@ #define GDB_NAT_RISCV_LINUX_TDESC_H #include "arch/riscv.h" +#include "asm/ptrace.h" /* Determine XLEN and FLEN for the LWP identified by TID, and return a corresponding features object. */ struct riscv_gdbarch_features riscv_linux_read_features (int tid); +#define RISCV_MAX_VLENB (8192) + +/* Some branches and/or commits of linux kernel named this "struct __riscv_v_state", + and later it was changed to "struct __riscv_v_ext_state", + so using a macro to stand-in for that struct type to make it easier to modify + in a single place, if compiling against one of those older Linux kernel commits */ +#ifndef RISCV_VECTOR_STATE_T +#define RISCV_VECTOR_STATE_T struct __riscv_v_ext_state +#endif + +/* Struct for use in ptrace() calls for vector CSRs/registers */ +struct __riscv_vregs +{ + RISCV_VECTOR_STATE_T vstate; + gdb_byte data[RISCV_MAX_VLENB * 32]; /* data will arrive packed, VLENB bytes per element, not necessarily RISCV_MAX_VLENB bytes per element */ +}; + +#define VCSR_MASK_VXSAT 0x1 +#define VCSR_POS_VXSAT 0 +#define VCSR_MASK_VXRM 0x3 +#define VCSR_POS_VXRM 1 + + #endif /* GDB_NAT_RISCV_LINUX_TDESC_H */ diff --git a/gdb/riscv-linux-nat.c b/gdb/riscv-linux-nat.c index 8846329afc6..a8dcc1e637a 100644 --- a/gdb/riscv-linux-nat.c +++ b/gdb/riscv-linux-nat.c @@ -21,6 +21,7 @@ #include "linux-nat.h" #include "riscv-tdep.h" #include "inferior.h" +#include "regset.h" #include "elf/common.h" @@ -124,6 +125,113 @@ supply_fpregset_regnum (struct regcache *regcache, const prfpregset_t *fpregs, } } +#define MEMBER_SIZE(type, member) sizeof(((type *) 0)->member) + +static const regcache_map_entry riscv_linux_vregmap[] = +{ + { 1, RISCV_CSR_VSTART_REGNUM, MEMBER_SIZE(struct __riscv_vregs, vstate.vstart) }, + { 1, RISCV_CSR_VL_REGNUM, MEMBER_SIZE(struct __riscv_vregs, vstate.vl) }, + { 1, RISCV_CSR_VTYPE_REGNUM, MEMBER_SIZE(struct __riscv_vregs, vstate.vtype) }, + { 1, RISCV_CSR_VCSR_REGNUM, MEMBER_SIZE(struct __riscv_vregs, vstate.vcsr) }, + /* struct __riscv_vregs member "datap" is a pointer that doesn't correspond + to a register value. In the context of ptrace(), member is always zero, + with V0..V31 values inline after that. So, skipping datap */ + { 1, REGCACHE_MAP_SKIP, MEMBER_SIZE(struct __riscv_vregs, vstate.datap) }, + /* Here's V0..V31. Specifying 0 as size leads to a call to register_size() + for size determination */ + { 32, RISCV_V0_REGNUM, 0 }, + { 0 }, /* count==0 represents termination of entries */ +}; + +/* Define the vector register regset. */ + +static const struct regset riscv_linux_vregset = +{ + riscv_linux_vregmap, + regcache_supply_regset /* Other RISC-V regsets use riscv_supply_regset here; not sure that'd be correct for this case */, + regcache_collect_regset +}; + + +/* Supply RISC-V vector register values (including inferred CSRs) to the GDB regcache. */ + +static void +supply_vregset_regnum (struct regcache *regcache, + const struct __riscv_vregs *vregs, int regnum) +{ + const gdb_byte *buf; + int vlenb = register_size (regcache->arch (), RISCV_V0_REGNUM); + + regcache_supply_regset (&riscv_linux_vregset, regcache, regnum, vregs, sizeof(*vregs)); + + if (regnum == -1 || regnum == RISCV_CSR_VLENB_REGNUM) + { + /* we already have a local copy above, use that (widened for XLEN padding) */ + uint64_t xlen_safe_vlenb = vlenb; + buf = (gdb_byte *) & xlen_safe_vlenb; + regcache->raw_supply (RISCV_CSR_VLENB_REGNUM, buf); + } + + if (regnum == -1 || regnum == RISCV_CSR_VXSAT_REGNUM) + { + /* this CSR is not part of vregs->vstate literally, but we can infer a value from vcsr */ + uint64_t vxsat = ((vregs->vstate.vcsr >> VCSR_POS_VXSAT) & VCSR_MASK_VXSAT); + buf = (gdb_byte *) & vxsat; + regcache->raw_supply (RISCV_CSR_VXSAT_REGNUM, buf); + } + + if (regnum == -1 || regnum == RISCV_CSR_VXRM_REGNUM) + { + /* this CSR is not part of vregs->vstate literally, but we can infer a value from vcsr */ + uint64_t vxrm = ((vregs->vstate.vcsr >> VCSR_POS_VXRM) & VCSR_MASK_VXRM); + buf = (gdb_byte *) & vxrm; + regcache->raw_supply (RISCV_CSR_VXRM_REGNUM, buf); + } +} + +/* Collect RISC-V vector register values (including inferred CSRs) from the GDB regcache. */ +static void +fill_vregset (const struct regcache *regcache, struct __riscv_vregs *vregs, + int regnum) +{ + regcache_collect_regset (&riscv_linux_vregset, regcache, regnum, vregs, sizeof(*vregs)); + + if (regnum == -1 || regnum == RISCV_CSR_VCSR_REGNUM || regnum == RISCV_CSR_VXSAT_REGNUM + || regnum == RISCV_CSR_VXRM_REGNUM) + { + uint64_t vxsat_from_regcache; + uint64_t vxrm_from_regcache; + + if ( ! (regnum == -1 || regnum == RISCV_CSR_VCSR_REGNUM) ) + { + /* We don't already have the VCSR value, from the earlier regcache_collect_regset call, so let's get it now. */ + regcache_collect_regset (&riscv_linux_vregset, regcache, RISCV_CSR_VCSR_REGNUM, vregs, sizeof(*vregs)); + } + + if (regnum == RISCV_CSR_VXSAT_REGNUM) + { + /* Overwrite VCSR with the VXSAT bit here. */ + gdb_byte *buf = (gdb_byte *) &vxsat_from_regcache; + regcache->raw_collect (RISCV_CSR_VXSAT_REGNUM, buf); + vregs->vstate.vcsr &= ~((uint64_t) VCSR_MASK_VXSAT << VCSR_POS_VXSAT); + vregs->vstate.vcsr |= ((vxsat_from_regcache & VCSR_MASK_VXSAT) << VCSR_POS_VXSAT); + } + + if (regnum == RISCV_CSR_VXRM_REGNUM) + { + /* Overwrite VCSR with the VXRM bit here. */ + gdb_byte *buf = (gdb_byte *) &vxsat_from_regcache; + regcache->raw_collect (RISCV_CSR_VXRM_REGNUM, buf); + vregs->vstate.vcsr &= ~((uint64_t) VCSR_MASK_VXRM << VCSR_POS_VXRM); + vregs->vstate.vcsr |= ((vxrm_from_regcache & VCSR_MASK_VXRM) << VCSR_POS_VXRM); + } + } + + /* VLENB register is not writable, so that's why nothing is collected here for that register. */ + +} + + /* Copy all floating point registers from regset FPREGS into REGCACHE. */ void @@ -254,6 +362,31 @@ riscv_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum) supply_fpregset_regnum (regcache, ®s, regnum); } + /* if Linux kernel was not configured to support RISC-V vectors, then + the ptrace call will return -1, and we just won't get vector registers, + but in that case it wouldn't be an error that needs user attention. + */ + if ((regnum >= RISCV_V0_REGNUM && regnum <= RISCV_V31_REGNUM) + || (regnum == RISCV_CSR_VSTART_REGNUM) + || (regnum == RISCV_CSR_VL_REGNUM) + || (regnum == RISCV_CSR_VTYPE_REGNUM) + || (regnum == RISCV_CSR_VCSR_REGNUM) + || (regnum == RISCV_CSR_VLENB_REGNUM) + || (regnum == RISCV_CSR_VXSAT_REGNUM) + || (regnum == RISCV_CSR_VXRM_REGNUM) + || (regnum == -1)) + { + struct iovec iov; + struct __riscv_vregs vregs; + + iov.iov_base = &vregs; + iov.iov_len = sizeof (vregs); + + if (ptrace (PTRACE_GETREGSET, tid, NT_RISCV_VECTOR, + (PTRACE_TYPE_ARG3) & iov) == 0) + supply_vregset_regnum (regcache, &vregs, regnum); + } + if ((regnum == RISCV_CSR_MISA_REGNUM) || (regnum == -1)) { @@ -323,6 +456,35 @@ riscv_linux_nat_target::store_registers (struct regcache *regcache, int regnum) } } + /* VLENB isn't writable, so we'll skip considering that one, if it's being + specified alone */ + if ((regnum >= RISCV_V0_REGNUM && regnum <= RISCV_V31_REGNUM) + || (regnum == RISCV_CSR_VSTART_REGNUM) + || (regnum == RISCV_CSR_VL_REGNUM) + || (regnum == RISCV_CSR_VTYPE_REGNUM) + || (regnum == RISCV_CSR_VCSR_REGNUM) + || (regnum == RISCV_CSR_VXSAT_REGNUM) + || (regnum == RISCV_CSR_VXRM_REGNUM) + || (regnum == -1)) + { + struct iovec iov; + struct __riscv_vregs vregs; + + iov.iov_base = &vregs; + iov.iov_len = sizeof (vregs); + + if (ptrace (PTRACE_GETREGSET, tid, NT_RISCV_VECTOR, + (PTRACE_TYPE_ARG3) & iov) == 0) + { + fill_vregset (regcache, &vregs, regnum); + + if (ptrace (PTRACE_SETREGSET, tid, NT_RISCV_VECTOR, + (PTRACE_TYPE_ARG3) & iov) == -1) + perror_with_name (_("Couldn't set vector registers")); + } + } + + /* Access to CSRs has potential security issues, don't support them for now. */ } diff --git a/gdb/riscv-linux-tdep.c b/gdb/riscv-linux-tdep.c index e1ea6158a45..e9531094de5 100644 --- a/gdb/riscv-linux-tdep.c +++ b/gdb/riscv-linux-tdep.c @@ -38,6 +38,10 @@ extern unsigned int record_debug; #define RISCV_NR_rt_sigreturn 139 +/* Magic number written to the head.magic field of struct __sc_riscv_v_state that kernel + places in the reserved area of struct sigcontext. Comes from */ +#define RVV_MAGIC 0x53465457 + /* Define the general register mapping. The kernel puts the PC at offset 0, gdb puts it at offset 32. Register x0 is always 0 and can be ignored. Registers x1 to x31 are in the same place. */ @@ -126,8 +130,123 @@ static const struct tramp_frame riscv_linux_sigframe = { mcontext_t uc_mcontext; }; */ + +/* Read RVV magic and size fields from address REGS_BASE and return true if a valid + RISC-V vector context header is found, otherwise return false. THIS_FRAME is used + for the architecture and byte-order when reading memory. VLEN and XLEN are the + v-register and x-register sizes (in bytes) and are used for validation. */ + +static bool +riscv_linux_vector_sigframe_header_check (frame_info_ptr this_frame, + int vlen, int xlen, + CORE_ADDR regs_base) +{ + uint32_t rvv_magic; + uint32_t rvv_size; + bool info_good = false; + + /* If vector information is available, then we should see this structure at this address: + struct __riscv_ctx_hdr { + __u32 magic; (RVV_MAGIC). + __u32 size; (size of struct __sc_riscv_v_state + vector register data size (32*VLENB)) + } head; + */ + + rvv_magic = + get_frame_memory_unsigned (this_frame, regs_base, sizeof (rvv_magic)); + regs_base += sizeof (rvv_magic); + rvv_size = + get_frame_memory_unsigned (this_frame, regs_base, sizeof (rvv_magic)); + regs_base += sizeof (rvv_size); + + + info_good = (rvv_magic == RVV_MAGIC); + if (!info_good) + { + /* Not an error, because kernels can be configured without CONFIG_VECTOR, but worth noting if frame debug + setting is turned on */ + frame_debug_printf + ("Did not find RISC-V vector information in ucontext (kernel not built with CONFIG_VECTOR?)"); + + return false; + } + + if (frame_debug) + { + uint32_t expected_rvv_size; + + frame_debug_printf + ("Located RISC-V vector information in signal frame ucontext (info size %u)", + rvv_size); + + /* sanity check the reported size; should be sizeof(uint32_t) + sizeof(uint32_t) + 5 * XLENB + 32 * vlen */ + expected_rvv_size = sizeof (uint32_t) /* magic */ + + sizeof (uint32_t) /* size */ + + 5 * xlen /* vstart, vl, vtype, vcsr, and datap */ + + 32 * vlen; /* v0..v31 values */ + + if (rvv_size != expected_rvv_size) + { + warning (_("Size in RISC-V vector information header in ucontext (%u) differs from expected size (%u)."), + rvv_size, expected_rvv_size); + + /* Additional debug details if frame_debug is on. */ + frame_debug_printf ("Detailed size mismatch: expected %u based on VLEN=%d and XLEN=%d", + expected_rvv_size, vlen, xlen); + } + } + + return info_good; +} + +static CORE_ADDR +riscv_linux_sigframe_vector_init (frame_info_ptr this_frame, + struct trad_frame_cache *this_cache, + CORE_ADDR regs_base, int xlen, int vlen) +{ + int vfieldidx; + CORE_ADDR p_datap; + CORE_ADDR datap; + + /* vstart, vl, vtype, vcsr, and datap are XLEN sized fields (unsigned long) from this point. */ + vfieldidx = 0; + trad_frame_set_reg_addr (this_cache, RISCV_CSR_VSTART_REGNUM, + regs_base + (vfieldidx * xlen)); + vfieldidx++; + trad_frame_set_reg_addr (this_cache, RISCV_CSR_VL_REGNUM, + regs_base + (vfieldidx * xlen)); + + vfieldidx++; + trad_frame_set_reg_addr (this_cache, RISCV_CSR_VTYPE_REGNUM, + regs_base + (vfieldidx * xlen)); + + vfieldidx++; + trad_frame_set_reg_addr (this_cache, RISCV_CSR_VCSR_REGNUM, + regs_base + (vfieldidx * xlen)); + + /* for the datap member, there is one level of memory indirection to get the address of + the block of values for v0..v31 */ + vfieldidx++; + p_datap = regs_base + (vfieldidx * xlen); + datap = get_frame_memory_unsigned (this_frame, p_datap, xlen); + regs_base = datap; + for (int i = 0; i < 32; i++) + { + trad_frame_set_reg_addr (this_cache, RISCV_V0_REGNUM + i, + regs_base + (i * vlen)); + } + regs_base += 32 * vlen; + + return regs_base; +} + + #define SIGFRAME_SIGINFO_SIZE 128 #define UCONTEXT_MCONTEXT_OFFSET 176 +#define MCONTEXT_VECTOR_OFFSET 784 /* offset of struct mcontext's __reserved field, + which is where the struct __sc_riscv_v_state is overlaid */ +#define RISCV_CONTEXT_HEADER_SIZE 8 /* size of struct __riscv_ctx_hdr {__u32 magic; __u32 size; } */ + static void riscv_linux_sigframe_init (const struct tramp_frame *self, @@ -138,6 +257,7 @@ riscv_linux_sigframe_init (const struct tramp_frame *self, struct gdbarch *gdbarch = get_frame_arch (this_frame); int xlen = riscv_isa_xlen (gdbarch); int flen = riscv_isa_flen (gdbarch); + int vlen = riscv_isa_vlen (gdbarch); CORE_ADDR frame_sp = get_frame_sp (this_frame); CORE_ADDR mcontext_base; CORE_ADDR regs_base; @@ -161,6 +281,19 @@ riscv_linux_sigframe_init (const struct tramp_frame *self, regs_base += 32 * flen; trad_frame_set_reg_addr (this_cache, RISCV_CSR_FCSR_REGNUM, regs_base); + /* Handle the vector registers, if present. */ + if (vlen > 0) + { + regs_base = mcontext_base + MCONTEXT_VECTOR_OFFSET; + if (riscv_linux_vector_sigframe_header_check + (this_frame, vlen, xlen, regs_base)) + { + regs_base += RISCV_CONTEXT_HEADER_SIZE; /* advance past the header */ + riscv_linux_sigframe_vector_init (this_frame, this_cache, regs_base, + xlen, vlen); + } + } + /* Choice of the bottom of the sigframe is somewhat arbitrary. */ trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); } diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index a735c095b0d..f61a3429b70 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -47,6 +47,7 @@ #include "remote.h" #include "target-descriptions.h" #include "dwarf2/frame.h" +#include "dwarf2/expr.h" #include "user-regs.h" #include "valprint.h" #include "opcode/riscv-opc.h" @@ -653,6 +654,14 @@ struct riscv_vector_feature : public riscv_register_feature { RISCV_V0_REGNUM + 29, { "v29" } }, { RISCV_V0_REGNUM + 30, { "v30" } }, { RISCV_V0_REGNUM + 31, { "v31" } }, + /* vector CSRs */ + { RISCV_CSR_VSTART_REGNUM, { "vstart" } }, + { RISCV_CSR_VXSAT_REGNUM, { "vxsat" } }, + { RISCV_CSR_VXRM_REGNUM, { "vxrm" } }, + { RISCV_CSR_VL_REGNUM, { "vl" } }, + { RISCV_CSR_VTYPE_REGNUM, { "vtype" } }, + { RISCV_CSR_VCSR_REGNUM, { "vcsr" } }, + { RISCV_CSR_VLENB_REGNUM, { "vlenb" } }, }; } @@ -684,10 +693,16 @@ struct riscv_vector_feature : public riscv_register_feature return true; } - /* Check all of the vector registers are present. */ + /* Check all of the vector registers are present. We also + check that the vector CSRs are present too, though if these + are missing this is not fatal. */ for (const auto ® : m_registers) { - if (!reg.check (tdesc_data, feature_vector, aliases)) + bool found = reg.check (tdesc_data, feature_vector, aliases); + + bool is_ctrl_reg_p = !(reg.regnum >= RISCV_V0_REGNUM && reg.regnum <= RISCV_V31_REGNUM); + + if (!found && !is_ctrl_reg_p) return false; } @@ -697,6 +712,12 @@ struct riscv_vector_feature : public riscv_register_feature int vector_bitsize = -1; for (const auto ® : m_registers) { + + bool is_ctrl_reg_p = !(reg.regnum >= RISCV_V0_REGNUM && reg.regnum <= RISCV_V31_REGNUM); + + if (is_ctrl_reg_p) + continue; + int reg_bitsize = -1; for (const char *name : reg.names) { @@ -819,6 +840,16 @@ riscv_abi_embedded (struct gdbarch *gdbarch) return tdep->abi_features.embedded; } +/* See riscv-tdep.h. */ + +int +riscv_isa_vlen (struct gdbarch *gdbarch) +{ + riscv_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + return tdep->isa_features.vlen; +} + + /* Return true if the target for GDBARCH has floating point hardware. */ static bool @@ -1470,7 +1501,19 @@ riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum, return 0; } else if (reggroup == vector_reggroup) - return (regnum >= RISCV_V0_REGNUM && regnum <= RISCV_V31_REGNUM); + { + if (regnum >= RISCV_V0_REGNUM && regnum <= RISCV_V31_REGNUM) + return 1; + if (regnum == RISCV_CSR_VSTART_REGNUM + || regnum == RISCV_CSR_VXSAT_REGNUM + || regnum == RISCV_CSR_VXRM_REGNUM + || regnum == RISCV_CSR_VL_REGNUM + || regnum == RISCV_CSR_VTYPE_REGNUM + || regnum == RISCV_CSR_VCSR_REGNUM + || regnum == RISCV_CSR_VLENB_REGNUM) + return 1; + return 0; + } else return 0; } diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h index 2903aefd007..82213f820f3 100644 --- a/gdb/riscv-tdep.h +++ b/gdb/riscv-tdep.h @@ -50,6 +50,7 @@ enum RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */ RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */ + #define DECLARE_CSR(name, num, class, define_version, abort_version) \ RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num, #include "opcode/riscv-opc.h" @@ -158,6 +159,11 @@ extern int riscv_abi_flen (struct gdbarch *gdbarch); argument registers. */ extern bool riscv_abi_embedded (struct gdbarch *gdbarch); +/* Return the width in bytes of the hardware vector registers for + GDBARCH. If this architecture has no vector registers, then + return 0. */ +extern int riscv_isa_vlen (struct gdbarch *gdbarch); + /* Single step based on where the current instruction will take us. */ extern std::vector riscv_software_single_step (struct regcache *regcache); diff --git a/gdbserver/linux-riscv-low.cc b/gdbserver/linux-riscv-low.cc index 8c742f406a2..face971a5e7 100644 --- a/gdbserver/linux-riscv-low.cc +++ b/gdbserver/linux-riscv-low.cc @@ -161,6 +161,113 @@ riscv_store_fpregset (struct regcache *regcache, const void *buf) supply_register_by_name (regcache, "fcsr", regbuf); } +/* Collect vector registers from REGCACHE into BUF. */ + +static void +riscv_fill_vregset (struct regcache *regcache, void *buf) +{ + const struct target_desc *tdesc = regcache->tdesc; + int regno = find_regno (tdesc, "v0"); + int vlenb = register_size (regcache->tdesc, regno); + uint64_t u64_vlenb = vlenb; /* pad to max XLEN for buffer conversion */ + uint64_t u64_vxsat = 0; + uint64_t u64_vxrm = 0; + uint64_t u64_vcsr = 0; + gdb_byte *regbuf; + int i; + + /* Since vxsat and equivalent bits in vcsr are aliases (and same for vxrm), we have a dilemma. + For this gdb -> gdbserver topology, if the aliased pairs have values that disagree, then + which value should take precedence? We don't know which alias was most + recently assigned. We're just getting a block of register values including vxsat, vxrm, + and vcsr. We have to impose some kind of rule for predictable resolution to resolve any inconsistency. + For now, let's say that vxsat and vxrm take precedence, and those values will be applied to the + corresponding fields in vcsr. Reconcile these 3 interdependent registers now: + */ + regbuf = (gdb_byte *) & u64_vcsr; + collect_register_by_name (regcache, "vcsr", regbuf); + regbuf = (gdb_byte *) & u64_vxsat; + collect_register_by_name (regcache, "vxsat", regbuf); + regbuf = (gdb_byte *) & u64_vxrm; + collect_register_by_name (regcache, "vxrm", regbuf); + + u64_vcsr &= ~((uint64_t)VCSR_MASK_VXSAT << VCSR_POS_VXSAT); + u64_vcsr |= ((u64_vxsat & VCSR_MASK_VXSAT) << VCSR_POS_VXSAT); + u64_vcsr &= ~((uint64_t)VCSR_MASK_VXRM << VCSR_POS_VXRM); + u64_vcsr |= ((u64_vxrm & VCSR_MASK_VXRM) << VCSR_POS_VXRM); + + /* Replace the original vcsr value with the "cooked" value */ + regbuf = (gdb_byte *) & u64_vcsr; + supply_register_by_name (regcache, "vcsr", regbuf); + + /* Now stage the ptrace buffer (it'll receive the cooked vcsr value) */ + + regbuf = (gdb_byte *) buf + offsetof (struct __riscv_vregs, vstate.vstart); + collect_register_by_name (regcache, "vstart", regbuf); + regbuf = (gdb_byte *) buf + offsetof (struct __riscv_vregs, vstate.vl); + collect_register_by_name (regcache, "vl", regbuf); + regbuf = (gdb_byte *) buf + offsetof (struct __riscv_vregs, vstate.vtype); + collect_register_by_name (regcache, "vtype", regbuf); + regbuf = (gdb_byte *) buf + offsetof (struct __riscv_vregs, vstate.vcsr); + collect_register_by_name (regcache, "vcsr", regbuf); + regbuf = (gdb_byte *) & u64_vlenb; + collect_register_by_name (regcache, "vlenb", regbuf); + + + regbuf = (gdb_byte *) buf + offsetof (struct __riscv_vregs, data); + for (i = 0; i < 32; i++, regbuf += vlenb) + collect_register (regcache, regno + i, regbuf); +} + +/* Supply vector registers from BUF into REGCACHE. */ + +static void +riscv_store_vregset (struct regcache *regcache, const void *buf) +{ + const struct target_desc *tdesc = regcache->tdesc; + int regno = find_regno (tdesc, "v0"); + int vlenb = register_size (regcache->tdesc, regno); + uint64_t u64_vlenb = vlenb; /* pad to max XLEN for buffer conversion */ + uint64_t vcsr; + uint64_t vxsat; + uint64_t vxrm; + const gdb_byte *regbuf; + int i; + + regbuf = + (const gdb_byte *) buf + offsetof (struct __riscv_vregs, vstate.vstart); + supply_register_by_name (regcache, "vstart", regbuf); + regbuf = + (const gdb_byte *) buf + offsetof (struct __riscv_vregs, vstate.vl); + supply_register_by_name (regcache, "vl", regbuf); + regbuf = + (const gdb_byte *) buf + offsetof (struct __riscv_vregs, vstate.vtype); + supply_register_by_name (regcache, "vtype", regbuf); + regbuf = + (const gdb_byte *) buf + offsetof (struct __riscv_vregs, vstate.vcsr); + supply_register_by_name (regcache, "vcsr", regbuf); + /* also store off a non-byte-wise copy of vcsr, to derive values for vxsat and vxrm */ + vcsr = *(uint64_t*)regbuf; + /* vlenb isn't part of vstate, but we have already inferred its value by running code on this + hart, and we're assuming homogeneous VLENB if it's an SMP system */ + regbuf = (gdb_byte *) & u64_vlenb; + supply_register_by_name (regcache, "vlenb", regbuf); + + /* vxsat and vxrm, are not part of vstate, so we have to extract from VCSR + value */ + vxsat = ((vcsr >> VCSR_POS_VXSAT) & VCSR_MASK_VXSAT); + regbuf = (gdb_byte *) &vxsat; + supply_register_by_name (regcache, "vxsat", regbuf); + vxrm = ((vcsr >> VCSR_POS_VXRM) & VCSR_MASK_VXRM); + regbuf = (gdb_byte *) &vxrm; + supply_register_by_name (regcache, "vxrm", regbuf); + + /* v0..v31 */ + regbuf = (const gdb_byte *) buf + offsetof (struct __riscv_vregs, data); + for (i = 0; i < 32; i++, regbuf += vlenb) + supply_register (regcache, regno + i, regbuf); +} + /* RISC-V/Linux regsets. FPRs are optional and come in different sizes, so define multiple regsets for them marking them all as OPTIONAL_REGS rather than FP_REGS, so that "regsets_fetch_inferior_registers" picks @@ -178,6 +285,9 @@ static struct regset_info riscv_regsets[] = { { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, sizeof (struct __riscv_mc_f_ext_state), OPTIONAL_REGS, riscv_fill_fpregset, riscv_store_fpregset }, + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_RISCV_VECTOR, + sizeof (struct __riscv_vregs), OPTIONAL_REGS, + riscv_fill_vregset, riscv_store_vregset }, NULL_REGSET }; diff --git a/include/elf/common.h b/include/elf/common.h index fd032d1e03e..7003f987b94 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -758,6 +758,7 @@ /* note name must be "LINUX". */ #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */ /* note name must be "LINUX". */ +#define NT_RISCV_VECTOR 0x901 /* RISC-V Vector Registers. */ #define NT_SIGINFO 0x53494749 /* Fields of siginfo_t. */ #define NT_FILE 0x46494c45 /* Description of mapped files. */ -- 2.43.0