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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: htecgroup.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PR3PR09MB4361.eurprd09.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e49e94b9-b6d9-4716-039a-08dd50e58c12 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Feb 2025 13:01:38.3912 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 9f85665b-7efd-4776-9dfe-b6bfda2565ee X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jQN7n2C0Jjvs1suzwn9wLjwUlID139UMN86cbuttL0hEprRLhPbO2lWcwa0WWQO80JPwpyWbdJPGkLqSz74qd+snJkR+57r7t9iF6U+A90I= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR09MB6726 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org Introduce new instruction encodings from Release 6 of the MIPS architecture [1]. Support breakpoints and single stepping with compact branches, forbidden slots, new branch instruction and new atomic load-store instruction encodings. --- gdb/mips-tdep.c | 548 +++++++++++++-- gdb/testsuite/gdb.arch/mips-64-r6.c | 916 ++++++++++++++++++++++++++ gdb/testsuite/gdb.arch/mips-64-r6.exp | 76 +++ 3 files changed, 1498 insertions(+), 42 deletions(-) create mode 100644 gdb/testsuite/gdb.arch/mips-64-r6.c create mode 100644 gdb/testsuite/gdb.arch/mips-64-r6.exp diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c index dbf0b1aa5df..49093640e01 100644 --- a/gdb/mips-tdep.c +++ b/gdb/mips-tdep.c @@ -76,6 +76,10 @@ static int mips16_insn_at_pc_has_delay_slot (struct gdba= rch *gdbarch, static void mips_print_float_info (struct gdbarch *, struct ui_file *, const frame_info_ptr &, const char *); =20 +static void +mips_read_fp_register_single (const frame_info_ptr &frame, int regno, + gdb::array_view rare_buffer); + /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ #define ST0_FR (1 << 26) @@ -326,6 +330,17 @@ mips_abi_regsize (struct gdbarch *gdbarch) } } =20 +/* Return true if the gdbarch is based on MIPS Release 6. */ + +static bool +is_mipsr6_isa (struct gdbarch *gdbarch) +{ + const struct bfd_arch_info *info =3D gdbarch_bfd_arch_info (gdbarch); + + return (info->mach =3D=3D bfd_mach_mipsisa32r6 + || info->mach =3D=3D bfd_mach_mipsisa64r6); +} + /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here are some functions to handle addresses associated with compressed code including but not limited to testing, setting, or clearing @@ -1553,6 +1568,7 @@ mips_fetch_instruction (struct gdbarch *gdbarch, #define b0s11_op(x) ((x) & 0x7ff) #define b0s12_imm(x) ((x) & 0xfff) #define b0s16_imm(x) ((x) & 0xffff) +#define b0s21_imm(x) ((x) & 0x1fffff) #define b0s26_imm(x) ((x) & 0x3ffffff) #define b6s10_ext(x) (((x) >> 6) & 0x3ff) #define b11s5_reg(x) (((x) >> 11) & 0x1f) @@ -1589,6 +1605,24 @@ mips32_relative_offset (ULONGEST inst) return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; } =20 +/* Calculates pc-relative offset from lower 21 bits of instruction. + Used by BEQZC, BNEZC. */ + +static LONGEST +mips32_relative_offset21 (ULONGEST insn) +{ + return ((b0s21_imm (insn) ^ 0x100000) - 0x100000) << 2; +} + +/* Calculates pc-relative offset from lower 26 bits of an instruction. + Used by BC, BALC. */ + +static LONGEST +mips32_relative_offset26 (ULONGEST insn) +{ + return ((b0s26_imm (insn) ^ 0x2000000) - 0x2000000) << 2; +} + /* Determine the address of the next instruction executed after the INST floating condition branch instruction at PC. COUNT specifies the number of the floating condition bits tested by the branch. */ @@ -1649,6 +1683,77 @@ is_octeon_bbit_op (int op, struct gdbarch *gdbarch) return 0; } =20 +/* Detects whether overflow occurs when adding two 32-bit integers. */ + +static bool +is_add32bit_overflow (int32_t a, int32_t b) +{ + int32_t r =3D (uint32_t) a + (uint32_t) b; + return (a < 0 && b < 0 && r >=3D 0) || (a > 0 && b > 0 && r <=3D 0); +} + +/* Helper function for BOVC and BNVC instructions which are introduced in + MIPS Release 6. + + BOVC performs a signed 32-bit addition of two registers. BOVC discards= the + sum, but detects signed 32-bit integer overflow of the sum (and the inp= uts, + in MIPS64), and branches if such overflow is detected. + + BNVC does the opposite, i.e. branches if such overflow is not detected.= */ + +static bool +is_add64bit_overflow (int64_t a, int64_t b) +{ + if (a !=3D (int32_t) a) + return true; + if (b !=3D (int32_t) b) + return true; + return is_add32bit_overflow ((int32_t) a, (int32_t) b); +} + +#define DELAY_SLOT_SIZE 4 + +/* Calculate address of next instruction after BLEZ. */ + +static CORE_ADDR +mips32_blez_pc (struct gdbarch *gdbarch, struct regcache *regcache, + ULONGEST inst, CORE_ADDR pc, int invert) +{ + int rs =3D itype_rs (inst); + int rt =3D itype_rt (inst); + LONGEST val_rs =3D regcache_raw_get_signed (regcache, rs); + LONGEST val_rt =3D regcache_raw_get_signed (regcache, rt); + ULONGEST uval_rs =3D regcache_raw_get_unsigned (regcache, rs); + ULONGEST uval_rt =3D regcache_raw_get_unsigned (regcache, rt); + bool taken =3D false; + + /* BLEZ, BLEZL, BGTZ, BGTZL */ + if (rt =3D=3D 0) + taken =3D (val_rs <=3D 0); + else if (is_mipsr6_isa (gdbarch)) + { + /* BLEZALC, BGTZALC */ + if (rs =3D=3D 0 && rt !=3D 0) + taken =3D (val_rt <=3D 0); + /* BGEZALC, BLTZALC */ + else if (rs =3D=3D rt && rt !=3D 0) + taken =3D (val_rt >=3D 0); + /* BGEUC, BLTUC */ + else if (rs !=3D rt && rs !=3D 0 && rt !=3D 0) + taken =3D (uval_rs >=3D uval_rt); + } + + if (invert) + taken =3D !taken; + + /* Calculate branch target. */ + if (taken) + pc +=3D mips32_relative_offset (inst); + else + pc +=3D DELAY_SLOT_SIZE; + + return pc; +} =20 /* Determine where to set a single step breakpoint while considering branch prediction. */ @@ -1659,11 +1764,16 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc) struct gdbarch *gdbarch =3D regcache->arch (); unsigned long inst; int op; + bool mips64bitreg =3D false; + + if (mips_isa_regsize (gdbarch) =3D=3D 8) + mips64bitreg =3D true; + inst =3D mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); op =3D itype_op (inst); if ((inst & 0xe0000000) !=3D 0) /* Not a special, jump or branch instruc= tion. */ { - if (op >> 2 =3D=3D 5) + if (op >> 2 =3D=3D 5 && ((op & 0x02) =3D=3D 0 || itype_rt (inst) =3D= =3D 0)) { /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ switch (op & 0x03) @@ -1673,7 +1783,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR = pc) case 1: /* BNEL */ goto neq_branch; case 2: /* BLEZL */ - goto less_branch; + goto lez_branch; case 3: /* BGTZL */ goto greater_branch; default: @@ -1685,19 +1795,23 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc) /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1); } - else if (op =3D=3D 17 && itype_rs (inst) =3D=3D 9 + else if (!is_mipsr6_isa (gdbarch) + && op =3D=3D 17 + && itype_rs (inst) =3D=3D 9 && (itype_rt (inst) & 2) =3D=3D 0) { /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2); } - else if (op =3D=3D 17 && itype_rs (inst) =3D=3D 10 + else if (!is_mipsr6_isa (gdbarch) + && op =3D=3D 17 + && itype_rs (inst) =3D=3D 10 && (itype_rt (inst) & 2) =3D=3D 0) { /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4); } - else if (op =3D=3D 29) + else if (!is_mipsr6_isa (gdbarch) && op =3D=3D 29) { /* JALX: 011101 The new PC will be alternate mode. */ @@ -1730,7 +1844,148 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc) pc +=3D 8; } } + else if (is_mipsr6_isa (gdbarch)) + { + if (op =3D=3D 8 || op =3D=3D 24) + { + /* BOVC, BEQZALC, BEQC and BNVC, BNEZALC, BNEC */ + int rs =3D rtype_rs (inst); + int rt =3D rtype_rt (inst); + LONGEST val_rs =3D regcache_raw_get_signed (regcache, rs); + LONGEST val_rt =3D regcache_raw_get_signed (regcache, rt); + bool taken =3D false; + if (rs >=3D rt) + { + /* BOVC (BNVC) */ + if (mips64bitreg) + taken =3D is_add64bit_overflow (val_rs, val_rt); + else + taken =3D is_add32bit_overflow (val_rs, val_rt); + } + else if (rs < rt && rs =3D=3D 0) + { + /* BEQZALC (BNEZALC) */ + taken =3D (val_rt =3D=3D 0); + } + else + { + /* BEQC (BNEC) */ + taken =3D (val_rs =3D=3D val_rt); + } =20 + if (op =3D=3D 24) + { + /* BNVC, BNEZALC, BNEC */ + taken =3D !taken; + } + + if (taken) + pc +=3D mips32_relative_offset (inst) + 4; + else + { + /* Step through the forbidden slot to avoid repeated + exceptions. + We do not currently have access to the BD bit when hitting + a breakpoint and therefore cannot tell if the breakpoint + hit on the branch or the forbidden slot. */ + pc +=3D 8; + } + } + else if (op =3D=3D 17 && (itype_rs (inst) =3D=3D 9 || itype_rs (inst) = =3D=3D 13)) + { + /* BC1EQZ, BC1NEZ */ + gdb_byte status; + gdb_byte true_val =3D 0; + unsigned int fp =3D (gdbarch_num_regs (gdbarch) + + mips_regnum (gdbarch)->fp0 + + itype_rt (inst)); + struct frame_info_ptr frame =3D get_current_frame (); + gdb_byte *buf_tmp =3D (gdb_byte *) alloca (sizeof (gdb_byte) * 4); + gdb::array_view raw_buffer =3D gdb::make_array_view (buf_= tmp, sizeof (gdb_byte) * 4); + mips_read_fp_register_single (frame, fp, raw_buffer); + + if (gdbarch_byte_order (gdbarch) =3D=3D BFD_ENDIAN_BIG) + status =3D raw_buffer[3]; + else + status =3D raw_buffer[0]; + + if (itype_rs (inst) =3D=3D 13) + true_val =3D 1; + + if ((status & 0x1) =3D=3D true_val) + pc +=3D mips32_relative_offset (inst) + 4; + else + pc +=3D 8; + } + else if (op =3D=3D 22 || op =3D=3D 23) + { + /* BLEZC, BGEZC, BGEC, BGTZC, BLTZC, BLTC */ + int rs =3D rtype_rs (inst); + int rt =3D rtype_rt (inst); + LONGEST val_rs =3D regcache_raw_get_signed (regcache, rs); + LONGEST val_rt =3D regcache_raw_get_signed (regcache, rt); + bool taken =3D false; + /* The R5 rt =3D=3D 0 case is handled above so we treat it as + an unknown instruction here for future ISA usage. */ + if (rs =3D=3D 0 && rt !=3D 0) + taken =3D (val_rt <=3D 0); + else if (rs =3D=3D rt && rt !=3D 0) + taken =3D (val_rt >=3D 0); + else if (rs !=3D rt && rs !=3D 0 && rt !=3D 0) + taken =3D (val_rs >=3D val_rt); + + if (op =3D=3D 23) + taken =3D !taken; + + if (taken) + pc +=3D mips32_relative_offset (inst) + 4; + else + { + /* Step through the forbidden slot to avoid repeated + exceptions. + We do not currently have access to the BD bit when hitting + a breakpoint and therefore cannot tell if the breakpoint + hit on the branch or the forbidden slot. */ + pc +=3D 8; + } + } + else if (op =3D=3D 50 || op =3D=3D 58) + { + /* BC, BALC */ + pc +=3D mips32_relative_offset26 (inst) + 4; + } + else if ((op =3D=3D 54 || op =3D=3D 62) + && rtype_rs (inst) =3D=3D 0) + { + /* JIC, JIALC */ + pc =3D regcache_raw_get_signed (regcache, itype_rt (inst)); + pc +=3D (itype_immediate (inst) ^ 0x8000) - 0x8000; + } + else if (op =3D=3D 54 || op =3D=3D 62) + { + /* BEQZC, BNEZC */ + int rs =3D itype_rs (inst); + LONGEST rs_val =3D regcache_raw_get_signed (regcache, rs); + bool taken =3D (rs_val =3D=3D 0); + if (op =3D=3D 62) + taken =3D !taken; + if (taken) + pc +=3D mips32_relative_offset21 (inst) + 4; + else + { + /* Step through the forbidden slot to avoid repeated exceptions + we do not currently have access to the BD bit when hitting a + breakpoint and therefore cannot tell if the breakpoint + hit on the branch or the forbidden slot. */ + pc +=3D 8; + } + } + else + { + /* Not a branch, next instruction is easy. */ + pc +=3D 4; + } + } else pc +=3D 4; /* Not a branch, next instruction is easy. */ } @@ -1774,7 +2029,6 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR = pc) case 2: /* BLTZL */ case 16: /* BLTZAL */ case 18: /* BLTZALL */ - less_branch: if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0) pc +=3D mips32_relative_offset (inst) + 4; else @@ -1790,6 +2044,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR = pc) pc +=3D 8; /* after the delay slot */ break; case 0x1c: /* BPOSGE32 */ + case 0x1d: /* BPOSGE32C */ case 0x1e: /* BPOSGE64 */ pc +=3D 4; if (itype_rs (inst) =3D=3D 0) @@ -1803,11 +2058,18 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc) break; } =20 + /* BPOSGE32C */ + if (op =3D=3D 0x1d) + { + if (!is_mipsr6_isa (gdbarch)) + break; + } + if ((regcache_raw_get_unsigned (regcache, dspctl) & 0x7f) >=3D pos) pc +=3D mips32_relative_offset (inst); else - pc +=3D 4; + pc +=3D DELAY_SLOT_SIZE; } break; /* All of the other instructions in the REGIMM category */ @@ -1841,19 +2103,14 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc) else pc +=3D 8; break; - case 6: /* BLEZ, BLEZL */ - if (regcache_raw_get_signed (regcache, itype_rs (inst)) <=3D 0) - pc +=3D mips32_relative_offset (inst) + 4; - else - pc +=3D 8; + case 6: /* BLEZ, BLEZL, BLEZALC, BGEZALC, BGEUC */ + lez_branch: + pc =3D mips32_blez_pc (gdbarch, regcache, inst, pc + 4, 0); break; case 7: default: - greater_branch: /* BGTZ, BGTZL */ - if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0) - pc +=3D mips32_relative_offset (inst) + 4; - else - pc +=3D 8; + greater_branch: /* BGTZ, BGTZL, BGTZALC, BLTZALC, BLTUC */ + pc =3D mips32_blez_pc (gdbarch, regcache, inst, pc + 4, 1); break; } /* switch */ } /* else */ @@ -2486,6 +2743,63 @@ micromips_instruction_is_compact_branch (unsigned sh= ort insn) } } =20 +/* Return non-zero if the MIPS instruction INSN is a compact branch + or jump. A value of 1 indicates an unconditional compact branch + and a value of 2 indicates a conditional compact branch. */ + +static int +mips32_instruction_is_compact_branch (struct gdbarch *gdbarch, ULONGEST in= sn) +{ + switch (itype_op (insn)) + { + case 50: /* BC */ + case 58: /* BALC */ + if (is_mipsr6_isa (gdbarch)) + return 1; + break; + case 8: /* BOVC, BEQZALC, BEQC */ + case 24: /* BNVC, BNEZALC, BNEC */ + if (is_mipsr6_isa (gdbarch)) + return 2; + break; + case 54: /* BEQZC, JIC */ + case 62: /* BNEZC, JIALC */ + if (is_mipsr6_isa (gdbarch)) + { + /* JIC, JIALC are unconditional */ + return (itype_rs (insn) =3D=3D 0) ? 1 : 2; + } + break; + case 22: /* BLEZC, BGEZC, BGEC */ + case 23: /* BGTZC, BLTZC, BLTC */ + case 6: /* BLEZALC, BGEZALC, BGEUC */ + case 7: /* BGTZALC, BLTZALC, BLTUC */ + if (is_mipsr6_isa (gdbarch) + && itype_rt (insn) !=3D 0) + return 2; + break; + case 1: /* BPOSGE32C */ + if (is_mipsr6_isa (gdbarch) + && itype_rt (insn) =3D=3D 0x1d && itype_rs (insn) =3D=3D 0) + return 2; + } + return 0; +} + +/* Return true if a standard MIPS instruction at ADDR has a branch + forbidden slot (i.e. it is a conditional compact branch instruction). = */ + +static bool +mips32_insn_at_pc_has_forbidden_slot (struct gdbarch *gdbarch, CORE_ADDR a= ddr) +{ + int status; + ULONGEST insn =3D mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &stat= us); + if (status) + return false; + + return mips32_instruction_is_compact_branch (gdbarch, insn) =3D=3D 2; +} + struct mips_frame_cache { CORE_ADDR base; @@ -3529,7 +3843,8 @@ mips32_scan_prologue (struct gdbarch *gdbarch, reg =3D high_word & 0x1f; =20 if (high_word =3D=3D 0x27bd /* addiu $sp,$sp,-i */ - || high_word =3D=3D 0x23bd /* addi $sp,$sp,-i */ + || (high_word =3D=3D 0x23bd /* addi $sp,$sp,-i */ + && !is_mipsr6_isa (gdbarch)) || high_word =3D=3D 0x67bd) /* daddiu $sp,$sp,-i */ { if (offset < 0) /* Negative stack adjustment? */ @@ -3669,7 +3984,9 @@ mips32_scan_prologue (struct gdbarch *gdbarch, =20 /* A jump or branch, or enough non-prologue insns seen? If so, then we must have reached the end of the prologue by now. */ - if (prev_delay_slot || non_prologue_insns > 1) + if (prev_delay_slot + || non_prologue_insns > 1 + || mips32_instruction_is_compact_branch (gdbarch, inst)) break; =20 prev_non_prologue_insn =3D this_non_prologue_insn; @@ -3975,6 +4292,70 @@ mips_addr_bits_remove (struct gdbarch *gdbarch, CORE= _ADDR addr) #define LLD_OPCODE 0x34 #define SC_OPCODE 0x38 #define SCD_OPCODE 0x3c +#define LLSC_R6_OPCODE 0x1f +#define LL_R6_FUNCT 0x36 +#define LLE_FUNCT 0x2e +#define LLD_R6_FUNCT 0x37 +#define SC_R6_FUNCT 0x26 +#define SCE_FUNCT 0x1e +#define SCD_R6_FUNCT 0x27 + +/* Determine whether instruction 'insn' is of 'load linked X' type. + LL/SC instructions provide primitives to implement atomic + read-modify-write operations for synchronizable memory locations. */ + +static bool +is_ll_insn (struct gdbarch *gdbarch, ULONGEST insn) +{ + if (itype_op (insn) =3D=3D LL_OPCODE + || itype_op (insn) =3D=3D LLD_OPCODE) + return true; + + if (rtype_op (insn) =3D=3D LLSC_R6_OPCODE + && rtype_funct (insn) =3D=3D LLE_FUNCT + && (insn & 0x40) =3D=3D 0) + return true; + + /* Handle LL and LLP varieties. */ + if (is_mipsr6_isa (gdbarch) + && rtype_op (insn) =3D=3D LLSC_R6_OPCODE + && (rtype_funct (insn) =3D=3D LL_R6_FUNCT + || rtype_funct (insn) =3D=3D LLD_R6_FUNCT + || rtype_funct (insn) =3D=3D LLE_FUNCT)) + return true; + + return false; +} + +/* Determine whether instruction 'insn' is of 'store conditional X' type. + SC instructions and varieties perform completion of read-modify-write + atomic sequence. */ + +static bool +is_sc_insn (struct gdbarch *gdbarch, ULONGEST insn) +{ + if (itype_op (insn) =3D=3D SC_OPCODE + || itype_op (insn) =3D=3D SCD_OPCODE) + return true; + + if (rtype_op (insn) =3D=3D LLSC_R6_OPCODE + && rtype_funct (insn) =3D=3D SCE_FUNCT + && (insn & 0x40) =3D=3D 0) + return true; + + /* Handle SC and SCP varieties. */ + if (is_mipsr6_isa (gdbarch) + && rtype_op (insn) =3D=3D LLSC_R6_OPCODE + && (rtype_funct (insn) =3D=3D SC_R6_FUNCT + || rtype_funct (insn) =3D=3D SCD_R6_FUNCT + || rtype_funct (insn) =3D=3D SCE_FUNCT)) + return true; + + return false; +} + +/* Handle mips atomic sequence which starts with LL/LLD and ends with + SC/SCD instruction. */ =20 static std::vector mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) @@ -3987,10 +4368,11 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdb= arch, CORE_ADDR pc) int index; int last_breakpoint =3D 0; /* Defaults to 0 (no breakpoints placed). */ const int atomic_sequence_length =3D 16; /* Instruction sequence length.= */ + bool is_mipsr6 =3D is_mipsr6_isa (gdbarch); =20 insn =3D mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); /* Assume all atomic sequences start with a ll/lld instruction. */ - if (itype_op (insn) !=3D LL_OPCODE && itype_op (insn) !=3D LLD_OPCODE) + if (!is_ll_insn (gdbarch, insn)) return {}; =20 /* Assume that no atomic sequence is longer than "atomic_sequence_length= " @@ -4020,28 +4402,72 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdb= arch, CORE_ADDR pc) return {}; /* fallback to the standard single-step code. */ case 4: /* BEQ */ case 5: /* BNE */ - case 6: /* BLEZ */ - case 7: /* BGTZ */ case 20: /* BEQL */ case 21: /* BNEL */ - case 22: /* BLEZL */ - case 23: /* BGTTL */ + case 22: /* BLEZL (BLEZC, BGEZC, BGEC) */ + case 23: /* BGTZL (BGTZC, BLTZC, BLTC) */ is_branch =3D 1; break; + case 6: /* BLEZ (BLEZALC, BGEZALC, BGEUC) */ + case 7: /* BGTZ (BGTZALC, BLTZALC, BLTUC) */ + if (is_mipsr6) + { + /* BLEZALC, BGTZALC */ + if (itype_rs (insn) =3D=3D 0 && itype_rt (insn) !=3D 0) + return {}; /* fallback to the standard single-step code. */ + /* BGEZALC, BLTZALC */ + else if (itype_rs (insn) =3D=3D itype_rt (insn) + && itype_rt (insn) !=3D 0) + return {}; /* fallback to the standard single-step code. */ + } + is_branch =3D 1; + break; + case 8: /* BOVC, BEQZALC, BEQC */ + case 24: /* BNVC, BNEZALC, BNEC */ + if (is_mipsr6) + is_branch =3D 1; + break; + case 50: /* BC */ + case 58: /* BALC */ + if (is_mipsr6) + return {}; /* fallback to the standard single-step code. */ + break; + case 54: /* BEQZC, JIC */ + case 62: /* BNEZC, JIALC */ + if (is_mipsr6) + { + if (itype_rs (insn) =3D=3D 0) /* JIC, JIALC */ + return {}; /* fallback to the standard single-step code. */ + else + is_branch =3D 2; /* Marker for branches with a 21-bit offset. */ + } + break; case 17: /* COP1 */ - is_branch =3D ((itype_rs (insn) =3D=3D 9 || itype_rs (insn) =3D=3D 10) - && (itype_rt (insn) & 0x2) =3D=3D 0); - if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ + is_branch =3D ((!is_mipsr6 + /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ + && (itype_rs (insn) =3D=3D 9 || itype_rs (insn) =3D=3D 10) + && (itype_rt (insn) & 0x2) =3D=3D 0) + /* BZ.df: 010001 110xx */ + || (itype_rs (insn) & 0x18) =3D=3D 0x18); + if (is_branch !=3D 0) break; [[fallthrough]]; case 18: /* COP2 */ case 19: /* COP3 */ - is_branch =3D (itype_rs (insn) =3D=3D 8); /* BCzF, BCzFL, BCzT, BCzTL *= / + /* BCzF, BCzFL, BCzT, BCzTL, BC*EQZ, BC*NEZ */ + is_branch =3D ((itype_rs (insn) =3D=3D 8) + || (is_mipsr6 + && (itype_rs (insn) =3D=3D 9 + || itype_rs (insn) =3D=3D 13))); break; } - if (is_branch) + if (is_branch !=3D 0) { - branch_bp =3D loc + mips32_relative_offset (insn) + 4; + /* Is this a special PC21_S2 branch? */ + if (is_branch =3D=3D 2) + branch_bp =3D loc + mips32_relative_offset21 (insn) + 4; + else + branch_bp =3D loc + mips32_relative_offset (insn) + 4; if (last_breakpoint >=3D 1) return {}; /* More than one branch found, fallback to the standard single-step code. */ @@ -4049,12 +4475,12 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdb= arch, CORE_ADDR pc) last_breakpoint++; } =20 - if (itype_op (insn) =3D=3D SC_OPCODE || itype_op (insn) =3D=3D SCD_O= PCODE) + if (is_sc_insn (gdbarch, insn)) break; } =20 /* Assume that the atomic sequence ends with a sc/scd instruction. */ - if (itype_op (insn) !=3D SC_OPCODE && itype_op (insn) !=3D SCD_OPCODE) + if (!is_sc_insn (gdbarch, insn)) return {}; =20 loc +=3D MIPS_INSN32_SIZE; @@ -4203,7 +4629,7 @@ micromips_deal_with_atomic_sequence (struct gdbarch *= gdbarch, } break; } - if (is_branch) + if (is_branch !=3D 0) { if (last_breakpoint >=3D 1) return {}; /* More than one branch found, fallback to the @@ -4279,8 +4705,14 @@ mips_about_to_return (struct gdbarch *gdbarch, CORE_= ADDR pc) gdb_assert (mips_pc_is_mips (pc)); =20 insn =3D mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); - hint =3D 0x7c0; - return (insn & ~hint) =3D=3D 0x3e00008; /* jr(.hb) $ra */ + /* Mask the hint and the jalr/jr bit. */ + hint =3D 0x7c1; + + if (is_mipsr6_isa (gdbarch) && insn =3D=3D 0xd81f0000) /* jrc $31 */ + return 1; + + /* jr(.hb) $ra and "jalr(.hb) $ra" */ + return ((insn & ~hint) =3D=3D 0x3e00008); } =20 /* This fencepost looks highly suspicious to me. Removing it also @@ -6798,7 +7230,9 @@ mips32_stack_frame_destroyed_p (struct gdbarch *gdbar= ch, CORE_ADDR pc) =20 if (high_word !=3D 0x27bd /* addiu $sp,$sp,offset */ && high_word !=3D 0x67bd /* daddiu $sp,$sp,offset */ - && inst !=3D 0x03e00008 /* jr $ra */ + && (inst & ~0x1) !=3D 0x03e00008 /* jr $31 or jalr $0, $31 */ + && (!is_mipsr6_isa (gdbarch) + || inst !=3D 0xd81f0000) /* jrc $31 */ && inst !=3D 0x00000000) /* nop */ return 0; } @@ -7176,6 +7610,7 @@ mips32_instruction_has_delay_slot (struct gdbarch *gd= barch, ULONGEST inst) int op; int rs; int rt; + bool is_mipsr6 =3D is_mipsr6_isa (gdbarch); =20 op =3D itype_op (inst); if ((inst & 0xe0000000) !=3D 0) @@ -7183,15 +7618,23 @@ mips32_instruction_has_delay_slot (struct gdbarch *= gdbarch, ULONGEST inst) rs =3D itype_rs (inst); rt =3D itype_rt (inst); return (is_octeon_bbit_op (op, gdbarch) - || op >> 2 =3D=3D 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ - || op =3D=3D 29 /* JALX: bits 011101 */ + || (op >> 1 =3D=3D 10) /* BEQL, BNEL: bits 01010x */ + || (op >> 1 =3D=3D 11 && rt =3D=3D 0) /* BLEZL, BGTZL: bits 01011x = */ + || (!is_mipsr6 && op =3D=3D 29) /* JALX: bits 011101 */ || (op =3D=3D 17 && (rs =3D=3D 8 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ - || (rs =3D=3D 9 && (rt & 0x2) =3D=3D 0) + || (!is_mipsr6 && rs =3D=3D 9 && (rt & 0x2) =3D=3D 0) /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ - || (rs =3D=3D 10 && (rt & 0x2) =3D=3D 0)))); + || (!is_mipsr6 && rs =3D=3D 10 && (rt & 0x2) =3D=3D 0))) /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ + || (is_mipsr6 + && ((op =3D=3D 17 + && (rs =3D=3D 9 /* BC1EQZ: 010001 01001 */ + || rs =3D=3D 13)) /* BC1NEZ: 010001 01101 */ + || (op =3D=3D 18 + && (rs =3D=3D 9 /* BC2EQZ: 010010 01001 */ + || rs =3D=3D 13))))); /* BC2NEZ: 010010 01101 */ } else switch (op & 0x07) /* extract bits 28,27,26 */ @@ -7210,7 +7653,11 @@ mips32_instruction_has_delay_slot (struct gdbarch *g= dbarch, ULONGEST inst) || ((rt & 0x1e) =3D=3D 0x1c && rs =3D=3D 0)); /* BPOSGE32, BPOSGE64: bits 1110x */ break; /* end REGIMM */ - default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ + case 6: /* BLEZ */ + case 7: /* BGTZ */ + return (itype_rt (inst) =3D=3D 0); + break; + default: /* J, JAL, BEQ, BNE */ return 1; break; } @@ -7422,7 +7869,18 @@ mips_adjust_breakpoint_address (struct gdbarch *gdba= rch, CORE_ADDR bpaddr) =20 So, we'll use the second solution. To do this we need to know if the instruction we're trying to set the breakpoint on is in the - branch delay slot. */ + branch delay slot. + + A similar problem occurs for breakpoints on forbidden slots where + the trap will be reported for the branch with the BD bit set. + In this case it would be ideal to recover using solution 1 from + above as there is no problem with the branch being skipped + (since the forbidden slot only exists on not-taken branches). + However, the BD bit is not available in all scenarios currently + so instead we move the breakpoint on to the next instruction. + This means that it is not possible to stop on an instruction + that can be in a forbidden slot even if that instruction is + jumped to directly. */ =20 boundary =3D mips_segment_boundary (bpaddr); =20 @@ -7444,6 +7902,12 @@ mips_adjust_breakpoint_address (struct gdbarch *gdba= rch, CORE_ADDR bpaddr) prev_addr =3D bpaddr - 4; if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr)) bpaddr =3D prev_addr; + /* If the previous instruction has a forbidden slot, we have to + move the breakpoint to the following instruction to prevent + breakpoints in forbidden slots being reported as unknown + traps. */ + else if (mips32_insn_at_pc_has_forbidden_slot (gdbarch, prev_addr)) + bpaddr +=3D 4; } else { diff --git a/gdb/testsuite/gdb.arch/mips-64-r6.c b/gdb/testsuite/gdb.arch/m= ips-64-r6.c new file mode 100644 index 00000000000..e1a1dd041cc --- /dev/null +++ b/gdb/testsuite/gdb.arch/mips-64-r6.c @@ -0,0 +1,916 @@ +/* + Copyright 2023-2025 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#define xstr(s) str(s) +#define str(s) #s + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D macros from sim/testutils/mips/uti= ls-r6.inc =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ + +/* 58 is local label to exit with errcode !=3D 0, indicating error. */ +#define fp_assert(a, b) "beq " xstr (a) ", " xstr (b) ", 1f \n\t" \ + "nop \n\t" \ + "b 58f \n\t" \ + "nop \n\t" \ + "1: \n\t" + +/* Clobbers: $4,$6,$7. */ +#define r6ck_1r(inst, a, ret) \ + "li $4, " xstr (a) " \n\t" \ + "li $6, " xstr (ret) " \n\t" \ + xstr (inst) " $7, $4 \n\t" \ + fp_assert ($6, $7) + +/* Clobbers: $4,$6,$7. */ +#define r6ck_1dr(inst, a, ret) \ + "ld $4, " xstr (a) " \n\t" \ + "ld $6, " xstr (ret) " \n\t" \ + xstr (inst) " $7, $4 \n\t" \ + fp_assert ($6, $7) + +/* Clobbers: $4,$5,$6,$7. */ +#define r6ck_2r(inst, a, b, ret) \ + "li $4, " xstr (a) " \n\t" \ + "li $5, " xstr (b) " \n\t" \ + "li $6, " xstr (ret) " \n\t" \ + xstr (inst) " $7, $4, $5 \n\t" \ + fp_assert ($6, $7) + +/* Clobbers: $4,$5,$6,$7. */ +#define r6ck_2dr(inst, a, b, ret) \ + "ld $4, " xstr (a) " \n\t" \ + "ld $5, " xstr (b) " \n\t" \ + "ld $6, " xstr (ret) " \n\t" \ + xstr (inst) " $7, $4, $5 \n\t" \ + fp_assert ($6, $7) + +/* Clobbers: $4,$5,$6,$7. */ +#define r6ck_2dr1i(inst, a, b, imm, ret) \ + "ld $4, " xstr (a) " \n\t" \ + "ld $5, " xstr (b) " \n\t" \ + "ld $6, " xstr (ret) " \n\t" \ + xstr (inst) " $7, $4, $5, " xstr (imm) " \n\t" \ + fp_assert ($6, $7) + +/* Clobbers: $4,$6,$7. */ +#define r6ck_1r1i(inst, a, imm, ret) \ + "li $4, " xstr (a) " \n\t" \ + "li $6, " xstr (ret) " \n\t" \ + xstr (inst) " $7, $4, " xstr (imm) " \n\t" \ + fp_assert ($6, $7) + +/* Clobbers: $4,$6,$7. */ +#define r6ck_1dr1i(inst, a, imm, ret) \ + "ld $4, " xstr (a) " \n\t" \ + "ld $6, " xstr (ret) " \n\t" \ + xstr (inst) " $7, $4, " xstr (imm) " \n\t" \ + fp_assert ($6, $7) + +/* Clobbers: $4,$6. */ +#define r6ck_0dr1i(inst, a, imm, ret) \ + "ld $4, " xstr (a) " \n\t" \ + "ld $6, " xstr (ret) " \n\t" \ + xstr (inst) " $4, $4, " xstr (imm) " \n\t" \ + fp_assert ($6, $4) + +/* Clobbers: $4,$5,$6,$7. */ +#define r6ck_2r1i(inst, a, b, imm, ret) \ + "li $4, " xstr (a) " \n\t" \ + "li $5, " xstr (b) " \n\t" \ + "li $6, " xstr (ret) " \n\t" \ + xstr (inst) " $7, $4, $5, " xstr (imm) " \n\t" \ + fp_assert ($6, $7) + +/* Clobbers: $4,$5,$6,$7,$8,$f2,$f4,$f6. */ +#define r6ck_3s(inst, a, b, c, ret) \ + "li $4, " xstr (a) " \n\t" \ + "li $5, " xstr (b) " \n\t" \ + "li $6, " xstr (c) " \n\t" \ + "li $7, " xstr (ret) " \n\t" \ + "mtc1 $4, $f2 \n\t" \ + "mtc1 $5, $f4 \n\t" \ + "mtc1 $6, $f6 \n\t" \ + xstr (inst) " $f2, $f4, $f6 \n\t" \ + "mfc1 $8, $f2 \n\t" \ + fp_assert ($7, $8) + +/* Clobbers: $4,$5,$6,$7,$f2,$f4. */ +#define r6ck_2s(inst, a, b, ret) \ + "li $4, " xstr (a) " \n\t" \ + "li $5, " xstr (b) " \n\t" \ + "li $6, " xstr (ret) " \n\t" \ + "mtc1 $4, $f2 \n\t" \ + "mtc1 $5, $f4 \n\t" \ + xstr (inst) " $f2, $f4 \n\t" \ + "mfc1 $7, $f2 \n\t" \ + fp_assert ($6, $7) + +/* Clobbers: $4,$5,$6,$7,$8,$9,$10,$f2,$f4. */ +#define r6ck_2d(inst, a, b, ret) \ + ".data \n\t" \ + "1: .dword " xstr (a) " \n\t" \ + "2: .dword " xstr (b) " \n\t" \ + "3: .dword " xstr (ret) " \n\t" \ + ".text \n\t" \ + "dla $4, 1b \n\t" \ + "dla $5, 2b \n\t" \ + "dla $6, 3b \n\t" \ + "ldc1 $f2, 0($4) \n\t" \ + "ldc1 $f4, 0($5) \n\t" \ + "lw $7, 0($6) \n\t" \ + "lw $8, 4($6) \n\t" \ + xstr (inst) " $f2, $f4 \n\t" \ + "mfhc1 $9, $f2 \n\t" \ + "mfc1 $10, $f2 \n\t" \ + fp_assert ($7, $9) \ + fp_assert ($8, $10) + +/* Clobbers: $2,$4,$5,$6,$7,$8,$9,$10,$f2,$f4,$f6. */ +#define r6ck_3d(inst, a, b, c, ret) \ + ".data \n\t" \ + "1: .dword " xstr (a) " \n\t" \ + "2: .dword " xstr (b) " \n\t" \ + "3: .dword " xstr (c) " \n\t" \ + "4: .dword " xstr (ret) " \n\t" \ + ".text \n\t" \ + "dla $4, 1b \n\t" \ + "dla $5, 2b \n\t" \ + "dla $6, 3b \n\t" \ + "dla $2, 4b \n\t" \ + "ldc1 $f2, 0($4) \n\t" \ + "ldc1 $f4, 0($5) \n\t" \ + "ldc1 $f6, 0($6) \n\t" \ + "lw $7, 0($2) \n\t" \ + "lw $8, 4($2) \n\t" \ + xstr (inst) " $f2, $f4, $f6 \n\t" \ + "mfhc1 $9, $f2 \n\t" \ + "mfc1 $10, $f2 \n\t" \ + fp_assert ($7, $9) \ + fp_assert ($8, $10) + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D macros from sim/testutils/mips/tes= tutils.inc =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ + +/* Put value 'val' into register 'reg'. + Clobbers: None. */ +#define load32(reg, val) \ + "li " xstr (reg) ", " xstr (val) " \n\t" + +/* Check whether two registers contain the same value. + Clobbers: None. */ +#define checkreg(reg, expreg) \ + ".set push \n\t" \ + ".set noat \n\t" \ + ".set noreorder \n\t" \ + "beq " xstr (expreg) ", " xstr (reg) ", 901f \n\t" \ + "nop \n\t" \ + "b 58f \n\t" \ + "nop \n\t" \ + "901: \n\t" \ + ".set pop \n\t" + +/* Check if register 'reg' contains value 'val'. + Clobbers: $1. */ +#define check32(reg, val) \ + ".set push \n\t" \ + ".set noat \n\t" \ + load32 ($1, val) \ + checkreg (reg, $1) \ + ".set pop \n\t" + +/* Checkpair based on endianess + Clobbers: $1. */ +#define checkpair_xendian(lo, hi, base, ec, w) \ + ".set noat \n\t" \ + "lw $1, " xstr (ec) " \n\t" \ + "andi $1, $1, 0x1 \n\t" \ + "beqz $1, 2f \n\t" \ + ".set at \n\t" \ + "1: \n\t" \ + checkpair_be_##w (lo, hi, base) \ + "b 3f \n\t" \ + "nop \n\t" \ + "2: \n\t" \ + checkpair_le_##w (lo, hi, base) \ + "3: \n\t" + +/* Check hi-lo register pair against data stored at base+o1 and base+o2. + Clobbers: $1 - $5. */ +#define checkpair(lo, hi, base, w, o1, o2) \ + "move $2, " xstr (lo) " \n\t" \ + "move $3, " xstr (hi) " \n\t" \ + ".set noat \n\t" \ + "dla $1, " xstr (base) " \n\t" \ + "l" xstr (w) " $4, " xstr (o1) "($1) \n\t" \ + "l" xstr (w) " $5, " xstr (o2) "($1) \n\t" \ + ".set at \n\t" \ + checkreg ($2, $4) \ + checkreg ($3, $5) + +#define checkpair_le_d(lo, hi, base) \ + checkpair (lo, hi, base, w, 0, 4) + +#define checkpair_be_d(lo, hi, base) \ + checkpair (lo, hi, base, w, 4, 0) + +#define checkpair_le_q(lo, hi, base) \ + checkpair (lo, hi, base, d, 0, 8) + +#define checkpair_be_q(lo, hi, base) \ + checkpair (lo, hi, base, d, 8, 0) + +#define checkpair_qword(lo, hi, base, oe) \ + checkpair_xendian (lo, hi, base, oe, q) + +#define checkpair_dword(lo, hi, base, oe) \ + checkpair_xendian (lo, hi, base, oe, d) + +void +abort (void); + +/* Tests branch instructions. */ + +int +test_r6_branch (void) +{ +/* Using volatile to prevent certain optimizations which could cause + instruction deletion. + 'err' identifies instruction which (eventually) caused error. + (err =3D=3D 0) =3D=3D> all instructions executed successfully. */ + + volatile int err =3D -1; + volatile int a14 =3D 0xffffffff; + volatile int a13 =3D 0x123; + volatile int a12 =3D 0x45; + volatile int a7 =3D 0x45; + volatile int a8 =3D 0xfffffffe; + volatile int a9 =3D 2147483647; + volatile int a11 =3D 0; + volatile int a10 =3D 0; + + asm ( + ".set push \n\t" /* Create new scope for asm configuration. = */ + ".set noreorder \n\t" /* Don't allow reordering of instructions. = */ + "li %[err], 1 \n\t" + "bovc %[a12], %[a13], Lfail \n\t" /* BOVC */ + "nop \n\t" + "bovc %[a9], %[a13], L2 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L2: \n\t" + "li %[err], 2 \n\t" + "bnvc %[a9], %[a13], Lfail \n\t" /* BNVC */ + "nop \n\t" + "bnvc %[a12], %[a13], L3 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L3: \n\t" + "li %[err], 3 \n\t" + "beqc %[a12], %[a13], Lfail \n\t" /* BEQC */ + "nop \n\t" + "beqc %[a12], %[a7], L4 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L4: \n\t" + "li %[err], 4 \n\t" + "bnec %[a12], %[a7], Lfail \n\t" /* BNEC */ + "nop \n\t" + "bnec %[a12], %[a13], L5 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L5: \n\t" + "li %[err], 5 \n\t" + "bltc %[a13], %[a12], Lfail \n\t" /* BLTC */ + "nop \n\t" + "bltc %[a12], %[a13], L6 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L6: \n\t" + "L7: \n\t" + "li %[err], 7 \n\t" + "bgec %[a12], %[a13], Lfail \n\t" /* BGEC */ + "nop \n\t" + "bgec %[a13], %[a12], L8 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L8: \n\t" + "L9: \n\t" + "li %[err], 9 \n\t" + "bltuc %[a14], %[a13], Lfail \n\t" /* BLTUC */ + "nop \n\t" + "bltuc %[a8], %[a14], L10 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L10: \n\t" + "L11: \n\t" + "li %[err], 11 \n\t" + "bgeuc %[a13], %[a14], Lfail \n\t" /* BGEUC */ + "nop \n\t" + "bgeuc %[a14], %[a8], L12 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L12: \n\t" + "L13: \n\t" + "li %[err], 13 \n\t" + "bltzc %[a13], Lfail \n\t" /* BLTZC */ + "nop \n\t" + "bltzc %[a11], Lfail \n\t" + "nop \n\t" + "bltzc %[a14], L14 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L14: \n\t" + "li %[err], 14 \n\t" + "blezc %[a13], Lfail \n\t" /* BLEZC */ + "nop \n\t" + "blezc %[a11], L145 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L145: \n\t" + "blezc %[a14], L15 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L15: \n\t" + "li %[err], 15 \n\t" + "bgezc %[a8], Lfail \n\t" /* BGEZC */ + "nop \n\t" + "bgezc %[a11], L155 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L155: \n\t" + "bgezc %[a13], L16 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L16: \n\t" + "li %[err], 16 \n\t" + "bgtzc %[a8], Lfail \n\t" /* BGTZC */ + "nop \n\t" + "bgtzc %[a11], Lfail \n\t" + "nop \n\t" + "bgtzc %[a13], L17 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "li %[a10], 0 \n\t" + "L17: \n\t" + "li %[err], 17 \n\t" + "blezalc %[a12], Lfail \n\t" /* BLEZALC */ + "nop \n\t" + "blezalc %[a11], Lret \n\t" + "li %[a10], 1 \n\t" + "beqzc %[a10], L175 \n\t" /* BEQZC */ + "nop \n\t" + "li %[err], 8531 \n\t" + "b Lfail \n\t" + "nop \n\t" + "L175: \n\t" + "li %[err], 23531 \n\t" + "blezalc %[a14], Lret \n\t" + "li %[a10], 1 \n\t" + "beqzc %[a10], L18 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L18: \n\t" + "li %[err], 18 \n\t" + "bgezalc %[a14], Lfail \n\t" /* BGEZALC */ + "nop \n\t" + "bgezalc %[a11], Lret \n\t" + "li %[a10], 1 \n\t" + "beqzc %[a10], L185 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L185: \n\t" + "bgezalc %[a12], Lret \n\t" + "li %[a10], 1 \n\t" + "beqzc %[a10], L19 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L19: \n\t" + "li %[err], 19 \n\t" + "bgtzalc %[a14], Lfail \n\t" /* BGTZALC */ + "nop \n\t" + "bgtzalc %[a11], Lfail \n\t" + "nop \n\t" + "bgtzalc %[a12], Lret \n\t" + "li %[a10], 1 \n\t" + "beqzc %[a10], L20 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L20: \n\t" + "li %[err], 20 \n\t" + "bltzalc %[a12], Lfail \n\t" /* BLTZALC */ + "nop \n\t" + "bltzalc %[a11], Lfail \n\t" + "nop \n\t" + "bltzalc %[a14], Lret \n\t" + "li %[a10], 1 \n\t" + "beqzc %[a10], L21 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L21: \n\t" + "li %[err], 21 \n\t" + "bc L22 \n\t" /* BC */ + "b Lfail \n\t" + "nop \n\t" + "L22: \n\t" + "li %[err], 22 \n\t" + "balc Lret \n\t" /* BALC */ + "li %[a10], 1 \n\t" + "beqzc %[a10], L23 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L23: \n\t" + "li %[err], 23 \n\t" + "jal GetPC \n\t" /* JAL */ + "nop \n\t" + "jic $6, 4 \n\t" /* JIC */ + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L24: \n\t" + "li %[err], 24 \n\t" + "li %[a10], 1 \n\t" + "jal GetPC \n\t" + "nop \n\t" + "jialc $6, 20 \n\t" /* JIALC */ + "nop \n\t" + "beqzc %[a10], L25 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "LJIALCRET: \n\t" + "li %[a10], 0 \n\t" + "jr $31 \n\t" /* JR */ + "nop \n\t" + "L25: \n\t" + "li %[err], 25 \n\t" + "jal GetPC \n\t" + "nop \n\t" + "move %[a11], $6 \n\t" + "nal \n\t" + "nop \n\t" + "addiu %[a11], 12 \n\t" /* ADDIU */ + "beqc %[a11], $31, L26 \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "L26: \n\t" + "li %[err], 26 \n\t" + "balc Lret \n\t" + "li %[a10], 1 \n\t" + "beqzc %[a10], Lend \n\t" + "nop \n\t" + "b Lfail \n\t" + "nop \n\t" + "Lret: \n\t" + "li %[a10], 0 \n\t" + "daddiu $31, 4 \n\t" /* DADDIU */ + "jrc $31 \n\t" /* JRC */ + "nop \n\t" + "GetPC: \n\t" + "move $6, $31 \n\t" + "jr $31 \n\t" + "Lend: \n\t" + "li %[err], 0 \n\t" + "Lfail: \n\t" + ".set pop \n\t" /* Restore previous config */ + : [err] "+r"(err), [a14] "+r"(a14), [a13] "+r"(a13), [a12] "+r"(a12), + [a7] "+r"(a7), [a8] "+r"(a8), [a9] "+r"(a9), [a10] "+r"(a10), + [a11] "+r"(a11) + : /* inputs */ + : "$31", "$6" /* clobbers */ + ); + + return err; +} + +/* Tests forbidden slot branching i.e. conditional compact branch + instructions. */ + +int +test_r6_forbidden (void) +{ + volatile int err =3D -1; + volatile int a4 =3D 0; + volatile int a2 =3D 0; + volatile int a1 =3D 0; + + asm ( + ".set push \n\t" + ".set noreorder \n\t" +/* Test if FS is ignored when branch is taken */ + "li %[err], 1 \n\t" + "li %[a4], 0 \n\t" + "beqzalc %[a4], L41 \n\t" + "li %[err], -85 \n\t" + "L42: \n\t" + "b Lfail2 \n\t" + "nop \n\t" + "L41: \n\t" + "blez %[err], Lfail2 \n\t" +/* Test if FS is used when branch is not taken */ + "li %[err], 2 \n\t" + "li %[a4], 1 \n\t" + "blezc %[a4], L43 \n\t" + "addiu %[a4], %[a4], 1 \n\t" + "li %[a2], 2 \n\t" + "beq %[a4], %[a2], L44 \n\t" + "nop \n\t" + "L43: \n\t" + "nop \n\t" + "b Lfail2 \n\t" + "nop \n\t" + "L44: \n\t" + "li %[err], 3 \n\t" + "li %[a4], 3 \n\t" + "beqzalc %[a4], Lfail2 \n\t" +/* Note: 'bc L45' instead nop would cause SegFault: Illegal instruction: + Forbidden slot causes an error when it contains a branch. */ + "nop \n\t" + "b Lend2 \n\t" + "nop \n\t" + "L45: \n\t" + "nop \n\t" + "b Lfail2 \n\t" + "nop \n\t" + "Lend2: \n\t" + "li %[err], 0 \n\t" + "Lfail2: \n\t" + "nop \n\t" + ".set pop \n\t" + : [err] "+r" (err), [a4] "+r"(a4), [a2] "+r"(a2), [a1] "+r"(a1) /* outpu= ts */ + : /* inputs */ + : "$31" /* clobbers */ + ); + + return err; +} + +int +test_r6_64 (void) +{ + volatile int err =3D 0; + + asm ( + ".set push \n\t" + ".set noreorder \n\t" + ".data \n\t" + "dval: .dword 0xaa55bb66cc77dd88 \n\t" + "d1: .dword 0xaaaabbbbccccdddd \n\t" + "d5: .dword 0x00000000000000dd \n\t" + "d7: .dword 0xeeeeffff00001111 \n\t" + "d8: .dword 0xbbccccddddeeeeff \n\t" + "d9: .dword 0x000000ddaaaabbbb \n\t" + "dval1: .word 0x1234abcd \n\t" + "dval2: .word 0xffee0000 \n\t" + "dval3: .dword 0xffffffffffffffff \n\t" + " .fill 240,1,0 \n\t" + "dval4: .dword 0x5555555555555555 \n\t" + " .fill 264,1,0 \n\t" + +/* Register $11 stores instruction currently being tested and hence + * identifies error if it occurs. */ + ".text \n\t" + + "li $11, 1 \n\t" /* Test DALIGN */ + r6ck_2dr1i (dalign, d7, d1, 3, d8) + r6ck_2dr1i (dalign, d1, d5, 4, d9) + + "li $11, 2 \n\t" /* Test LDPC */ + "ld $5, dval \n\t" + "nop \n\t" + "ldpc $4, dval \n\t" + fp_assert ($4, $5) + + "li $11, 3 \n\t" /* Test LWUPC */ + "lwu $5, dval1 \n\t" + "lwupc $4, dval1 \n\t" + fp_assert ($4, $5) + "lwu $5, dval2 \n\t" + "lwupc $4, dval2 \n\t" + fp_assert ($4, $5) + + "li $11, 4 \n\t" /* Test LLD */ + "ld $5, dval3 \n\t" + "dla $3, dval4 \n\t" + "lld $4, -248($3) \n\t" + fp_assert ($4, $5) + + "li $11, 5 \n\t" /* Test SCD */ + "lld $4, -248($3) \n\t" + "dli $4, 0xafaf \n\t" + "scd $4, -248($3) \n\t" + "ld $5, dval3 \n\t" + "dli $4, 0xafaf \n\t" + fp_assert ($4, $5) + + "Lend3: \n\t" + "li $11, 0 \n\t" + "58: \n\t" + "move %[err], $11 \n\t" + ".set pop \n\t" + : [err] "+r" (err) /* outputs */ + : /* inputs */ + : "$3", "$4", "$5", "$6", "$7", "$11" /* clobbers */ + ); + + return err; +} + +int +test_r6 (void) +{ + volatile int err =3D 0; + + asm ( + ".set push \n\t" + ".set noreorder \n\t" + ".data \n\t" + "dval_1: .word 0xabcd1234 \n\t" + "dval_2: .word 0x1234eeff \n\t" + ".fill 248,1,0 \n\t" + "dval_3: .word 0x55555555 \n\t" + ".fill 260,1,0 \n\t" + "dval_4: .word 0xaaaaaaaa \n\t" + ".text \n\t" + "li $11, 1 \n\t" /* ADDIUPC */ + "jal GetPC_2 \n\t" + "nop \n\t" + "addiu $4, $6, 8 \n\t" + "addiupc $5, 4 \n\t" + fp_assert ($4, $5) + + "li $11, 2 \n\t" /* AUIPC */ + "jal GetPC_2 \n\t" + "nop \n\t" + "addiu $4, $6, 8 \n\t" + "aui $4, $4, 8 \n\t" + "auipc $5, 8 \n\t" + fp_assert ($4, $5) + + "li $11, 3 \n\t" /* ALUIPC */ + "jal GetPC_2 \n\t" + "nop \n\t" + "addiu $4, $6, 16 \n\t" + "aui $4, $4, 8 \n\t" + "li $7, 0xffff0000 \n\t" + "and $4, $4, $7 \n\t" + "aluipc $5, 8 \n\t" + fp_assert ($4, $5) + + "li $11, 4 \n\t" /* LWPC */ + "lw $5, dval_1 \n\t" + "lwpc $4, dval_1 \n\t" + fp_assert ($4, $5) + "lw $5, dval_2 \n\t" + "lwpc $4, dval_2 \n\t" + fp_assert ($4, $5) + +/* Testing LL follows. + * NOTE: May be redundant because SC already contains LL in its test. */ + "li $11, 5 \n\t" + "lw $5, dval_2 \n\t" + "dla $3, dval_3 \n\t" + "ll $4, -252($3) \n\t" + fp_assert ($4, $5) + + "li $11, 6 \n\t" /* LL-SC sequence */ + "ll $4, -252($3) \n\t" + "li $4, 0xafaf \n\t" + "sc $4, -252($3) \n\t" + "lw $5, dval_2 \n\t" + "li $4, 0xafaf \n\t" + fp_assert ($4, $5) + "b Lend4 \n\t" + "nop \n\t" + "GetPC_2: \n\t" + "move $6, $31 \n\t" + "jr $31 \n\t" + "Lend4: \n\t" + "li $11, 0 \n\t" + "58: \n\t" + "move %[err], $11 \n\t" + ".set pop \n\t" + : [err] "+r"(err) /* outputs */ + : /* inputs */ + : "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", + "$11", "$31" /* clobbers */ + ); + + return err; +} + +/* For fpu-branching testing, bc1eq/eqz are enough. */ + +int +test_r6_fpu (void) +{ + volatile int err =3D 0; + + asm ( + ".set push \n\t" + ".set noreorder \n\t" +/* Test qNaN format is 754-2008 */ + "li $11, 1 \n\t" + "li $4, 0x0 \n\t" + "li $5, 0x0 \n\t" + "li $6, 0x7fc00000 \n\t" + "mtc1 $4, $f2 \n\t" + "mtc1 $5, $f4 \n\t" + "div.s $f6, $f2, $f4 \n\t" + "mfc1 $8, $f6 \n\t" + fp_assert ($6, $8) + + "li $11, 2 \n\t" /* bc1eqz */ + "li $10, 0x01 \n\t" + "mtc1 $10, $f2 \n\t" + "mtc1 $0, $f4 \n\t" + "bc1eqz $f2, 58f \n\t" + "nop \n\t" + "bc1eqz $f4, L62 \n\t" + "nop \n\t" + "b 58f \n\t" + "nop \n\t" +"L62: \n\t" + "li $11, 3 \n\t" /* bc1nez */ + "bc1nez $f4, 58f \n\t" + "nop \n\t" + "bc1nez $f2, Lend8 \n\t" + "nop \n\t" + "b 58f \n\t" + "nop \n\t" +"Lend8: \n\t" + "li $11, 0 \n\t" + "58: \n\t" + "move %[err], $11 \n\t" + ".set pop \n\t" + : [err] "+r"(err) /* outputs */ + : /* inputs */ + : "$4", "$5", "$6", "$8", "$10", "$11", "$31", + "$f2", "$f4", "$f6" /* clobbers */ + ); + + return err; +} + +/* R6 specific tests for mips64 (64-bit). */ + +int +test_r6_llsc_dp (void) +{ + volatile int err =3D 0; + + asm ( + ".set push \n\t" + ".set noreorder \n\t" + ".data \n\t" + ".align 16 \n\t" + "test_data: \n\t" + ".word 0xaaaaaaaa \n\t" + ".word 0xbbbbbbbb \n\t" + ".word 0xcccccccc \n\t" + ".word 0xdddddddd \n\t" + ".align 16 \n\t" + "end_check: \n\t" + ".byte 0 \n\t" + ".byte 0 \n\t" + ".byte 0 \n\t" + ".byte 0x1 \n\t" + ".text \n\t" + "li $11, 1 \n\t" /* LLWP */ + "llwp $2, $3, test_data \n\t" + checkpair_dword ($2, $3, test_data, end_check) + "sll $2, $2, 1 \n\t" + "srl $3, $3, 1 \n\t" + "move $s0, $2 \n\t" + "scwp $2, $3, test_data \n\t" + check32 ($2, 1) + checkpair_dword ($s0, $3, test_data, end_check) + /* Test SCWP, done */ + "li $11, 2 \n\t" + "li $11, 3 \n\t" /* LLDP */ + "lldp $2, $3, test_data \n\t" + checkpair_qword ($2, $3, test_data, end_check) + "dsll $2, $2, 1 \n\t" + "dsrl $3, $3, 1 \n\t" + "move $s0, $2 \n\t" + "scdp $2, $3, test_data \n\t" + check32 ($2, 1) + checkpair_qword ($s0, $3, test_data, end_check) + "li $11, 4 \n\t" /* SCDP done= */ + "Lend5: \n\t" + "li $11, 0 \n\t" + "58: \n\t" + "move %[err], $11 \n\t" + ".set pop \n\t" + : [err] "+r"(err) /* outputs */ + : /* inputs */ + : "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", + "$31", "$s0" /* clobbers */ + ); + + return err; +} + +/* R6 specific tests for mips32 (32-bit). */ + +int +test_r6_llsc_wp (void) +{ + volatile int err =3D 0; + + asm ( + ".set push \n\t" + ".set noreorder \n\t" + ".data \n\t" + ".align 8 \n\t" + "test_data_2: \n\t" + ".word 0xaaaaaaaa \n\t" + ".word 0xbbbbbbbb \n\t" + ".align 8 \n\t" + "end_check_2: \n\t" + ".byte 0 \n\t" + ".byte 0 \n\t" + ".byte 0 \n\t" + ".byte 0x1 \n\t" + ".text \n\t" + "li $11, 1 \n\t" /* Test LLWP= */ + "llwp $2, $3, test_data_2 \n\t" + checkpair_dword ($2, $3, test_data_2, end_check_2) + "sll $2, $2, 1 \n\t" + "srl $3, $3, 1 \n\t" + "move $s0, $2 \n\t" + "scwp $2, $3, test_data_2 \n\t" + check32 ($2, 1) + checkpair_dword ($s0, $3, test_data_2, end_check_2) +/* Test SCWP, done. */ + "li $11, 2 \n\t" + "Lend6: \n\t" + "li $11, 0 \n\t" + "58: \n\t" + "move %[err], $11 \n\t" + ".set pop \n\t" + : [err] "+r"(err) /* outputs */ + : /* inputs */ + : "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", + "$11", "$31", "$s0" /* clobbers */ + ); + + return err; +} + +/* If any test_r6_* function returns non-zero, it's a failure. */ +#define EXPECT(X) if ((X)) abort (); + +int +main (void) +{ + EXPECT (test_r6_branch ()); + + EXPECT (test_r6_forbidden ()); + + EXPECT (test_r6_64 ()); + + EXPECT (test_r6 ()); + + EXPECT (test_r6_fpu ()); + + EXPECT (test_r6_llsc_dp ()); + + EXPECT (test_r6_llsc_wp ()); + + return 0; +} diff --git a/gdb/testsuite/gdb.arch/mips-64-r6.exp b/gdb/testsuite/gdb.arch= /mips-64-r6.exp new file mode 100644 index 00000000000..710da94c542 --- /dev/null +++ b/gdb/testsuite/gdb.arch/mips-64-r6.exp @@ -0,0 +1,76 @@ +# Copyright (C) 2023-2025 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see . + +################################################################ +################## MIPS Release 6 patch tests ################## +################################################################ + +# Send 'si' to gdb until inferior exits. +proc stepi {} { + global gdb_prompt + set timeout [get_largest_timeout] + set start [timestamp] + while { [timestamp] - $start < 3*$timeout } { + gdb_test_multiple "stepi" "" { + -re ".*exited normally.*" { + pass "success" + return + } + -re ".*The program is not being run.*" { + fail "failure" + return + } + -re ".*Breakpoint.*test_.*$gdb_prompt $" { + } + -re "$gdb_prompt.*" { + } + } + } + fail "test failed" + return +} + +require {istarget "*mips*"} + +set testfile "mips-64-r6" +set srcfile ${testfile}.c +set binfile ${objdir}/${subdir}/${testfile} + +if {[prepare_for_testing "failed to prepare" "${binfile}" "${srcfile}" {de= bug nowarnings}]} { + untested "failed to prepare" + return +} + +# Native needs run. +if { ![runto_main] } { + untested "couldn't run to main" + return +} + +set tests "" +foreach n [list "r6_branch" "r6_forbidden" "r6_64" "r6" "r6_fpu" "r6_llsc_= dp" "r6_llsc_wp"] { + lappend tests "test_$n" +} + +# Put breakpoint on each test-function +foreach func $tests { + if {![gdb_breakpoint "$func"]} { + untested "couldn't put breakpoint to $func" + return + } +} + +# Step through the binary +stepi --=20 2.34.1