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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: htecgroup.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PR3PR09MB4361.eurprd09.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5915440d-6b81-4341-c439-08dd50e58b5c X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Feb 2025 13:01:37.2084 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 9f85665b-7efd-4776-9dfe-b6bfda2565ee X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Zgg2CUUjpjOgsJJGS8BjoJNcM6nO1PCuJuqJO1D8Q2oX3eMvbz//nepoXKIOz2UPnk8XO3p6NN0msq8OyiomXJkYTP8qkpuS6zzJGX1yeuE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR3PR09MB4378 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org Format mips-tdep.c code as described on links: https://sourceware.org/gdb/wiki/Internals%20GDB-C-Coding-Standards https://www.gnu.org/prep/standards/standards.html#Comments --- gdb/mips-tdep.c | 395 +++++++++++++++++++++++++++--------------------- 1 file changed, 221 insertions(+), 174 deletions(-) diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c index a28c99d3366..dbf0b1aa5df 100644 --- a/gdb/mips-tdep.c +++ b/gdb/mips-tdep.c @@ -1,6 +1,6 @@ /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debug= ger. =20 - Copyright (C) 1988-2024 Free Software Foundation, Inc. + Copyright (C) 1988-2025 Free Software Foundation, Inc. =20 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. @@ -76,8 +76,8 @@ static int mips16_insn_at_pc_has_delay_slot (struct gdbar= ch *gdbarch, static void mips_print_float_info (struct gdbarch *, struct ui_file *, const frame_info_ptr &, const char *); =20 -/* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ -/* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ +/* A useful bit in the CP0 status register (MIPS_PS_REGNUM). + This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ #define ST0_FR (1 << 26) =20 /* The sizes of floating point registers. */ @@ -220,6 +220,7 @@ static std::string mips_disassembler_options; to the ABI we have selected, perhaps via a `set mips abi ...' override, rather than ones inferred from the ABI set in the ELF headers of the binary file selected for debugging. */ + static const char mips_disassembler_options_o32[] =3D "gpr-names=3D32"; static const char mips_disassembler_options_n32[] =3D "gpr-names=3Dn32"; static const char mips_disassembler_options_n64[] =3D "gpr-names=3D64"; @@ -633,7 +634,6 @@ static const char * const mips_linux_reg_names[NUM_MIPS= _PROCESSOR_REGS] =3D { "fsr", "fir" }; =20 - /* Return the name of the register corresponding to REGNO. */ static const char * mips_register_name (struct gdbarch *gdbarch, int regno) @@ -657,7 +657,7 @@ mips_register_name (struct gdbarch *gdbarch, int regno) =20 enum mips_abi abi =3D mips_abi (gdbarch); =20 - /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,= =20 + /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, but then don't make the raw register names visible. This (upper) range of user visible register numbers are the pseudo-registers. =20 @@ -668,6 +668,7 @@ mips_register_name (struct gdbarch *gdbarch, int regno) configured to be 32-bits wide. The registers that the user sees - the pseudo registers - match the users expectations given the programming model being used. */ + int rawnum =3D regno % gdbarch_num_regs (gdbarch); if (regno < gdbarch_num_regs (gdbarch)) return ""; @@ -1005,7 +1006,7 @@ mips_value_to_register (const frame_info_ptr &frame, = int regnum, size_t len =3D type->length (); frame_info_ptr next_frame =3D get_next_frame_sentinel_okay (frame); =20 - /* Sign extend values, irrespective of type, that are stored to=20 + /* Sign extend values, irrespective of type, that are stored to a 64-bit general purpose register. (32-bit unsigned values are stored as signed quantities within a 64-bit register. When performing an operation, in compiled code, that combines @@ -1074,21 +1075,29 @@ mips_register_type (struct gdbarch *gdbarch, int re= gnum) else if (gdbarch_osabi (gdbarch) !=3D GDB_OSABI_LINUX && rawnum >=3D MIPS_FIRST_EMBED_REGNUM && rawnum <=3D MIPS_LAST_EMBED_REGNUM) - /* The pseudo/cooked view of the embedded registers is always - 32-bit. The raw view is handled below. */ - return builtin_type (gdbarch)->builtin_int32; + { + /* The pseudo/cooked view of the embedded registers is always + 32-bit. The raw view is handled below. */ + return builtin_type (gdbarch)->builtin_int32; + } else if (tdep->mips64_transfers_32bit_regs_p) - /* The target, while possibly using a 64-bit register buffer, - is only transferring 32-bits of each integer register. - Reflect this in the cooked/pseudo (ABI) register value. */ - return builtin_type (gdbarch)->builtin_int32; + { + /* The target, while possibly using a 64-bit register buffer, + is only transferring 32-bits of each integer register. + Reflect this in the cooked/pseudo (ABI) register value. */ + return builtin_type (gdbarch)->builtin_int32; + } else if (mips_abi_regsize (gdbarch) =3D=3D 4) - /* The ABI is restricted to 32-bit registers (the ISA could be - 32- or 64-bit). */ - return builtin_type (gdbarch)->builtin_int32; + { + /* The ABI is restricted to 32-bit registers (the ISA could be + 32- or 64-bit). */ + return builtin_type (gdbarch)->builtin_int32; + } else - /* 64-bit ABI. */ - return builtin_type (gdbarch)->builtin_int64; + { + /* 64-bit ABI. */ + return builtin_type (gdbarch)->builtin_int64; + } } } =20 @@ -1236,6 +1245,7 @@ mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR= memaddr) elfread.c in the high bit of the info field. Use this to decide if the function is MIPS16. Otherwise if bit 0 of the address is set, then ELF file flags will tell if this is a MIPS16 function. */ + bound_minimal_symbol sym =3D lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); if (sym.minsym) @@ -1254,6 +1264,7 @@ mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_A= DDR memaddr) if the function is microMIPS. Otherwise if bit 0 of the address is set, then ELF file flags will tell if this is a microMIPS function. */ + bound_minimal_symbol sym =3D lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); if (sym.minsym) @@ -1273,6 +1284,7 @@ mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memad= dr) this to decide if the function is MIPS16 or microMIPS or normal MIPS. Otherwise if bit 0 of the address is set, then ELF file flags will tell if this is a MIPS16 or a microMIPS function. */ + bound_minimal_symbol sym =3D lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); if (sym.minsym) @@ -1566,7 +1578,7 @@ mips_insn_size (enum mips_isa isa, ULONGEST insn) else return MIPS_INSN16_SIZE; case ISA_MIPS: - return MIPS_INSN32_SIZE; + return MIPS_INSN32_SIZE; } internal_error (_("invalid ISA")); } @@ -1593,8 +1605,10 @@ mips32_bc1_pc (struct gdbarch *gdbarch, struct regca= che *regcache, int cond; =20 if (fcsr =3D=3D -1) - /* No way to handle; it'll most likely trap anyway. */ - return pc; + { + /* No way to handle; it'll most likely trap anyway. */ + return pc; + } =20 fcs =3D regcache_raw_get_unsigned (regcache, fcsr); cond =3D ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); @@ -1626,10 +1640,10 @@ is_octeon_bbit_op (int op, struct gdbarch *gdbarch) { if (!is_octeon (gdbarch)) return 0; - /* BBIT0 is encoded as LWC2: 110 010. */ - /* BBIT032 is encoded as LDC2: 110 110. */ - /* BBIT1 is encoded as SWC2: 111 010. */ - /* BBIT132 is encoded as SDC2: 111 110. */ + /* BBIT0 is encoded as LWC2: 110 010. + BBIT032 is encoded as LDC2: 110 110. + BBIT1 is encoded as SWC2: 111 010. + BBIT132 is encoded as SDC2: 111 110. */ if (op =3D=3D 50 || op =3D=3D 54 || op =3D=3D 58 || op =3D=3D 62) return 1; return 0; @@ -1647,12 +1661,11 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc) int op; inst =3D mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); op =3D itype_op (inst); - if ((inst & 0xe0000000) !=3D 0) /* Not a special, jump or branch - instruction. */ + if ((inst & 0xe0000000) !=3D 0) /* Not a special, jump or branch instruc= tion. */ { if (op >> 2 =3D=3D 5) - /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ { + /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ switch (op & 0x03) { case 0: /* BEQL */ @@ -1668,20 +1681,26 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc) } } else if (op =3D=3D 17 && itype_rs (inst) =3D=3D 8) - /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ - pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1); + { + /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ + pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1); + } else if (op =3D=3D 17 && itype_rs (inst) =3D=3D 9 && (itype_rt (inst) & 2) =3D=3D 0) - /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ - pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2); + { + /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ + pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2); + } else if (op =3D=3D 17 && itype_rs (inst) =3D=3D 10 && (itype_rt (inst) & 2) =3D=3D 0) - /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ - pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4); + { + /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ + pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4); + } else if (op =3D=3D 29) - /* JALX: 011101 */ - /* The new PC will be alternate mode. */ { + /* JALX: 011101 + The new PC will be alternate mode. */ unsigned long reg; =20 reg =3D jtype_target (inst) << 2; @@ -1695,28 +1714,33 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc) branch_if =3D op =3D=3D 58 || op =3D=3D 62; bit =3D itype_rt (inst); =20 - /* Take into account the *32 instructions. */ if (op =3D=3D 54 || op =3D=3D 62) - bit +=3D 32; + { + /* Take into account the *32 instructions. */ + bit +=3D 32; + } =20 if (((regcache_raw_get_signed (regcache, itype_rs (inst)) >> bit) & 1) =3D=3D branch_if) pc +=3D mips32_relative_offset (inst) + 4; else - pc +=3D 8; /* After the delay slot. */ + { + /* After the delay slot. */ + pc +=3D 8; + } } =20 else pc +=3D 4; /* Not a branch, next instruction is easy. */ } else - { /* This gets way messy. */ - - /* Further subdivide into SPECIAL, REGIMM and other. */ + { + /* This gets way messy. + Further subdivide into SPECIAL, REGIMM and other. */ switch (op & 0x07) /* Extract bits 28,27,26. */ { - case 0: /* SPECIAL */ + case 0: /* SPECIAL */ op =3D rtype_funct (inst); switch (op) { @@ -1725,7 +1749,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR = pc) /* Set PC to that address. */ pc =3D regcache_raw_get_signed (regcache, rtype_rs (inst)); break; - case 12: /* SYSCALL */ + case 12: /* SYSCALL */ { mips_gdbarch_tdep *tdep =3D gdbarch_tdep (gdbarch); @@ -1740,10 +1764,10 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc) pc +=3D 4; } =20 - break; /* end SPECIAL */ - case 1: /* REGIMM */ + break; /* end SPECIAL */ + case 1: /* REGIMM */ { - op =3D itype_rt (inst); /* branch condition */ + op =3D itype_rt (inst); /* branch condition */ switch (op) { case 0: /* BLTZ */ @@ -1774,8 +1798,10 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR= pc) int dspctl =3D mips_regnum (gdbarch)->dspctl; =20 if (dspctl =3D=3D -1) - /* No way to handle; it'll most likely trap anyway. */ - break; + { + /* No way to handle; it'll most likely trap anyway. */ + break; + } =20 if ((regcache_raw_get_unsigned (regcache, dspctl) & 0x7f) >=3D pos) @@ -1789,7 +1815,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR = pc) pc +=3D 4; } } - break; /* end REGIMM */ + break; /* end REGIMM */ case 2: /* J */ case 3: /* JAL */ { @@ -1823,7 +1849,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR = pc) break; case 7: default: - greater_branch: /* BGTZ, BGTZL */ + greater_branch: /* BGTZ, BGTZL */ if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0) pc +=3D mips32_relative_offset (inst) + 4; else @@ -1889,8 +1915,10 @@ micromips_bc1_pc (struct gdbarch *gdbarch, struct re= gcache *regcache, int cond; =20 if (fcsr =3D=3D -1) - /* No way to handle; it'll most likely trap anyway. */ - return pc; + { + /* No way to handle; it'll most likely trap anyway. */ + return pc; + } =20 fcs =3D regcache_raw_get_unsigned (regcache, fcsr); cond =3D ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); @@ -2004,8 +2032,10 @@ micromips_next_pc (struct regcache *regcache, CORE_A= DDR pc) case 0x14: /* BC2F: bits 010000 10100 xxx00 */ case 0x15: /* BC2T: bits 010000 10101 xxx00 */ if (((insn >> 16) & 0x3) =3D=3D 0x0) - /* BC2F, BC2T: don't know how to handle these. */ - break; + { + /* BC2F, BC2T: don't know how to handle these. */ + break; + } break; =20 case 0x1a: /* BPOSGE64: bits 010000 11010 */ @@ -2015,8 +2045,10 @@ micromips_next_pc (struct regcache *regcache, CORE_A= DDR pc) int dspctl =3D mips_regnum (gdbarch)->dspctl; =20 if (dspctl =3D=3D -1) - /* No way to handle; it'll most likely trap anyway. */ - break; + { + /* No way to handle; it'll most likely trap anyway. */ + break; + } =20 if ((regcache_raw_get_unsigned (regcache, dspctl) & 0x7f) >=3D pos) @@ -2046,27 +2078,27 @@ micromips_next_pc (struct regcache *regcache, CORE_= ADDR pc) case 0x1d: /* JALS: bits 011101 */ case 0x35: /* J: bits 110101 */ case 0x3d: /* JAL: bits 111101 */ - pc =3D ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); + pc =3D ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); break; =20 case 0x25: /* BEQ: bits 100101 */ - if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) + if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) =3D=3D regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) - pc +=3D micromips_relative_offset16 (insn); - else - pc +=3D micromips_pc_insn_size (gdbarch, pc); + pc +=3D micromips_relative_offset16 (insn); + else + pc +=3D micromips_pc_insn_size (gdbarch, pc); break; =20 case 0x2d: /* BNE: bits 101101 */ if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) !=3D regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) - pc +=3D micromips_relative_offset16 (insn); + pc +=3D micromips_relative_offset16 (insn); else - pc +=3D micromips_pc_insn_size (gdbarch, pc); + pc +=3D micromips_pc_insn_size (gdbarch, pc); break; =20 case 0x3c: /* JALX: bits 111100 */ - pc =3D ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); + pc =3D ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); break; } break; @@ -2077,11 +2109,15 @@ micromips_next_pc (struct regcache *regcache, CORE_= ADDR pc) { case 0x11: /* POOL16C: bits 010001 */ if ((b5s5_op (insn) & 0x1c) =3D=3D 0xc) - /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ - pc =3D regcache_raw_get_signed (regcache, b0s5_reg (insn)); + { + /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ + pc =3D regcache_raw_get_signed (regcache, b0s5_reg (insn)); + } else if (b5s5_op (insn) =3D=3D 0x18) - /* JRADDIUSP: bits 010001 11000 */ - pc =3D regcache_raw_get_signed (regcache, MIPS_RA_REGNUM); + { + /* JRADDIUSP: bits 010001 11000 */ + pc =3D regcache_raw_get_signed (regcache, MIPS_RA_REGNUM); + } break; =20 case 0x23: /* BEQZ16: bits 100011 */ @@ -2150,6 +2186,7 @@ enum mips16_inst_fmts extRi64type, /* 20 5,6,5,5,3,3,5 */ extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ }; + /* I am heaping all the fields of the formats into one structure and then, only the fields which are involved in instruction extension. */ struct upk_mips16 @@ -2159,7 +2196,6 @@ struct upk_mips16 unsigned int regy; }; =20 - /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format for the bits which make up the immediate extension. */ =20 @@ -2267,7 +2303,6 @@ unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, upk->regy =3D regy; } =20 - /* Calculate the destination of a branch whose 16-bit opcode word is at PC= , and having a signed 16-bit OFFSET. */ =20 @@ -2395,6 +2430,7 @@ mips16_next_pc (struct regcache *regcache, CORE_ADDR = pc) It works by decoding the current instruction and predicting where a branch will go. This isn't hard because all the data is available. The MIPS32, MIPS16 and microMIPS variants are quite different. */ + static CORE_ADDR mips_next_pc (struct regcache *regcache, CORE_ADDR pc) { @@ -2482,7 +2518,6 @@ set_reg_offset (struct gdbarch *gdbarch, struct mips_= frame_cache *this_cache, } } =20 - /* Fetch the immediate value from a MIPS16 instruction. If the previous instruction was an EXTEND, use it to extend the upper bits of the immediate value. This is a helper function @@ -2517,8 +2552,7 @@ mips16_get_imm (unsigned short prev_inst, /* previous= instruction */ } } =20 - -/* Analyze the function prologue from START_PC to LIMIT_PC. Builds +/* Analyze the function prologue from START_PC to LIMIT_PC. Builds the associated FRAME_CACHE if not null. Return the address of the first instruction past the prologue. */ =20 @@ -2535,8 +2569,8 @@ mips16_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR cur_pc; CORE_ADDR frame_addr =3D 0; /* Value of $r17, used as frame pointer. */ CORE_ADDR sp; - long frame_offset =3D 0; /* Size of stack frame. */ - long frame_adjust =3D 0; /* Offset of FP from SP. */ + long frame_offset =3D 0; /* Size of stack frame. */ + long frame_adjust =3D 0; /* Offset of FP from SP. */ int frame_reg =3D MIPS_SP_REGNUM; unsigned short prev_inst =3D 0; /* saved copy of previous instruction. = */ unsigned inst =3D 0; /* current instruction */ @@ -2600,10 +2634,12 @@ mips16_scan_prologue (struct gdbarch *gdbarch, if (offset < 0) /* Negative stack adjustment? */ frame_offset -=3D offset; else - /* Exit loop if a positive stack adjustment is found, which - usually means that the stack cleanup code in the function - epilogue is reached. */ - break; + { + /* Exit loop if a positive stack adjustment is found, which + usually means that the stack cleanup code in the function + epilogue is reached. */ + break; + } } else if ((inst & 0xf800) =3D=3D 0xd000) /* sw reg,n($sp) */ { @@ -2888,7 +2924,7 @@ mips_insn16_frame_cache (const frame_info_ptr &this_f= rame, void **this_cache) mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, (struct mips_frame_cache *) *this_cache); } - =20 + /* gdbarch_sp_regnum contains the value and not the address. */ cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM].set_value (cache->base); @@ -3063,7 +3099,7 @@ micromips_scan_prologue (struct gdbarch *gdbarch, && dreg =3D=3D MIPS_SP_REGNUM && sreg =3D=3D MIPS_SP_REGNUM && treg =3D=3D 3) /* (D)SUBU $sp, $v1 */ - sp_adj =3D v1_off; + sp_adj =3D v1_off; else if (op !=3D 0x150 /* ADDU: bits 000000 00101010000 */ /* DADDU: bits 010110 00101010000 */ @@ -3273,7 +3309,7 @@ micromips_scan_prologue (struct gdbarch *gdbarch, gdbarch_num_regs (gdbarch) + frame_reg) + frame_offset - frame_adjust); /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we shoul= d - be able to get rid of the assignment below, evetually. But it's + be able to get rid of the assignment below, evetually. But it's still needed for now. */ this_cache->saved_regs[gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc] @@ -3292,7 +3328,7 @@ micromips_scan_prologue (struct gdbarch *gdbarch, =20 /* Heuristic unwinder for procedures using microMIPS instructions. Procedures that use the 32-bit instruction set are handled by the - mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */ + mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. *= / =20 static struct mips_frame_cache * mips_micro_frame_cache (const frame_info_ptr &this_frame, void **this_cach= e) @@ -3425,7 +3461,7 @@ reset_saved_regs (struct gdbarch *gdbarch, struct mip= s_frame_cache *this_cache) } =20 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds - the associated FRAME_CACHE if not null. =20 + the associated FRAME_CACHE if not null. Return the address of the first instruction past the prologue. */ =20 static CORE_ADDR @@ -3437,7 +3473,7 @@ mips32_scan_prologue (struct gdbarch *gdbarch, int prev_non_prologue_insn; int this_non_prologue_insn; int non_prologue_insns; - CORE_ADDR frame_addr =3D 0; /* Value of $r30. Used by gcc for + CORE_ADDR frame_addr =3D 0; /* Value of $r30. Used by gcc for frame-pointer. */ int prev_delay_slot; CORE_ADDR prev_pc; @@ -3499,10 +3535,12 @@ mips32_scan_prologue (struct gdbarch *gdbarch, if (offset < 0) /* Negative stack adjustment? */ frame_offset -=3D offset; else - /* Exit loop if a positive stack adjustment is found, which - usually means that the stack cleanup code in the function - epilogue is reached. */ - break; + { + /* Exit loop if a positive stack adjustment is found, which + usually means that the stack cleanup code in the function + epilogue is reached. */ + break; + } seen_sp_adjust =3D 1; } else if (((high_word & 0xFFE0) =3D=3D 0xafa0) /* sw reg,offset($sp) = */ @@ -3576,7 +3614,7 @@ mips32_scan_prologue (struct gdbarch *gdbarch, } } } - else if ((high_word & 0xFFE0) =3D=3D 0xafc0 /* sw reg,offset($30) *= / + else if ((high_word & 0xFFE0) =3D=3D 0xafc0 /* sw reg,offset($30) *= / && !regsize_is_64_bits) { set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); @@ -3641,7 +3679,7 @@ mips32_scan_prologue (struct gdbarch *gdbarch, =20 if (this_cache !=3D NULL) { - this_cache->base =3D=20 + this_cache->base =3D (get_frame_register_signed (this_frame, gdbarch_num_regs (gdbarch) + frame_reg) + frame_offset); @@ -3660,7 +3698,7 @@ mips32_scan_prologue (struct gdbarch *gdbarch, its address instead. */ end_prologue_addr =3D prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; - =20 + /* In a frameless function, we might have incorrectly skipped some load immediate instructions. Undo the skipping if the load immediate was not followed by a stack adjustment. */ @@ -3673,7 +3711,7 @@ mips32_scan_prologue (struct gdbarch *gdbarch, /* Heuristic unwinder for procedures using 32-bit instructions (covers both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit instructions (a.k.a. MIPS16) are handled by the mips_insn16 - unwinder. Likewise microMIPS and the mips_micro unwinder. */ + unwinder. Likewise microMIPS and the mips_micro unwinder. */ =20 static struct mips_frame_cache * mips_insn32_frame_cache (const frame_info_ptr &this_frame, void **this_cac= he) @@ -3704,7 +3742,7 @@ mips_insn32_frame_cache (const frame_info_ptr &this_f= rame, void **this_cache) mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, (struct mips_frame_cache *) *this_cache); } - =20 + /* gdbarch_sp_regnum contains the value and not the address. */ cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM].set_value (cache->base); @@ -3904,30 +3942,31 @@ mips_addr_bits_remove (struct gdbarch *gdbarch, COR= E_ADDR addr) mips_gdbarch_tdep *tdep =3D gdbarch_tdep (gdbarch); =20 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 =3D=3D 0xffff= ffffUL)) - /* This hack is a work-around for existing boards using PMON, the - simulator, and any other 64-bit targets that doesn't have true - 64-bit addressing. On these targets, the upper 32 bits of - addresses are ignored by the hardware. Thus, the PC or SP are - likely to have been sign extended to all 1s by instruction - sequences that load 32-bit addresses. For example, a typical - piece of code that loads an address is this: - - lui $r2, - ori $r2, - - But the lui sign-extends the value such that the upper 32 bits - may be all 1s. The workaround is simply to mask off these - bits. In the future, gcc may be changed to support true 64-bit - addressing, and this masking will have to be disabled. */ - return addr &=3D 0xffffffffUL; + { + /* This hack is a work-around for existing boards using PMON, the + simulator, and any other 64-bit targets that doesn't have true + 64-bit addressing. On these targets, the upper 32 bits of + addresses are ignored by the hardware. Thus, the PC or SP are + likely to have been sign extended to all 1s by instruction + sequences that load 32-bit addresses. For example, a typical + piece of code that loads an address is this: + + lui $r2, + ori $r2, + + But the lui sign-extends the value such that the upper 32 bits + may be all 1s. The workaround is simply to mask off these + bits. In the future, gcc may be changed to support true 64-bit + addressing, and this masking will have to be disabled. */ + return addr &=3D 0xffffffffUL; + } else return addr; } =20 - /* Checks for an atomic sequence of instructions beginning with a LL/LLD instruction and ending with a SC/SCD instruction. If such a sequence - is found, attempt to step through it. A breakpoint is placed at the en= d of=20 + is found, attempt to step through it. A breakpoint is placed at the en= d of the sequence. */ =20 /* Instructions used during single-stepping of atomic sequences, standard @@ -3946,7 +3985,7 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbar= ch, CORE_ADDR pc) ULONGEST insn; int insn_count; int index; - int last_breakpoint =3D 0; /* Defaults to 0 (no breakpoints placed). */= =20 + int last_breakpoint =3D 0; /* Defaults to 0 (no breakpoints placed). */ const int atomic_sequence_length =3D 16; /* Instruction sequence length.= */ =20 insn =3D mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); @@ -3954,7 +3993,7 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbar= ch, CORE_ADDR pc) if (itype_op (insn) !=3D LL_OPCODE && itype_op (insn) !=3D LLD_OPCODE) return {}; =20 - /* Assume that no atomic sequence is longer than "atomic_sequence_length= "=20 + /* Assume that no atomic sequence is longer than "atomic_sequence_length= " instructions. */ for (insn_count =3D 0; insn_count < atomic_sequence_length; ++insn_count= ) { @@ -4130,7 +4169,7 @@ micromips_deal_with_atomic_sequence (struct gdbarch *= gdbarch, case 0x35: /* J: bits 110101 */ case 0x3d: /* JAL: bits 111101 */ case 0x3c: /* JALX: bits 111100 */ - return {}; /* Fall back to the standard single-step code. */ + return {}; /* Fall back to the standard single-step code. */ =20 case 0x18: /* POOL32C: bits 011000 */ if ((b12s4_op (insn) & 0xb) =3D=3D 0xb) @@ -4157,10 +4196,10 @@ micromips_deal_with_atomic_sequence (struct gdbarch= *gdbarch, && b5s5_op (insn) !=3D 0x18) /* JRADDIUSP: bits 010001 11000 */ break; - return {}; /* Fall back to the standard single-step code. */ + return {}; /* Fall back to the standard single-step code. */ =20 case 0x33: /* B16: bits 110011 */ - return {}; /* Fall back to the standard single-step code. */ + return {}; /* Fall back to the standard single-step code. */ } break; } @@ -4244,7 +4283,6 @@ mips_about_to_return (struct gdbarch *gdbarch, CORE_A= DDR pc) return (insn & ~hint) =3D=3D 0x3e00008; /* jr(.hb) $ra */ } =20 - /* This fencepost looks highly suspicious to me. Removing it also seems suspicious as it could affect remote debugging across serial lines. */ @@ -4476,6 +4514,7 @@ mips_type_needs_double_align (struct type *type) =20 /* Adjust the address downward (direction of stack growth) so that it is correctly aligned for a new stack frame. */ + static CORE_ADDR mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) { @@ -4817,7 +4856,7 @@ mips_eabi_return_value (struct gdbarch *gdbarch, stru= ct value *function, { if (type->code () =3D=3D TYPE_CODE_FLT) fp_return_type =3D 1; - /* Structs with a single field of float type=20 + /* Structs with a single field of float type are returned in a floating point register. */ if ((type->code () =3D=3D TYPE_CODE_STRUCT || type->code () =3D=3D TYPE_CODE_UNION) @@ -4830,7 +4869,7 @@ mips_eabi_return_value (struct gdbarch *gdbarch, stru= ct value *function, } } =20 - if (fp_return_type) =20 + if (fp_return_type) { /* A floating-point value belongs in the least significant part of FP0/FP1. */ @@ -4838,7 +4877,7 @@ mips_eabi_return_value (struct gdbarch *gdbarch, stru= ct value *function, gdb_printf (gdb_stderr, "Return float in $fp0\n"); regnum =3D mips_regnum (gdbarch)->fp0; } - else=20 + else { /* An integer value goes in V0/V1. */ if (mips_debug) @@ -4861,7 +4900,6 @@ mips_eabi_return_value (struct gdbarch *gdbarch, stru= ct value *function, return RETURN_VALUE_REGISTER_CONVENTION; } =20 - /* N32/N64 ABI stuff. */ =20 /* Search for a naturally aligned double at OFFSET inside a struct @@ -6525,7 +6563,6 @@ print_fp_register_row (struct ui_file *file, const fr= ame_info_ptr &frame, return regnum + 1; } =20 - /* Print a row's worth of GP (int) registers, with name labels above. */ =20 static int @@ -6723,7 +6760,7 @@ mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADD= R pc) that bound, then use an arbitrary large number as the upper bound. *= / limit_pc =3D skip_prologue_using_sal (gdbarch, pc); if (limit_pc =3D=3D 0) - limit_pc =3D pc + 100; /* Magic. */ + limit_pc =3D pc + 100; /* Magic. */ =20 if (mips_pc_is_mips16 (gdbarch, pc)) return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); @@ -6964,7 +7001,6 @@ show_mipsfpu_command (const char *args, int from_tty) ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); } =20 - static void set_mipsfpu_single_command (const char *args, int from_tty) { @@ -7146,7 +7182,7 @@ mips32_instruction_has_delay_slot (struct gdbarch *gd= barch, ULONGEST inst) { rs =3D itype_rs (inst); rt =3D itype_rt (inst); - return (is_octeon_bbit_op (op, gdbarch)=20 + return (is_octeon_bbit_op (op, gdbarch) || op >> 2 =3D=3D 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ || op =3D=3D 29 /* JALX: bits 011101 */ || (op =3D=3D 17 @@ -7393,7 +7429,7 @@ mips_adjust_breakpoint_address (struct gdbarch *gdbar= ch, CORE_ADDR bpaddr) /* Make sure we don't scan back before the beginning of the current function, since we may fetch constant data or insns that look like a jump. Of course we might do that anyway if the compiler has - moved constants inline. :-( */ + moved constants inline. :-( */ if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) && func_addr > boundary && func_addr <=3D bpaddr) boundary =3D func_addr; @@ -7404,7 +7440,7 @@ mips_adjust_breakpoint_address (struct gdbarch *gdbar= ch, CORE_ADDR bpaddr) return bpaddr; =20 /* If the previous instruction has a branch delay slot, we have - to move the breakpoint to the branch instruction. */ + to move the breakpoint to the branch instruction. */ prev_addr =3D bpaddr - 4; if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr)) bpaddr =3D prev_addr; @@ -7437,36 +7473,42 @@ mips_adjust_breakpoint_address (struct gdbarch *gdb= arch, CORE_ADDR bpaddr) break; addr -=3D MIPS_INSN16_SIZE; if (i =3D=3D 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 0)) - /* Looks like a JR/JALR at [target-1], but it could be - the second word of a previous JAL/JALX, so record it - and check back one more. */ - jmpaddr =3D addr; + { + /* Looks like a JR/JALR at [target-1], but it could be + the second word of a previous JAL/JALX, so record it + and check back one more. */ + jmpaddr =3D addr; + } else if (i > 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 1)) { if (i =3D=3D 2) - /* Looks like a JAL/JALX at [target-2], but it could also - be the second word of a previous JAL/JALX, record it, - and check back one more. */ - jmpaddr =3D addr; + { + /* Looks like a JAL/JALX at [target-2], but it could also + be the second word of a previous JAL/JALX, record it, + and check back one more. */ + jmpaddr =3D addr; + } else - /* Looks like a JAL/JALX at [target-3], so any previously - recorded JAL/JALX or JR/JALR must be wrong, because: - - >-3: JAL - -2: JAL-ext (can't be JAL/JALX) - -1: bdslot (can't be JR/JALR) - 0: target insn - - Of course it could be another JAL-ext which looks - like a JAL, but in that case we'd have broken out - of this loop at [target-2]: - - -4: JAL - >-3: JAL-ext - -2: bdslot (can't be jmp) - -1: JR/JALR - 0: target insn */ - jmpaddr =3D 0; + { + /* Looks like a JAL/JALX at [target-3], so any previously + recorded JAL/JALX or JR/JALR must be wrong, because: + + >-3: JAL + -2: JAL-ext (can't be JAL/JALX) + -1: bdslot (can't be JR/JALR) + 0: target insn + + Of course it could be another JAL-ext which looks + like a JAL, but in that case we'd have broken out + of this loop at [target-2]: + + -4: JAL + >-3: JAL-ext + -2: bdslot (can't be jmp) + -1: JR/JALR + 0: target insn */ + jmpaddr =3D 0; + } } else { @@ -7733,15 +7775,19 @@ mips_skip_mips16_trampoline_code (const frame_info_= ptr &frame, CORE_ADDR pc) && mips_is_stub_suffix (name + prefixlen + 3, 0)) { if (pc =3D=3D start_addr) - /* This is the 'call' part of a call stub. The return - address is in $2. */ - return get_frame_register_signed + { + /* This is the 'call' part of a call stub. The return + address is in $2. */ + return get_frame_register_signed (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); + } else - /* This is the 'return' part of a call stub. The return - address is in $18. */ - return get_frame_register_signed + { + /* This is the 'return' part of a call stub. The return + address is in $18. */ + return get_frame_register_signed (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); + } } else return 0; /* Not a stub. */ @@ -7753,15 +7799,19 @@ mips_skip_mips16_trampoline_code (const frame_info_= ptr &frame, CORE_ADDR pc) || startswith (name, mips_str_call_stub)) { if (pc =3D=3D start_addr) - /* This is the 'call' part of a call stub. Call this helper - to scan through this code for interesting instructions - and determine the final PC. */ - return mips_get_mips16_fn_stub_pc (frame, pc); + { + /* This is the 'call' part of a call stub. Call this helper + to scan through this code for interesting instructions + and determine the final PC. */ + return mips_get_mips16_fn_stub_pc (frame, pc); + } else - /* This is the 'return' part of a call stub. The return address - is in $18. */ - return get_frame_register_signed + { + /* This is the 'return' part of a call stub. The return address + is in $18. */ + return get_frame_register_signed (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); + } } =20 return 0; /* Not a stub. */ @@ -7922,7 +7972,6 @@ mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int= num) return gdbarch_num_regs (gdbarch) + regnum; } =20 - /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ =20 @@ -7960,7 +8009,6 @@ mips_register_sim_regno (struct gdbarch *gdbarch, int= regnum) return LEGACY_SIM_REGNO_IGNORE; } =20 - /* Convert an integer into an address. Extracting the value signed guarantees a correctly sign extended address. */ =20 @@ -8361,7 +8409,6 @@ mips_gdbarch_init (struct gdbarch_info info, struct g= dbarch_list *arches) valid_p &=3D tdesc_numbered_register (feature, tdesc_data.get (), i, mips_gprs[i]); =20 - valid_p &=3D tdesc_numbered_register (feature, tdesc_data.get (), mips_regnum.lo, "lo"); valid_p &=3D tdesc_numbered_register (feature, tdesc_data.get (), @@ -8832,7 +8879,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct g= dbarch_list *arches) =20 for (i =3D 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, - value_of_mips_user_reg,=20 + value_of_mips_user_reg, &mips_numeric_register_aliases[i].regnum); =20 return gdbarch; @@ -8860,7 +8907,7 @@ show_mips_abi (struct ui_file *file, if (gdbarch_bfd_arch_info (current_inferior ()->arch ())->arch !=3D bfd_arch_mips) gdb_printf - (file,=20 + (file, "The MIPS ABI is unknown because the current architecture " "is not MIPS.\n"); else @@ -8871,7 +8918,7 @@ show_mips_abi (struct ui_file *file, =20 if (global_abi =3D=3D MIPS_ABI_UNKNOWN) gdb_printf - (file,=20 + (file, "The MIPS ABI is set automatically (currently \"%s\").\n", actual_abi_str); else if (global_abi =3D=3D actual_abi) --=20 2.34.1