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From: Tankut Baris Aktemur <tankut.baris.aktemur@intel.com>
To: gdb-patches@sourceware.org, Markus Metzger <markus.t.metzger@intel.com>
Subject: [PATCH v2 05/47] gdb, arch, intelgt: add intelgt arch definitions
Date: Fri, 13 Dec 2024 16:59:22 +0100	[thread overview]
Message-ID: <20241213-upstream-intelgt-mvp-v2-5-5c4caeb7b33d@intel.com> (raw)
In-Reply-To: <20241213-upstream-intelgt-mvp-v2-0-5c4caeb7b33d@intel.com>

From: Markus Metzger <markus.t.metzger@intel.com>

Provide Intel GT architecture-specific definitions that can be used by
both the low target at the server side and tdep at the GDB side.

Other than, for example, IA, Intel GT does not have a dedicated
breakpoint instruction.  Instead, it has a breakpoint bit in each
instruction.  We define arch methods for dealing with instruction
breakpoint bits.

Co-authored-by: Tankut Baris Aktemur <tankut.baris.aktemur@intel.com>
Co-authored-by: Mihails Strasuns <mihails.strasuns@intel.com>
Co-authored-by: Natalia Saiapova <natalia.saiapova@intel.com>
---
 gdb/Makefile.in    |   1 +
 gdb/arch/intelgt.c |  77 +++++++++++++++++++++++
 gdb/arch/intelgt.h | 175 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 253 insertions(+)

diff --git a/gdb/Makefile.in b/gdb/Makefile.in
index 52950759711af139f18e963b13fef7e70a5fc6e0..82e035fa02a29ec073c3a909397aca75d82e4a89 100644
--- a/gdb/Makefile.in
+++ b/gdb/Makefile.in
@@ -751,6 +751,7 @@ ALL_64_TARGET_OBS = \
 	arch/aarch64-scalable-linux.o \
 	arch/amd64-linux-tdesc.o \
 	arch/amd64.o \
+	arch/intelgt.o \
 	arch/riscv.o \
 	bpf-tdep.o \
 	ia64-linux-tdep.o \
diff --git a/gdb/arch/intelgt.c b/gdb/arch/intelgt.c
new file mode 100644
index 0000000000000000000000000000000000000000..89a19baea8428c1479d1e43de676a4f0dfb01952
--- /dev/null
+++ b/gdb/arch/intelgt.c
@@ -0,0 +1,77 @@
+/* Copyright (C) 2019-2024 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#include "intelgt.h"
+#include <stdlib.h>
+
+namespace intelgt {
+
+/* Get the bit at POS in INST.  */
+
+bool
+get_inst_bit (gdb::array_view<const gdb_byte> inst, int pos)
+{
+  if (pos < 0 || (inst.size () * 8) <= pos)
+    internal_error (_("bad bit offset: %d"), pos);
+
+  const int idx = pos >> 3;
+  const int off = pos & 7;
+  const int mask = 1 << off;
+  const gdb_byte byte = inst[idx];
+
+  return (byte & mask) != 0;
+}
+
+/* Set the bit at POS in INST.  */
+
+bool
+set_inst_bit (gdb::array_view<gdb_byte> inst, int pos)
+{
+  if (pos < 0 || (inst.size () * 8) <= pos)
+    internal_error (_("bad bit offset: %d"), pos);
+
+  const int idx = pos >> 3;
+  const int off = pos & 7;
+  const int mask = 1 << off;
+  const gdb_byte byte = inst[idx];
+
+  const bool old = (byte & mask) != 0;
+  inst[idx] |= mask;
+
+  return old;
+}
+
+/* Clear the bit at POS in INST.  */
+
+bool
+clear_inst_bit (gdb::array_view<gdb_byte> inst, int pos)
+{
+  if (pos < 0 || (inst.size () * 8) <= pos)
+    internal_error (_("bad bit offset: %d"), pos);
+
+  const int idx = pos >> 3;
+  const int off = pos & 7;
+  const int mask = 1 << off;
+  const gdb_byte byte = inst[idx];
+
+  const bool old = (byte & mask) != 0;
+  inst[idx] &= ~mask;
+
+  return old;
+}
+
+} /* namespace intelgt */
diff --git a/gdb/arch/intelgt.h b/gdb/arch/intelgt.h
new file mode 100644
index 0000000000000000000000000000000000000000..38e89053a9b22e26c370525758f8da7f3790f6bb
--- /dev/null
+++ b/gdb/arch/intelgt.h
@@ -0,0 +1,175 @@
+/* Copyright (C) 2019-2024 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#ifndef ARCH_INTELGT_H
+#define ARCH_INTELGT_H
+
+#include "gdbsupport/tdesc.h"
+#include <string>
+#include <vector>
+
+namespace intelgt {
+
+/* Various arch constants.  */
+
+enum breakpoint_kind
+{
+  BP_INSTRUCTION = 1,
+};
+
+/* The length of a full and compact IntelGT instruction in bytes.  */
+
+constexpr int MAX_INST_LENGTH = 16;
+constexpr int COMPACT_INST_LENGTH = 8;
+
+/* Feature names.
+
+   They correspond to register sets defined in zet_intel_gpu_debug.h.  We
+   declare feature names in the order used in that header.
+
+   The SBA register set consists of a set of base registers in the order
+   defined in that header file.
+
+   Not all registers have DWARF numbers.  See DWARF_REGSETS below for a
+   list of features that do.  */
+constexpr const char *FEATURE_GRF = "org.gnu.gdb.intelgt.grf";
+constexpr const char *FEATURE_ADDR = "org.gnu.gdb.intelgt.addr";
+constexpr const char *FEATURE_FLAG = "org.gnu.gdb.intelgt.flag";
+constexpr const char *FEATURE_CE = "org.gnu.gdb.intelgt.ce";
+constexpr const char *FEATURE_SR = "org.gnu.gdb.intelgt.sr";
+constexpr const char *FEATURE_CR = "org.gnu.gdb.intelgt.cr";
+constexpr const char *FEATURE_TDR = "org.gnu.gdb.intelgt.tdr";
+constexpr const char *FEATURE_ACC = "org.gnu.gdb.intelgt.acc";
+constexpr const char *FEATURE_MME = "org.gnu.gdb.intelgt.mme";
+constexpr const char *FEATURE_SP = "org.gnu.gdb.intelgt.sp";
+constexpr const char *FEATURE_SBA = "org.gnu.gdb.intelgt.sba";
+constexpr const char *FEATURE_DBG = "org.gnu.gdb.intelgt.dbg";
+constexpr const char *FEATURE_FC = "org.gnu.gdb.intelgt.fc";
+constexpr const char *FEATURE_DEBUGGER = "org.gnu.gdb.intelgt.debugger";
+
+/* Register sets/groups needed for DWARF mapping.  Used for
+   declaring static arrays for various mapping tables.  */
+
+enum dwarf_regsets : int
+{
+  REGSET_SBA = 0,
+  REGSET_GRF,
+  REGSET_ADDR,
+  REGSET_FLAG,
+  REGSET_ACC,
+  REGSET_MME,
+  REGSET_COUNT
+};
+
+/* Map of dwarf_regset values to the target description
+   feature names.  */
+
+constexpr const char *DWARF_REGSET_FEATURES[REGSET_COUNT] = {
+  FEATURE_SBA,
+  FEATURE_GRF,
+  FEATURE_ADDR,
+  FEATURE_FLAG,
+  FEATURE_ACC,
+  FEATURE_MME
+};
+
+/* Instruction details.  */
+
+enum
+{
+  /* The opcode mask for bits 6:0.  */
+  OPC_MASK = 0x7f,
+
+  /* Send instruction opcodes.  */
+  OPC_SEND = 0x31,
+  OPC_SENDC = 0x32,
+};
+
+/* Selected instruction control bit positions.  */
+
+enum
+{
+  /* The End Of Thread control.  Only used for SEND and SENDC.  */
+  CTRL_EOT = 34,
+};
+
+/* Get the bit at POS in INST.  */
+
+bool get_inst_bit (gdb::array_view<const gdb_byte> inst, int pos);
+
+/* Set the bit at POS in INST.  */
+
+bool set_inst_bit (gdb::array_view<gdb_byte> inst, int pos);
+
+/* Clear the bit at POS in INST.  */
+
+bool clear_inst_bit (gdb::array_view<gdb_byte> inst, int pos);
+
+static inline bool
+is_compacted_inst (gdb::array_view<const gdb_byte> inst)
+{
+  /* Check the CmptCtrl flag (bit 29).  */
+  return inst[3] & 0x20;
+}
+
+static inline int
+breakpoint_bit_offset (gdb::array_view<const gdb_byte> inst)
+{
+  return (is_compacted_inst (inst) ? 7 : 30);
+}
+
+static inline bool
+set_breakpoint (gdb::array_view<gdb_byte> inst)
+{
+  return set_inst_bit (inst, breakpoint_bit_offset (inst));
+}
+
+static inline bool
+clear_breakpoint (gdb::array_view<gdb_byte> inst)
+{
+  return clear_inst_bit (inst, breakpoint_bit_offset (inst));
+}
+
+static inline bool
+has_breakpoint (gdb::array_view<const gdb_byte> inst)
+{
+  return get_inst_bit (inst, breakpoint_bit_offset (inst));
+}
+
+static inline unsigned int
+inst_length_compacted ()
+{
+  return COMPACT_INST_LENGTH;
+}
+
+static inline unsigned int
+inst_length_full ()
+{
+  return MAX_INST_LENGTH;
+}
+
+static inline unsigned int
+inst_length (gdb::array_view<const gdb_byte> inst)
+{
+  return (is_compacted_inst (inst)
+	  ? inst_length_compacted ()
+	  : inst_length_full ());
+}
+
+} /* namespace intelgt */
+
+#endif

-- 
2.34.1

Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de
Managing Directors: Sean Fennelly, Jeffrey Schneiderman, Tiffany Doon Silva
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928

  parent reply	other threads:[~2024-12-13 16:19 UTC|newest]

Thread overview: 87+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-13 15:59 [PATCH v2 00/47] A new target to debug Intel GPUs Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 01/47] gdb, intelgt: add intelgt as a basic machine Tankut Baris Aktemur
2024-12-16  7:53   ` Jan Beulich
2024-12-17 18:48     ` Aktemur, Tankut Baris
2024-12-18  7:19       ` Jan Beulich
2024-12-20  9:55         ` Aktemur, Tankut Baris
2025-02-03 17:17           ` Aktemur, Tankut Baris
2025-02-04  7:06             ` Jan Beulich
2024-12-13 15:59 ` [PATCH v2 02/47] bfd: add intelgt target to BFD Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 03/47] ld: add intelgt as a target configuration Tankut Baris Aktemur
2024-12-16  7:43   ` Jan Beulich
2024-12-13 15:59 ` [PATCH v2 04/47] opcodes: add intelgt as a configuration Tankut Baris Aktemur
2024-12-16  7:44   ` Jan Beulich
2024-12-17 18:47     ` Aktemur, Tankut Baris
2024-12-18  7:22       ` Jan Beulich
2024-12-20  9:47         ` Aktemur, Tankut Baris
2025-01-03  4:46           ` Simon Marchi
2025-02-03 17:13             ` Aktemur, Tankut Baris
2025-02-04  7:07               ` Jan Beulich
2024-12-13 15:59 ` Tankut Baris Aktemur [this message]
2025-07-08  3:03   ` [PATCH v2 05/47] gdb, arch, intelgt: add intelgt arch definitions Thiago Jung Bauermann
2025-07-21 10:49     ` Aktemur, Tankut Baris
2024-12-13 15:59 ` [PATCH v2 06/47] gdb, intelgt: add the target-dependent definitions for the Intel GT architecture Tankut Baris Aktemur
2025-07-08  2:43   ` Thiago Jung Bauermann
2025-07-18 17:43     ` Aktemur, Tankut Baris
2024-12-13 15:59 ` [PATCH v2 07/47] gdb, gdbserver, gdbsupport: add 'device' tag to XML target description Tankut Baris Aktemur
2024-12-13 16:45   ` Eli Zaretskii
2025-07-08  4:04   ` Thiago Jung Bauermann
2025-07-21 10:49     ` Aktemur, Tankut Baris
2024-12-13 15:59 ` [PATCH v2 08/47] gdb, intelgt: add disassemble feature for the Intel GT architecture Tankut Baris Aktemur
2025-07-09  3:12   ` Thiago Jung Bauermann
2024-12-13 15:59 ` [PATCH v2 09/47] gdbsupport, filestuff, ze: temporary files Tankut Baris Aktemur
2025-07-14  1:26   ` Thiago Jung Bauermann
2024-12-13 15:59 ` [PATCH v2 10/47] gdb, gdbserver, ze: in-memory libraries Tankut Baris Aktemur
2025-07-14  2:35   ` Thiago Jung Bauermann
2025-07-31  6:09     ` Metzger, Markus T
2025-07-16  4:08   ` Thiago Jung Bauermann
2024-12-13 15:59 ` [PATCH v2 11/47] gdb, gdbserver, rsp, ze: acknowledge libraries Tankut Baris Aktemur
2024-12-13 16:43   ` Eli Zaretskii
2025-07-16  4:20   ` Thiago Jung Bauermann
2025-07-31  6:09     ` Metzger, Markus T
2024-12-13 15:59 ` [PATCH v2 12/47] gdb, solib, ze: solib_bfd_open_from_target_memory Tankut Baris Aktemur
2025-07-18  0:42   ` Thiago Jung Bauermann
2024-12-13 15:59 ` [PATCH v2 13/47] gdb, remote, ze: fix "$Hc-1#09...Packet received: E01" during startup Tankut Baris Aktemur
2025-07-18  0:41   ` Thiago Jung Bauermann
2025-08-01  7:55     ` Metzger, Markus T
2024-12-13 15:59 ` [PATCH v2 14/47] gdb, infrun, ze: allow saving process events Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 15/47] gdb, ze: add TARGET_WAITKIND_UNAVAILABLE Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 16/47] gdb, infrun, ze: handle stopping unavailable threads Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 17/47] gdb, infrun, ze: allow resuming " Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 18/47] gdb, gdbserver, ze: add U stop reply Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 19/47] gdb, gdbserver, ze: add library notification to " Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 20/47] gdbserver, ze: report TARGET_WAITKIND_UNAVAILABLE events Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 21/47] gdb, ze: handle TARGET_WAITKIND_UNAVAILABLE in stop_all_threads Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 22/47] gdb, remote: handle thread unavailability in print_one_stopped_thread Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 23/47] gdb, remote: do 'remote_add_inferior' in 'remote_notice_new_inferior' earlier Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 24/47] gdb, remote: handle a generic process PID in remote_notice_new_inferior Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 25/47] gdb, remote: handle a generic process PID in process_stop_reply Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 26/47] gdb: use the pid from inferior in setup_inferior Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 27/47] gdb: revise the pid_to_exec_file target op Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 28/47] gdb: load solibs if the target does not have the notion of an exec file Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 29/47] gdbserver: import AC_LIB_HAVE_LINKFLAGS macro into the autoconf script Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 30/47] gdbserver: add a pointer to the owner thread in regcache Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 31/47] gdbserver: dump 'xx...x' in collect_register_as_string for unavailable register Tankut Baris Aktemur
2024-12-23 11:38   ` Aktemur, Tankut Baris
2024-12-23 13:47     ` Luis Machado
2024-12-13 15:59 ` [PATCH v2 32/47] gdbserver: wait for stopped threads in queue_stop_reply_callback Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 33/47] gdbserver: adjust pid after the target attaches Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 34/47] gdb: do not create a thread after a process event Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 35/47] gdb, ze: on a whole process stop, mark all threads as not_resumed Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 36/47] gdb, dwarf, ze: add DW_OP_INTEL_regval_bits Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 37/47] gdbserver: allow configuring for a heterogeneous target Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 38/47] gdbserver, ze, intelgt: introduce ze-low and intel-ze-low targets Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 39/47] testsuite, sycl: add SYCL support Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 40/47] testsuite, sycl: add test for backtracing inside a kernel Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 41/47] testsuite, sycl: add test for 'info locals' and 'info args' Tankut Baris Aktemur
2024-12-13 15:59 ` [PATCH v2 42/47] testsuite, sycl: add tests for stepping and accessing data elements Tankut Baris Aktemur
2024-12-13 16:00 ` [PATCH v2 43/47] testsuite, sycl: add test for 1-D and 2-D parallel_for kernels Tankut Baris Aktemur
2024-12-13 16:00 ` [PATCH v2 44/47] testsuite, sycl: add test for scheduler-locking Tankut Baris Aktemur
2024-12-13 16:00 ` [PATCH v2 45/47] testsuite, arch, intelgt: add a disassembly test Tankut Baris Aktemur
2024-12-13 16:00 ` [PATCH v2 46/47] testsuite, arch, intelgt: add intelgt-program-bp.exp Tankut Baris Aktemur
2024-12-13 16:00 ` [PATCH v2 47/47] testsuite, sycl: test canceling a stepping flow Tankut Baris Aktemur
2025-02-07 10:18 ` [PATCH v2 00/47] A new target to debug Intel GPUs Aktemur, Tankut Baris
2025-05-08  7:40   ` Aktemur, Tankut Baris
2025-05-26  8:03     ` Aktemur, Tankut Baris
2025-06-17 12:22       ` Aktemur, Tankut Baris
2025-07-03 12:55   ` Aktemur, Tankut Baris

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