[PATCH v4 0/2] sim: riscv: Compressed instruction simulation

jaydeep.patil
2023-12-21T11:12:16Z

Hi Mike, Andrew,

Addressed review comments.
- Fixed riscv opcodes for NULL match_func
- Added models for C extension
- Using RA and SP from sim_riscv_regnum

I have removed the support for semi-hosting from this patch series, will push it
later once the spec is clear.

Jaydeep Patil (2):
[sim/riscv] Fix crash during instruction decoding
[sim/riscv] Add support for compressed integer instructions

opcodes/riscv-dis.c | 2 +-
sim/riscv/model_list.def | 9 +
sim/riscv/sim-main.c | 338 ++++++++++++++++++++++++++++++--
sim/testsuite/riscv/allinsn.exp | 19 ++
sim/testsuite/riscv/c-ext.s | 110 +++++++++++
5 files changed, 466 insertions(+), 12 deletions(-)
create mode 100644 sim/testsuite/riscv/c-ext.s

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2.25.1