Re: [PATCH 00/24] Fix reading and writing pseudo registers in non-current frames

John Baldwin
2023-11-11T20:26:40Z

On 11/7/23 9:00 PM, Simon Marchi wrote:
> This series fixes reading/writing pseudo registers from/to non-current
> frames (that is, frames other than frame 0). Currently, we get this:
>
> (gdb) frame 0
> #0 break_here_asm () at /home/smarchi/src/binutils-gdb/gdb/testsuite/gdb.arch/amd64-pseudo-unwind-asm.S:38
> 38 pop %rbx
> (gdb) p/x $rbx
> $1 = 0x2021222324252627
> (gdb) p/x $ebx
> $2 = 0x24252627
> (gdb) frame 1
> #1 0x000055555555517d in caller () at /home/smarchi/src/binutils-gdb/gdb/testsuite/gdb.arch/amd64-pseudo-unwind-asm.S:58
> 58 call callee
> (gdb) p/x $rbx
> $3 = 0x1011121314151617
> (gdb) p/x $ebx
> $4 = 0x24252627
>
> This is a bit surprising, we would expect the last value to be
> 0x14151617, the bottom half of the rbx value from frame 1 (the currently
> selected frame at that point). Instead, we got the bottom half of the
> rbx value from frame 0. This is because pseudo registers are always
> read/written from/to the current thread's regcache.
>
> This series fixes this (as well as writing to pseudo registers) by
> making it so pseudo registers are read/written using a frame.
>
> Simon Marchi (24):
> gdb: don't handle i386 k registers as pseudo registers
> gdb: use reg_buffer_common throughout gdbsupport/common-regcache.h
> gdb: make store_integer take an array_view
> gdb: simplify conditions in
> regcache::{read,write,raw_collect,raw_supply}_part
> gdb: change regcache interface to use array_view
> gdb: fix bugs in {get,put}_frame_register_bytes
> gdb: make put_frame_register take an array_view
> gdb: change value_of_register and value_of_register_lazy to take the
> next frame
> gdb: remove frame_register
> gdb: make put_frame_register take the next frame
> gdb: make put_frame_register_bytes take the next frame
> gdb: make get_frame_register_bytes take the next frame
> gdb: add value::allocate_register
> gdb: read pseudo register through frame
> gdb: change parameter name in frame_unwind_register_unsigned
> declaration
> gdb: rename gdbarch_pseudo_register_write to
> gdbarch_deprecated_pseudo_register_write
> gdb: add gdbarch_pseudo_register_write that takes a frame
> gdb: migrate i386 and amd64 to the new gdbarch_pseudo_register_write
> gdb: make aarch64_za_offsets_from_regnum return za_offsets
> gdb: add missing raw register read in
> aarch64_sme_pseudo_register_write
> gdb: migrate aarch64 to new gdbarch_pseudo_register_write
> gdb: migrate arm to gdbarch_pseudo_register_read_value
> gdb: migrate arm to new gdbarch_pseudo_register_write
> gdb/testsuite: add tests for unwinding of pseudo registers
>
> gdb/aarch64-tdep.c | 297 +++++-----
> gdb/alpha-tdep.c | 11 +-
> gdb/amd64-tdep.c | 82 +--
> gdb/arch/arm-get-next-pcs.c | 6 +-
> gdb/arch/arm-get-next-pcs.h | 5 +-
> gdb/arch/arm.c | 2 +-
> gdb/arch/arm.h | 4 +-
> gdb/arm-linux-tdep.c | 11 +-
> gdb/arm-tdep.c | 145 +++--
> gdb/avr-tdep.c | 3 +-
> gdb/bfin-tdep.c | 3 +-
> gdb/csky-tdep.c | 4 +-
> gdb/defs.h | 39 +-
> gdb/dwarf2/expr.c | 22 +-
> gdb/dwarf2/frame.c | 5 +-
> gdb/eval.c | 3 +-
> gdb/findvar.c | 50 +-
> gdb/frame-unwind.c | 3 +-
> gdb/frame.c | 174 +++---
> gdb/frame.h | 28 +-
> gdb/frv-tdep.c | 3 +-
> gdb/gdbarch-gen.h | 28 +-
> gdb/gdbarch.c | 40 +-
> gdb/gdbarch_components.py | 29 +-
> gdb/guile/scm-frame.c | 3 +-
> gdb/h8300-tdep.c | 3 +-
> gdb/i386-tdep.c | 380 ++++--------
> gdb/i386-tdep.h | 15 +-
> gdb/i387-tdep.c | 16 +-
> gdb/ia64-tdep.c | 18 +-
> gdb/infcmd.c | 6 +-
> gdb/loongarch-tdep.c | 3 +-
> gdb/m32c-tdep.c | 3 +-
> gdb/m68hc11-tdep.c | 3 +-
> gdb/m68k-tdep.c | 17 +-
> gdb/mep-tdep.c | 3 +-
> gdb/mi/mi-main.c | 3 +-
> gdb/mips-tdep.c | 29 +-
> gdb/msp430-tdep.c | 3 +-
> gdb/nat/aarch64-hw-point.c | 3 +-
> gdb/nat/aarch64-scalable-linux-ptrace.c | 20 +-
> gdb/nat/linux-btrace.c | 3 +-
> gdb/nds32-tdep.c | 8 +-
> gdb/python/py-frame.c | 3 +-
> gdb/python/py-unwind.c | 4 +-
> gdb/regcache.c | 548 +++++++++++-------
> gdb/regcache.h | 113 +++-
> gdb/riscv-tdep.c | 13 +-
> gdb/rl78-tdep.c | 3 +-
> gdb/rs6000-tdep.c | 21 +-
> gdb/s12z-tdep.c | 2 +-
> gdb/s390-tdep.c | 3 +-
> gdb/sh-tdep.c | 9 +-
> gdb/sparc-tdep.c | 3 +-
> gdb/sparc64-tdep.c | 3 +-
> gdb/std-regs.c | 11 +-
> .../gdb.arch/aarch64-pseudo-unwind-asm.S | 82 +++
> .../gdb.arch/aarch64-pseudo-unwind.c | 33 ++
> .../gdb.arch/aarch64-pseudo-unwind.exp | 90 +++
> .../gdb.arch/amd64-pseudo-unwind-asm.S | 66 +++
> gdb/testsuite/gdb.arch/amd64-pseudo-unwind.c | 33 ++
> .../gdb.arch/amd64-pseudo-unwind.exp | 91 +++
> .../gdb.arch/arm-pseudo-unwind-asm.S | 81 +++
> .../gdb.arch/arm-pseudo-unwind-legacy-asm.S | 84 +++
> .../gdb.arch/arm-pseudo-unwind-legacy.c | 33 ++
> .../gdb.arch/arm-pseudo-unwind-legacy.exp | 86 +++
> gdb/testsuite/gdb.arch/arm-pseudo-unwind.c | 33 ++
> gdb/testsuite/gdb.arch/arm-pseudo-unwind.exp | 88 +++
> gdb/valops.c | 31 +-
> gdb/value.c | 149 +++++
> gdb/value.h | 64 +-
> gdb/xtensa-tdep.c | 3 +-
> gdbserver/linux-arm-low.cc | 4 +-
> gdbserver/regcache.cc | 69 ++-
> gdbserver/regcache.h | 6 +-
> gdbsupport/common-regcache.cc | 2 +-
> gdbsupport/common-regcache.h | 58 +-
> gdbsupport/rsp-low.cc | 8 +
> gdbsupport/rsp-low.h | 2 +
> 79 files changed, 2324 insertions(+), 1144 deletions(-)
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-pseudo-unwind-asm.S
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-pseudo-unwind.c
> create mode 100644 gdb/testsuite/gdb.arch/aarch64-pseudo-unwind.exp
> create mode 100644 gdb/testsuite/gdb.arch/amd64-pseudo-unwind-asm.S
> create mode 100644 gdb/testsuite/gdb.arch/amd64-pseudo-unwind.c
> create mode 100644 gdb/testsuite/gdb.arch/amd64-pseudo-unwind.exp
> create mode 100644 gdb/testsuite/gdb.arch/arm-pseudo-unwind-asm.S
> create mode 100644 gdb/testsuite/gdb.arch/arm-pseudo-unwind-legacy-asm.S
> create mode 100644 gdb/testsuite/gdb.arch/arm-pseudo-unwind-legacy.c
> create mode 100644 gdb/testsuite/gdb.arch/arm-pseudo-unwind-legacy.exp
> create mode 100644 gdb/testsuite/gdb.arch/arm-pseudo-unwind.c
> create mode 100644 gdb/testsuite/gdb.arch/arm-pseudo-unwind.exp
>
>
> base-commit: 1185b5b79a12ba67eb60bee3f75babf7a222fde0

I did not review the aarch64/arm changes very thoroughly (patches 19-23),
but the rest all look fine to me aside from the one comment I had on
patch 18.

(So to be clear, you can add my Reviewed-by on all of 1-18.) Looks like
Luis is helping to validate the arm changes.

I certainly have a use case for this for CHERI support where GPRs are
also extended (so ideally I'd like to treat the 64-bit GPRs as pseudos
of the 129-bit capability registers), and also for Morello in particular
where the stack pointer is banked in userland and can vary by stack
frame depending on a permission in the PC as to which real register it
maps on to.

--
John Baldwin