From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id KQmDJyepP2VurjoAWB0awg (envelope-from ) for ; Mon, 30 Oct 2023 09:01:27 -0400 Authentication-Results: simark.ca; dkim=pass (2048-bit key; unprotected) header.d=imgtec.com header.i=@imgtec.com header.a=rsa-sha256 header.s=dk201812 header.b=BJjTEOsO; dkim-atps=neutral Received: by simark.ca (Postfix, from userid 112) id 9510B1E098; Mon, 30 Oct 2023 09:01:27 -0400 (EDT) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 4A1721E098 for ; Mon, 30 Oct 2023 09:01:25 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 645FE385B53E for ; Mon, 30 Oct 2023 13:01:24 +0000 (GMT) Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) by sourceware.org (Postfix) with ESMTPS id 6F4853858D28 for ; Mon, 30 Oct 2023 13:01:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6F4853858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=imgtec.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=imgtec.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 6F4853858D28 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=185.132.180.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698670873; cv=none; b=D+X0RUJi8gLwvNFzIFripYUa+HuwJgc20gx1o0ovaTuwMxsthy+dzto4+jliWTz8NsZflZcNaXiGHZYTDrxHV0iUxEClv4/per6JjWW/0z3pK0G0IXpL9LMLYGW2wV6bp/3bw+ZhpfQERU36cxYCejGy9dfVYR8lJm7cK0YRAZg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698670873; c=relaxed/simple; bh=TOcXPEfFpR84+vwlQuiiaew2FVniTDumU/IeF7t2+tg=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=CzfxwxbimJs9c9uXKGogcT4dhlWuQpOlhqtS/twUxAa0c+q1KO6shWgNsy7GS8bi5fsLlpe1apltkwhxWDPH3eRwyDXymJ3pRhFw1tI+5EfjWUUKqb2r0Du127WSFApJ01vLb/6P06hJaNT5LlQJt6JPLjCLaWy/3MqFz2LDGvM= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0168889.ppops.net [127.0.0.1]) by mx07-00376f01.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 39U6hUSh026687; Mon, 30 Oct 2023 13:00:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h= from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding:content-type; s=dk201812; bh=I4ghtBYs +V9NQbYwPiY/ClO0GR/oVYO9n1IKzvZXygs=; b=BJjTEOsOS6DuZ5sEmt2rvlBT L0YqSJL3PzacTkNPm0wwK4bJgc6YttbX/0D/FkW8sps7VUos0V+xpuYqYxIKQR/q gog9MmoQovXzJbwjPExd1+8nf9oAGgwf9t2+vuTw+V6B9iCuBgjy2bqSRs1VxpCC RHhC9HFieRTCkpECARx6xDwWqYyERAQCI8mKD82vXhkmu161BtvZo0swEX3WeRRO p1iAfYfo2ImsAZTMeXqy5TjAe7j9ap8Kv9xo03fXc3QIoB87SSRrQsIdq5XnJR3i tOVB4VomSfgRcIe62rKXEb9jd+3rBvnrEmXooWdIxQUSNnBq/pjXjXgI1r+ujw== Received: from hhmail04.hh.imgtec.org ([217.156.249.195]) by mx07-00376f01.pphosted.com (PPS) with ESMTPS id 3u0tcrhh37-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Mon, 30 Oct 2023 13:00:55 +0000 (GMT) Received: from hhjpatil.hh.imgtec.org (10.100.136.70) by HHMAIL04.hh.imgtec.org (10.100.10.119) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Mon, 30 Oct 2023 13:00:53 +0000 From: To: CC: , , , , Subject: [PATCH v2 0/3] sim: riscv: Compressed instruction simulation and semi-hosting support Date: Mon, 30 Oct 2023 13:00:39 +0000 Message-ID: <20231030130042.1472535-1-jaydeep.patil@imgtec.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.100.136.70] X-ClientProxiedBy: HHMAIL04.hh.imgtec.org (10.100.10.119) To HHMAIL04.hh.imgtec.org (10.100.10.119) X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-GUID: nhXX-F0m24J04jzMEt1mktzNwnrZTNw4 X-Proofpoint-ORIG-GUID: nhXX-F0m24J04jzMEt1mktzNwnrZTNw4 X-Spam-Status: No, score=-5.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org From: Jaydeep Patil Hi Andrew, Addressed review comments. Simulator specific tests are added in sim/testsuite/riscv/c-ext.s file. This is a collection of patches that add simulation of compressed integer instruction set ("c") and semi-hosting support to the RISC-V simulator. Two tests are added in gdb.arch to test basic semi-hosting and then the simulation of compressed integer instructions. Patch #1 adds basic semi-hosting support (OPEN, EXIT and GET_CMDLINE) and gdb.arch/riscv-exit-getcmd.c test Patch #2 adds support for compressed integer instruction set ("c") and gdb.arch/riscv-insn-simulation.c and sim/testsuite/riscv/c-ext.s tests Patch #3 adds support for remaining semi-hosting calls Contributions from: Joseph Faulls (Joseph.Faulls@imgtec.com) Jaydeep Patil (Jaydeep.Patil@imgtec.com) Bhushan Attarde (Bhushan.Attarde@imgtec.com) Jaydeep Patil (3): [sim/riscv] Add basic semi-hosting support [sim/riscv] Add support for compressed integer instruction set [sim/riscv] Add semi-hosting support gdb/testsuite/gdb.arch/riscv-exit-getcmd.c | 26 + gdb/testsuite/gdb.arch/riscv-exit-getcmd.exp | 27 + .../gdb.arch/riscv-insn-simulation.c | 1542 +++++++++++++++++ .../gdb.arch/riscv-insn-simulation.exp | 32 + sim/riscv/riscv-sim.h | 57 + sim/riscv/sim-main.c | 1050 ++++++++++- sim/testsuite/riscv/c-ext.s | 110 ++ 7 files changed, 2829 insertions(+), 15 deletions(-) create mode 100644 gdb/testsuite/gdb.arch/riscv-exit-getcmd.c create mode 100644 gdb/testsuite/gdb.arch/riscv-exit-getcmd.exp create mode 100755 gdb/testsuite/gdb.arch/riscv-insn-simulation.c create mode 100755 gdb/testsuite/gdb.arch/riscv-insn-simulation.exp create mode 100644 sim/testsuite/riscv/c-ext.s -- 2.25.1